7 files changed, 117 insertions, 44 deletions

diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
new file mode 100644
index 000000000000..ed2e95d46e29
--- /dev/null
+++ b/arch/arm/include/asm/arch_timer.h
@@ -0,0 +1,19 @@
+#ifndef __ASMARM_ARCH_TIMER_H
+#define __ASMARM_ARCH_TIMER_H
+
+#ifdef CONFIG_ARM_ARCH_TIMER
+int arch_timer_of_register(void);
+int arch_timer_sched_clock_init(void);
+#else
+static inline int arch_timer_of_register(void)
+{
+        return -ENXIO;
+}
+
+static inline int arch_timer_sched_clock_init(void)
+{
+        return -ENXIO;
+}
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 73f84fa4f366..d36a73d7c0e8 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -110,6 +110,6 @@ extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
 extern void it8152_init_irq(void);
 extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
+extern struct pci_ops it8152_ops;
 
 #endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index d943b7d20f11..26c511fddf8f 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -12,13 +12,14 @@
 #define __ASM_MACH_PCI_H
 
 struct pci_sys_data;
+struct pci_ops;
 struct pci_bus;
 
 struct hw_pci {
 #ifdef CONFIG_PCI_DOMAINS
         int             domain;
 #endif
-        struct list_head buses;
+        struct pci_ops  *ops;
         int             nr_controllers;
         int             (*setup)(int nr, struct pci_sys_data *);
         struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
@@ -45,16 +46,10 @@ struct pci_sys_data {
         u8              (*swizzle)(struct pci_dev *, u8 *);
                                         /* IRQ mapping                          */
         int             (*map_irq)(const struct pci_dev *, u8, u8);
-        struct hw_pci   *hw;
         void            *private_data;  /* platform controller private data     */
 };
 
 /*
- * This is the standard PCI-PCI bridge swizzling algorithm.
- */
-#define pci_std_swizzle pci_common_swizzle
-
-/*
  * Call this with your hw_pci struct to initialise the PCI system.
  */
 void pci_common_init(struct hw_pci *);
@@ -62,22 +57,22 @@ void pci_common_init(struct hw_pci *);
 /*
  * PCI controllers
  */
+extern struct pci_ops iop3xx_ops;
 extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
 extern void iop3xx_pci_preinit(void);
 extern void iop3xx_pci_preinit_cond(void);
 
+extern struct pci_ops dc21285_ops;
 extern int dc21285_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
 extern void dc21285_preinit(void);
 extern void dc21285_postinit(void);
 
+extern struct pci_ops via82c505_ops;
 extern int via82c505_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *);
 extern void via82c505_init(void *sysdata);
 
+extern struct pci_ops pci_v3_ops;
 extern int pci_v3_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *);
 extern void pci_v3_preinit(void);
 extern void pci_v3_postinit(void);
 
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index b8e580a297e4..14965658a923 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -34,11 +34,4 @@ typedef struct {
 
 #endif
 
-/*
- * switch_mm() may do a full cache flush over the context switch,
- * so enable interrupts over the context switch to avoid high
- * latency.
- */
-#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
-
 #endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a0b3cac0547c..0306bc642c0d 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -43,45 +43,104 @@ void __check_kvm_seq(struct mm_struct *mm);
 #define ASID_FIRST_VERSION      (1 << ASID_BITS)
 
 extern unsigned int cpu_last_asid;
-#ifdef CONFIG_SMP
-DECLARE_PER_CPU(struct mm_struct *, current_mm);
-#endif
 
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 void __new_context(struct mm_struct *mm);
+void cpu_set_reserved_ttbr0(void);
 
-static inline void check_context(struct mm_struct *mm)
+static inline void switch_new_context(struct mm_struct *mm)
 {
-        /*
-         * This code is executed with interrupts enabled. Therefore,
-         * mm->context.id cannot be updated to the latest ASID version
-         * on a different CPU (and condition below not triggered)
-         * without first getting an IPI to reset the context. The
-         * alternative is to take a read_lock on mm->context.id_lock
-         * (after changing its type to rwlock_t).
-         */
-        if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
-                __new_context(mm);
+        unsigned long flags;
+
+        __new_context(mm);
+
+        local_irq_save(flags);
+        cpu_switch_mm(mm->pgd, mm);
+        local_irq_restore(flags);
+}
 
+static inline void check_and_switch_context(struct mm_struct *mm,
+                                            struct task_struct *tsk)
+{
         if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                 __check_kvm_seq(mm);
+
+        /*
+         * Required during context switch to avoid speculative page table
+         * walking with the wrong TTBR.
+         */
+        cpu_set_reserved_ttbr0();
+
+        if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
+                /*
+                 * The ASID is from the current generation, just switch to the
+                 * new pgd. This condition is only true for calls from
+                 * context_switch() and interrupts are already disabled.
+                 */
+                cpu_switch_mm(mm->pgd, mm);
+        else if (irqs_disabled())
+                /*
+                 * Defer the new ASID allocation until after the context
+                 * switch critical region since __new_context() cannot be
+                 * called with interrupts disabled (it sends IPIs).
+                 */
+                set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+        else
+                /*
+                 * That is a direct call to switch_mm() or activate_mm() with
+                 * interrupts enabled and a new context.
+                 */
+                switch_new_context(mm);
 }
 
 #define init_new_context(tsk,mm)        (__init_new_context(tsk,mm),0)
 
-#else
-
-static inline void check_context(struct mm_struct *mm)
+#define finish_arch_post_lock_switch \
+        finish_arch_post_lock_switch
+static inline void finish_arch_post_lock_switch(void)
 {
+        if (test_and_clear_thread_flag(TIF_SWITCH_MM))
+                switch_new_context(current->mm);
+}
+
+#else   /* !CONFIG_CPU_HAS_ASID */
+
 #ifdef CONFIG_MMU
+
+static inline void check_and_switch_context(struct mm_struct *mm,
+                                            struct task_struct *tsk)
+{
         if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                 __check_kvm_seq(mm);
-#endif
+
+        if (irqs_disabled())
+                /*
+                 * cpu_switch_mm() needs to flush the VIVT caches. To avoid
+                 * high interrupt latencies, defer the call and continue
+                 * running with the old mm. Since we only support UP systems
+                 * on non-ASID CPUs, the old mm will remain valid until the
+                 * finish_arch_post_lock_switch() call.
+                 */
+                set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+        else
+                cpu_switch_mm(mm->pgd, mm);
 }
 
+#define finish_arch_post_lock_switch \
+        finish_arch_post_lock_switch
+static inline void finish_arch_post_lock_switch(void)
+{
+        if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
+                struct mm_struct *mm = current->mm;
+                cpu_switch_mm(mm->pgd, mm);
+        }
+}
+
+#endif  /* CONFIG_MMU */
+
 #define init_new_context(tsk,mm)        0
 
-#endif
+#endif  /* CONFIG_CPU_HAS_ASID */
 
 #define destroy_context(mm)             do { } while(0)
 
@@ -119,12 +178,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                 __flush_icache_all();
 #endif
         if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
-#ifdef CONFIG_SMP
-                struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
-                *crt_mm = next;
-#endif
-                check_context(next);
-                cpu_switch_mm(next->pgd, next);
+                check_and_switch_context(next, tsk);
                 if (cache_is_vivt())
                         cpumask_clear_cpu(cpu, mm_cpumask(prev));
         }
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d412a8d..68388eb4946b 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
 extern void vfp_sync_hwstate(struct thread_info *);
 extern void vfp_flush_hwstate(struct thread_info *);
 
+struct user_vfp;
+struct user_vfp_exc;
+
+extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
+                                           struct user_vfp_exc __user *);
+extern int vfp_restore_user_hwstate(struct user_vfp __user *,
+                                    struct user_vfp_exc __user *);
 #endif
 
 /*
@@ -146,6 +153,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     20
 #define TIF_SECCOMP             21
+#define TIF_SWITCH_MM           22      /* deferred switch_mm */
 
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 60843eb0f61c..73409e6c0251 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -7,6 +7,8 @@
 
         .macro set_tls_v6k, tp, tmp1, tmp2
         mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+        mov     \tmp1, #0
+        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         .endm
 
         .macro set_tls_v6, tp, tmp1, tmp2
@@ -15,6 +17,8 @@
         mov     \tmp2, #0xffff0fff
         tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
         mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        movne   \tmp1, #0
+        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
         .endm