1 files changed, 191 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
new file mode 100644
index 000000000000..04ad47876be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
+* Clock bindings for Freescale i.MX5
+Required properties:
+- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX5
+clocks and IDs.
+        Clock                   ID
+        ---------------------------
+        dummy                   0
+        ckil                    1
+        osc                     2
+        ckih1                   3
+        ckih2                   4
+        ahb                     5
+        ipg                     6
+        axi_a                   7
+        axi_b                   8
+        uart_pred               9
+        uart_root               10
+        esdhc_a_pred            11
+        esdhc_b_pred            12
+        esdhc_c_s               13
+        esdhc_d_s               14
+        emi_sel                 15
+        emi_slow_podf           16
+        nfc_podf                17
+        ecspi_pred              18
+        ecspi_podf              19
+        usboh3_pred             20
+        usboh3_podf             21
+        usb_phy_pred            22
+        usb_phy_podf            23
+        cpu_podf                24
+        di_pred                 25
+        tve_di                  26
+        tve_s                   27
+        uart1_ipg_gate          28
+        uart1_per_gate          29
+        uart2_ipg_gate          30
+        uart2_per_gate          31
+        uart3_ipg_gate          32
+        uart3_per_gate          33
+        i2c1_gate               34
+        i2c2_gate               35
+        gpt_ipg_gate            36
+        pwm1_ipg_gate           37
+        pwm1_hf_gate            38
+        pwm2_ipg_gate           39
+        pwm2_hf_gate            40
+        gpt_hf_gate             41
+        fec_gate                42
+        usboh3_per_gate         43
+        esdhc1_ipg_gate         44
+        esdhc2_ipg_gate         45
+        esdhc3_ipg_gate         46
+        esdhc4_ipg_gate         47
+        ssi1_ipg_gate           48
+        ssi2_ipg_gate           49
+        ssi3_ipg_gate           50
+        ecspi1_ipg_gate         51
+        ecspi1_per_gate         52
+        ecspi2_ipg_gate         53
+        ecspi2_per_gate         54
+        cspi_ipg_gate           55
+        sdma_gate               56
+        emi_slow_gate           57
+        ipu_s                   58
+        ipu_gate                59
+        nfc_gate                60
+        ipu_di1_gate            61
+        vpu_s                   62
+        vpu_gate                63
+        vpu_reference_gate      64
+        uart4_ipg_gate          65
+        uart4_per_gate          66
+        uart5_ipg_gate          67
+        uart5_per_gate          68
+        tve_gate                69
+        tve_pred                70
+        esdhc1_per_gate         71
+        esdhc2_per_gate         72
+        esdhc3_per_gate         73
+        esdhc4_per_gate         74
+        usb_phy_gate            75
+        hsi2c_gate              76
+        mipi_hsc1_gate          77
+        mipi_hsc2_gate          78
+        mipi_esc_gate           79
+        mipi_hsp_gate           80
+        ldb_di1_div_3_5         81
+        ldb_di1_div             82
+        ldb_di0_div_3_5         83
+        ldb_di0_div             84
+        ldb_di1_gate            85
+        can2_serial_gate        86
+        can2_ipg_gate           87
+        i2c3_gate               88
+        lp_apm                  89
+        periph_apm              90
+        main_bus                91
+        ahb_max                 92
+        aips_tz1                93
+        aips_tz2                94
+        tmax1                   95
+        tmax2                   96
+        tmax3                   97
+        spba                    98
+        uart_sel                99
+        esdhc_a_sel             100
+        esdhc_b_sel             101
+        esdhc_a_podf            102
+        esdhc_b_podf            103
+        ecspi_sel               104
+        usboh3_sel              105
+        usb_phy_sel             106
+        iim_gate                107
+        usboh3_gate             108
+        emi_fast_gate           109
+        ipu_di0_gate            110
+        gpc_dvfs                111
+        pll1_sw                 112
+        pll2_sw                 113
+        pll3_sw                 114
+        ipu_di0_sel             115
+        ipu_di1_sel             116
+        tve_ext_sel             117
+        mx51_mipi               118
+        pll4_sw                 119
+        ldb_di1_sel             120
+        di_pll4_podf            121
+        ldb_di0_sel             122
+        ldb_di0_gate            123
+        usb_phy1_gate           124
+        usb_phy2_gate           125
+        per_lp_apm              126
+        per_pred1               127
+        per_pred2               128
+        per_podf                129
+        per_root                130
+        ssi_apm                 131
+        ssi1_root_sel           132
+        ssi2_root_sel           133
+        ssi3_root_sel           134
+        ssi_ext1_sel            135
+        ssi_ext2_sel            136
+        ssi_ext1_com_sel        137
+        ssi_ext2_com_sel        138
+        ssi1_root_pred          139
+        ssi1_root_podf          140
+        ssi2_root_pred          141
+        ssi2_root_podf          142
+        ssi_ext1_pred           143
+        ssi_ext1_podf           144
+        ssi_ext2_pred           145
+        ssi_ext2_podf           146
+        ssi1_root_gate          147
+        ssi2_root_gate          148
+        ssi3_root_gate          149
+        ssi_ext1_gate           150
+        ssi_ext2_gate           151
+        epit1_ipg_gate          152
+        epit1_hf_gate           153
+        epit2_ipg_gate          154
+        epit2_hf_gate           155
+        can_sel                 156
+        can1_serial_gate        157
+        can1_ipg_gate           158
+Examples (for mx53):
+clks: ccm@53fd4000{
+        compatible = "fsl,imx53-ccm";
+        reg = <0x53fd4000 0x4000>;
+        interrupts = <0 71 0x04 0 72 0x04>;
+        #clock-cells = <1>;
+};
+can1: can@53fc8000 {
+        compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+        reg = <0x53fc8000 0x4000>;
+        interrupts = <82>;
+        clocks = <&clks 158>, <&clks 157>;
+        clock-names = "ipg", "per";
+        status = "disabled";
+};

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt new file mode 100644 index 000000000000..04ad47876be0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
	1	* Clock bindings for Freescale i.MX5
	2
	3	Required properties:
	4	- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
	5	- reg: Address and length of the register set
	6	- interrupts: Should contain CCM interrupt
	7	- #clock-cells: Should be <1>
	8
	9	The clock consumer should specify the desired clock by having the clock
	10	ID in its "clocks" phandle cell. The following is a full list of i.MX5
	11	clocks and IDs.
	12
	13	Clock ID
	14	---------------------------
	15	dummy 0
	16	ckil 1
	17	osc 2
	18	ckih1 3
	19	ckih2 4
	20	ahb 5
	21	ipg 6
	22	axi_a 7
	23	axi_b 8
	24	uart_pred 9
	25	uart_root 10
	26	esdhc_a_pred 11
	27	esdhc_b_pred 12
	28	esdhc_c_s 13
	29	esdhc_d_s 14
	30	emi_sel 15
	31	emi_slow_podf 16
	32	nfc_podf 17
	33	ecspi_pred 18
	34	ecspi_podf 19
	35	usboh3_pred 20
	36	usboh3_podf 21
	37	usb_phy_pred 22
	38	usb_phy_podf 23
	39	cpu_podf 24
	40	di_pred 25
	41	tve_di 26
	42	tve_s 27
	43	uart1_ipg_gate 28
	44	uart1_per_gate 29
	45	uart2_ipg_gate 30
	46	uart2_per_gate 31
	47	uart3_ipg_gate 32
	48	uart3_per_gate 33
	49	i2c1_gate 34
	50	i2c2_gate 35
	51	gpt_ipg_gate 36
	52	pwm1_ipg_gate 37
	53	pwm1_hf_gate 38
	54	pwm2_ipg_gate 39
	55	pwm2_hf_gate 40
	56	gpt_hf_gate 41
	57	fec_gate 42
	58	usboh3_per_gate 43
	59	esdhc1_ipg_gate 44
	60	esdhc2_ipg_gate 45
	61	esdhc3_ipg_gate 46
	62	esdhc4_ipg_gate 47
	63	ssi1_ipg_gate 48
	64	ssi2_ipg_gate 49
	65	ssi3_ipg_gate 50
	66	ecspi1_ipg_gate 51
	67	ecspi1_per_gate 52
	68	ecspi2_ipg_gate 53
	69	ecspi2_per_gate 54
	70	cspi_ipg_gate 55
	71	sdma_gate 56
	72	emi_slow_gate 57
	73	ipu_s 58
	74	ipu_gate 59
	75	nfc_gate 60
	76	ipu_di1_gate 61
	77	vpu_s 62
	78	vpu_gate 63
	79	vpu_reference_gate 64
	80	uart4_ipg_gate 65
	81	uart4_per_gate 66
	82	uart5_ipg_gate 67
	83	uart5_per_gate 68
	84	tve_gate 69
	85	tve_pred 70
	86	esdhc1_per_gate 71
	87	esdhc2_per_gate 72
	88	esdhc3_per_gate 73
	89	esdhc4_per_gate 74
	90	usb_phy_gate 75
	91	hsi2c_gate 76
	92	mipi_hsc1_gate 77
	93	mipi_hsc2_gate 78
	94	mipi_esc_gate 79
	95	mipi_hsp_gate 80
	96	ldb_di1_div_3_5 81
	97	ldb_di1_div 82
	98	ldb_di0_div_3_5 83
	99	ldb_di0_div 84
	100	ldb_di1_gate 85
	101	can2_serial_gate 86
	102	can2_ipg_gate 87
	103	i2c3_gate 88
	104	lp_apm 89
	105	periph_apm 90
	106	main_bus 91
	107	ahb_max 92
	108	aips_tz1 93
	109	aips_tz2 94
	110	tmax1 95
	111	tmax2 96
	112	tmax3 97
	113	spba 98
	114	uart_sel 99
	115	esdhc_a_sel 100
	116	esdhc_b_sel 101
	117	esdhc_a_podf 102
	118	esdhc_b_podf 103
	119	ecspi_sel 104
	120	usboh3_sel 105
	121	usb_phy_sel 106
	122	iim_gate 107
	123	usboh3_gate 108
	124	emi_fast_gate 109
	125	ipu_di0_gate 110
	126	gpc_dvfs 111
	127	pll1_sw 112
	128	pll2_sw 113
	129	pll3_sw 114
	130	ipu_di0_sel 115
	131	ipu_di1_sel 116
	132	tve_ext_sel 117
	133	mx51_mipi 118
	134	pll4_sw 119
	135	ldb_di1_sel 120
	136	di_pll4_podf 121
	137	ldb_di0_sel 122
	138	ldb_di0_gate 123
	139	usb_phy1_gate 124
	140	usb_phy2_gate 125
	141	per_lp_apm 126
	142	per_pred1 127
	143	per_pred2 128
	144	per_podf 129
	145	per_root 130
	146	ssi_apm 131
	147	ssi1_root_sel 132
	148	ssi2_root_sel 133
	149	ssi3_root_sel 134
	150	ssi_ext1_sel 135
	151	ssi_ext2_sel 136
	152	ssi_ext1_com_sel 137
	153	ssi_ext2_com_sel 138
	154	ssi1_root_pred 139
	155	ssi1_root_podf 140
	156	ssi2_root_pred 141
	157	ssi2_root_podf 142
	158	ssi_ext1_pred 143
	159	ssi_ext1_podf 144
	160	ssi_ext2_pred 145
	161	ssi_ext2_podf 146
	162	ssi1_root_gate 147
	163	ssi2_root_gate 148
	164	ssi3_root_gate 149
	165	ssi_ext1_gate 150
	166	ssi_ext2_gate 151
	167	epit1_ipg_gate 152
	168	epit1_hf_gate 153
	169	epit2_ipg_gate 154
	170	epit2_hf_gate 155
	171	can_sel 156
	172	can1_serial_gate 157
	173	can1_ipg_gate 158
	174
	175	Examples (for mx53):
	176
	177	clks: ccm@53fd4000{
	178	compatible = "fsl,imx53-ccm";
	179	reg = <0x53fd4000 0x4000>;
	180	interrupts = <0 71 0x04 0 72 0x04>;
	181	#clock-cells = <1>;
	182	};
	183
	184	can1: can@53fc8000 {
	185	compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
	186	reg = <0x53fc8000 0x4000>;
	187	interrupts = <82>;
	188	clocks = <&clks 158>, <&clks 157>;
	189	clock-names = "ipg", "per";
	190	status = "disabled";
	191	};