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-rw-r--r--drivers/net/netxen/netxen_nic.h65
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c12
-rw-r--r--drivers/net/netxen/netxen_nic_hdr.h242
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c65
-rw-r--r--drivers/net/netxen/netxen_nic_init.c3
-rw-r--r--drivers/net/netxen/netxen_nic_main.c6
-rw-r--r--drivers/net/netxen/netxen_nic_phan_reg.h8
7 files changed, 331 insertions, 70 deletions
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index fa1fbab65621..acc7d79457d6 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -111,6 +111,13 @@
111 111
112#define NX_P2_C0 0x24 112#define NX_P2_C0 0x24
113#define NX_P2_C1 0x25 113#define NX_P2_C1 0x25
114#define NX_P3_A0 0x30
115#define NX_P3_A2 0x30
116#define NX_P3_B0 0x40
117#define NX_P3_B1 0x41
118
119#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
120#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
114 121
115#define FIRST_PAGE_GROUP_START 0 122#define FIRST_PAGE_GROUP_START 0
116#define FIRST_PAGE_GROUP_END 0x100000 123#define FIRST_PAGE_GROUP_END 0x100000
@@ -125,6 +132,15 @@
125#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START 132#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
126#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START 133#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
127 134
135#define P2_MAX_MTU (8000)
136#define P3_MAX_MTU (9600)
137#define NX_ETHERMTU 1500
138#define NX_MAX_ETHERHDR 32 /* This contains some padding */
139
140#define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
141#define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
142#define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
143
128#define MAX_RX_BUFFER_LENGTH 1760 144#define MAX_RX_BUFFER_LENGTH 1760
129#define MAX_RX_JUMBO_BUFFER_LENGTH 8062 145#define MAX_RX_JUMBO_BUFFER_LENGTH 8062
130#define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512) 146#define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
@@ -139,16 +155,16 @@
139#define MAX_RING_CTX 1 155#define MAX_RING_CTX 1
140 156
141/* Opcodes to be used with the commands */ 157/* Opcodes to be used with the commands */
142enum { 158#define TX_ETHER_PKT 0x01
143 TX_ETHER_PKT = 0x01, 159#define TX_TCP_PKT 0x02
144/* The following opcodes are for IP checksum */ 160#define TX_UDP_PKT 0x03
145 TX_TCP_PKT, 161#define TX_IP_PKT 0x04
146 TX_UDP_PKT, 162#define TX_TCP_LSO 0x05
147 TX_IP_PKT, 163#define TX_TCP_LSO6 0x06
148 TX_TCP_LSO, 164#define TX_IPSEC 0x07
149 TX_IPSEC, 165#define TX_IPSEC_CMD 0x0a
150 TX_IPSEC_CMD 166#define TX_TCPV6_PKT 0x0b
151}; 167#define TX_UDPV6_PKT 0x0c
152 168
153/* The following opcodes are for internal consumption. */ 169/* The following opcodes are for internal consumption. */
154#define NETXEN_CONTROL_OP 0x10 170#define NETXEN_CONTROL_OP 0x10
@@ -190,6 +206,7 @@ enum {
190#define MAX_RCV_DESCRIPTORS 16384 206#define MAX_RCV_DESCRIPTORS 16384
191#define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4) 207#define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4)
192#define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4) 208#define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4)
209#define MAX_RCV_DESCRIPTORS_10G 8192
193#define MAX_JUMBO_RCV_DESCRIPTORS 1024 210#define MAX_JUMBO_RCV_DESCRIPTORS 1024
194#define MAX_LRO_RCV_DESCRIPTORS 64 211#define MAX_LRO_RCV_DESCRIPTORS 64
195#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS 212#define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
@@ -461,7 +478,20 @@ typedef enum {
461 478
462 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d, 479 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
463 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e, 480 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
464 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f 481 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
482
483 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
484 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
485 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
486 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
487 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
488 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
489 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
490 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
491 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
492 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
493 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032
494
465} netxen_brdtype_t; 495} netxen_brdtype_t;
466 496
467typedef enum { 497typedef enum {
@@ -1049,7 +1079,7 @@ struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1049 * NetXen Board information 1079 * NetXen Board information
1050 */ 1080 */
1051 1081
1052#define NETXEN_MAX_SHORT_NAME 16 1082#define NETXEN_MAX_SHORT_NAME 32
1053struct netxen_brdinfo { 1083struct netxen_brdinfo {
1054 netxen_brdtype_t brdtype; /* type of board */ 1084 netxen_brdtype_t brdtype; /* type of board */
1055 long ports; /* max no of physical ports */ 1085 long ports; /* max no of physical ports */
@@ -1063,6 +1093,17 @@ static const struct netxen_brdinfo netxen_boards[] = {
1063 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, 1093 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1064 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, 1094 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1065 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, 1095 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1096 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1097 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1098 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1099 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1100 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1101 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1102 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1103 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1104 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "Quad GB - March Madness"},
1105 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1106 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1066}; 1107};
1067 1108
1068#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) 1109#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index 99071c253766..cacc5280605e 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -159,9 +159,16 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
159 switch ((netxen_brdtype_t) boardinfo->board_type) { 159 switch ((netxen_brdtype_t) boardinfo->board_type) {
160 case NETXEN_BRDTYPE_P2_SB35_4G: 160 case NETXEN_BRDTYPE_P2_SB35_4G:
161 case NETXEN_BRDTYPE_P2_SB31_2G: 161 case NETXEN_BRDTYPE_P2_SB31_2G:
162 case NETXEN_BRDTYPE_P3_REF_QG:
163 case NETXEN_BRDTYPE_P3_4_GB:
164 case NETXEN_BRDTYPE_P3_4_GB_MM:
165 case NETXEN_BRDTYPE_P3_10000_BASE_T:
166
162 ecmd->supported |= SUPPORTED_Autoneg; 167 ecmd->supported |= SUPPORTED_Autoneg;
163 ecmd->advertising |= ADVERTISED_Autoneg; 168 ecmd->advertising |= ADVERTISED_Autoneg;
164 case NETXEN_BRDTYPE_P2_SB31_10G_CX4: 169 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
170 case NETXEN_BRDTYPE_P3_10G_CX4:
171 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
165 ecmd->supported |= SUPPORTED_TP; 172 ecmd->supported |= SUPPORTED_TP;
166 ecmd->advertising |= ADVERTISED_TP; 173 ecmd->advertising |= ADVERTISED_TP;
167 ecmd->port = PORT_TP; 174 ecmd->port = PORT_TP;
@@ -171,12 +178,17 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
171 break; 178 break;
172 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: 179 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
173 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: 180 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
181 case NETXEN_BRDTYPE_P3_IMEZ:
182 case NETXEN_BRDTYPE_P3_XG_LOM:
183 case NETXEN_BRDTYPE_P3_HMEZ:
174 ecmd->supported |= SUPPORTED_MII; 184 ecmd->supported |= SUPPORTED_MII;
175 ecmd->advertising |= ADVERTISED_MII; 185 ecmd->advertising |= ADVERTISED_MII;
176 ecmd->port = PORT_FIBRE; 186 ecmd->port = PORT_FIBRE;
177 ecmd->autoneg = AUTONEG_DISABLE; 187 ecmd->autoneg = AUTONEG_DISABLE;
178 break; 188 break;
179 case NETXEN_BRDTYPE_P2_SB31_10G: 189 case NETXEN_BRDTYPE_P2_SB31_10G:
190 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
191 case NETXEN_BRDTYPE_P3_10G_XFP:
180 ecmd->supported |= SUPPORTED_FIBRE; 192 ecmd->supported |= SUPPORTED_FIBRE;
181 ecmd->advertising |= ADVERTISED_FIBRE; 193 ecmd->advertising |= ADVERTISED_FIBRE;
182 ecmd->port = PORT_FIBRE; 194 ecmd->port = PORT_FIBRE;
diff --git a/drivers/net/netxen/netxen_nic_hdr.h b/drivers/net/netxen/netxen_nic_hdr.h
index 545180bf3be8..2374d8dc6cfe 100644
--- a/drivers/net/netxen/netxen_nic_hdr.h
+++ b/drivers/net/netxen/netxen_nic_hdr.h
@@ -126,7 +126,8 @@ enum {
126 NETXEN_HW_PEGR0_CRB_AGT_ADR, 126 NETXEN_HW_PEGR0_CRB_AGT_ADR,
127 NETXEN_HW_PEGR1_CRB_AGT_ADR, 127 NETXEN_HW_PEGR1_CRB_AGT_ADR,
128 NETXEN_HW_PEGR2_CRB_AGT_ADR, 128 NETXEN_HW_PEGR2_CRB_AGT_ADR,
129 NETXEN_HW_PEGR3_CRB_AGT_ADR 129 NETXEN_HW_PEGR3_CRB_AGT_ADR,
130 NETXEN_HW_PEGN4_CRB_AGT_ADR
130}; 131};
131 132
132/* Hub 5 */ 133/* Hub 5 */
@@ -316,6 +317,8 @@ enum {
316 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR) 317 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN2_CRB_AGT_ADR)
317#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \ 318#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN3 \
318 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR) 319 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN3_CRB_AGT_ADR)
320#define NETXEN_HW_CRB_HUB_AGT_ADR_PGN4 \
321 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGN4_CRB_AGT_ADR)
319#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \ 322#define NETXEN_HW_CRB_HUB_AGT_ADR_PGNC \
320 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR) 323 ((NETXEN_HW_H4_CH_HUB_ADR << 7) | NETXEN_HW_PEGNC_CRB_AGT_ADR)
321#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \ 324#define NETXEN_HW_CRB_HUB_AGT_ADR_PGR0 \
@@ -435,6 +438,7 @@ enum {
435#define NETXEN_CRB_ROMUSB \ 438#define NETXEN_CRB_ROMUSB \
436 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB) 439 NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_ROMUSB)
437#define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q) 440#define NETXEN_CRB_I2Q NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_I2Q)
441#define NETXEN_CRB_SMB NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SMB)
438#define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64) 442#define NETXEN_CRB_MAX NETXEN_PCI_CRB_WINDOW(64)
439 443
440#define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH) 444#define NETXEN_CRB_PCIX_HOST NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PH)
@@ -446,6 +450,7 @@ enum {
446#define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND) 450#define NETXEN_CRB_PEG_NET_D NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGND)
447#define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI) 451#define NETXEN_CRB_PEG_NET_I NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PGNI)
448#define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN) 452#define NETXEN_CRB_DDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_MN)
453#define NETXEN_CRB_QDR_NET NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_SN)
449 454
450#define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS) 455#define NETXEN_CRB_PCIX_MD NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_PS)
451#define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD 456#define NETXEN_CRB_PCIE NETXEN_CRB_PCIX_MD
@@ -461,11 +466,20 @@ enum {
461#define ISR_INT_TARGET_MASK_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 466#define ISR_INT_TARGET_MASK_F2 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
462#define ISR_INT_TARGET_STATUS_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 467#define ISR_INT_TARGET_STATUS_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
463#define ISR_INT_TARGET_MASK_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 468#define ISR_INT_TARGET_MASK_F3 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
469#define ISR_INT_TARGET_STATUS_F4 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
470#define ISR_INT_TARGET_MASK_F4 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
471#define ISR_INT_TARGET_STATUS_F5 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
472#define ISR_INT_TARGET_MASK_F5 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
473#define ISR_INT_TARGET_STATUS_F6 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
474#define ISR_INT_TARGET_MASK_F6 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
475#define ISR_INT_TARGET_STATUS_F7 (NETXEN_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
476#define ISR_INT_TARGET_MASK_F7 (NETXEN_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
464 477
465#define NETXEN_PCI_MAPSIZE 128 478#define NETXEN_PCI_MAPSIZE 128
466#define NETXEN_PCI_DDR_NET (0x00000000UL) 479#define NETXEN_PCI_DDR_NET (0x00000000UL)
467#define NETXEN_PCI_QDR_NET (0x04000000UL) 480#define NETXEN_PCI_QDR_NET (0x04000000UL)
468#define NETXEN_PCI_DIRECT_CRB (0x04400000UL) 481#define NETXEN_PCI_DIRECT_CRB (0x04400000UL)
482#define NETXEN_PCI_CAMQM (0x04800000UL)
469#define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL) 483#define NETXEN_PCI_CAMQM_MAX (0x04ffffffUL)
470#define NETXEN_PCI_OCM0 (0x05000000UL) 484#define NETXEN_PCI_OCM0 (0x05000000UL)
471#define NETXEN_PCI_OCM0_MAX (0x050fffffUL) 485#define NETXEN_PCI_OCM0_MAX (0x050fffffUL)
@@ -474,6 +488,13 @@ enum {
474#define NETXEN_PCI_CRBSPACE (0x06000000UL) 488#define NETXEN_PCI_CRBSPACE (0x06000000UL)
475#define NETXEN_PCI_128MB_SIZE (0x08000000UL) 489#define NETXEN_PCI_128MB_SIZE (0x08000000UL)
476#define NETXEN_PCI_32MB_SIZE (0x02000000UL) 490#define NETXEN_PCI_32MB_SIZE (0x02000000UL)
491#define NETXEN_PCI_2MB_SIZE (0x00200000UL)
492
493#define NETXEN_PCI_MN_2M (0)
494#define NETXEN_PCI_MS_2M (0x80000)
495#define NETXEN_PCI_OCM0_2M (0x000c0000UL)
496#define NETXEN_PCI_CAMQM_2M_BASE (0x000ff800UL)
497#define NETXEN_PCI_CAMQM_2M_END (0x04800800UL)
477 498
478#define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM) 499#define NETXEN_CRB_CAM NETXEN_PCI_CRB_WINDOW(NETXEN_HW_PX_MAP_CRB_CAM)
479 500
@@ -484,7 +505,14 @@ enum {
484#define NETXEN_ADDR_OCM1 (0x0000000200400000ULL) 505#define NETXEN_ADDR_OCM1 (0x0000000200400000ULL)
485#define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL) 506#define NETXEN_ADDR_OCM1_MAX (0x00000002004fffffULL)
486#define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL) 507#define NETXEN_ADDR_QDR_NET (0x0000000300000000ULL)
487#define NETXEN_ADDR_QDR_NET_MAX (0x00000003003fffffULL) 508#define NETXEN_ADDR_QDR_NET_MAX_P2 (0x00000003003fffffULL)
509#define NETXEN_ADDR_QDR_NET_MAX_P3 (0x0000000303ffffffULL)
510
511/*
512 * Register offsets for MN
513 */
514#define NETXEN_MIU_CONTROL (0x000)
515#define NETXEN_MIU_MN_CONTROL (NETXEN_CRB_DDR_NET+NETXEN_MIU_CONTROL)
488 516
489 /* 200ms delay in each loop */ 517 /* 200ms delay in each loop */
490#define NETXEN_NIU_PHY_WAITLEN 200000 518#define NETXEN_NIU_PHY_WAITLEN 200000
@@ -633,6 +661,59 @@ enum {
633#define NETXEN_NIU_XG1_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x80054) 661#define NETXEN_NIU_XG1_CONTROL_CHAR_CNT (NETXEN_CRB_NIU + 0x80054)
634#define NETXEN_NIU_XG1_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x80058) 662#define NETXEN_NIU_XG1_PAUSE_FRAME_CNT (NETXEN_CRB_NIU + 0x80058)
635 663
664/* P3 802.3ap */
665#define NETXEN_NIU_AP_MAC_CONFIG_0(I) (NETXEN_CRB_NIU+0xa0000+(I)*0x10000)
666#define NETXEN_NIU_AP_MAC_CONFIG_1(I) (NETXEN_CRB_NIU+0xa0004+(I)*0x10000)
667#define NETXEN_NIU_AP_MAC_IPG_IFG(I) (NETXEN_CRB_NIU+0xa0008+(I)*0x10000)
668#define NETXEN_NIU_AP_HALF_DUPLEX_CTRL(I) (NETXEN_CRB_NIU+0xa000c+(I)*0x10000)
669#define NETXEN_NIU_AP_MAX_FRAME_SIZE(I) (NETXEN_CRB_NIU+0xa0010+(I)*0x10000)
670#define NETXEN_NIU_AP_TEST_REG(I) (NETXEN_CRB_NIU+0xa001c+(I)*0x10000)
671#define NETXEN_NIU_AP_MII_MGMT_CONFIG(I) (NETXEN_CRB_NIU+0xa0020+(I)*0x10000)
672#define NETXEN_NIU_AP_MII_MGMT_COMMAND(I) (NETXEN_CRB_NIU+0xa0024+(I)*0x10000)
673#define NETXEN_NIU_AP_MII_MGMT_ADDR(I) (NETXEN_CRB_NIU+0xa0028+(I)*0x10000)
674#define NETXEN_NIU_AP_MII_MGMT_CTRL(I) (NETXEN_CRB_NIU+0xa002c+(I)*0x10000)
675#define NETXEN_NIU_AP_MII_MGMT_STATUS(I) (NETXEN_CRB_NIU+0xa0030+(I)*0x10000)
676#define NETXEN_NIU_AP_MII_MGMT_INDICATE(I) (NETXEN_CRB_NIU+0xa0034+(I)*0x10000)
677#define NETXEN_NIU_AP_INTERFACE_CTRL(I) (NETXEN_CRB_NIU+0xa0038+(I)*0x10000)
678#define NETXEN_NIU_AP_INTERFACE_STATUS(I) (NETXEN_CRB_NIU+0xa003c+(I)*0x10000)
679#define NETXEN_NIU_AP_STATION_ADDR_0(I) (NETXEN_CRB_NIU+0xa0040+(I)*0x10000)
680#define NETXEN_NIU_AP_STATION_ADDR_1(I) (NETXEN_CRB_NIU+0xa0044+(I)*0x10000)
681
682/*
683 * Register offsets for MN
684 */
685#define MIU_CONTROL (0x000)
686#define MIU_TEST_AGT_CTRL (0x090)
687#define MIU_TEST_AGT_ADDR_LO (0x094)
688#define MIU_TEST_AGT_ADDR_HI (0x098)
689#define MIU_TEST_AGT_WRDATA_LO (0x0a0)
690#define MIU_TEST_AGT_WRDATA_HI (0x0a4)
691#define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
692#define MIU_TEST_AGT_RDDATA_LO (0x0a8)
693#define MIU_TEST_AGT_RDDATA_HI (0x0ac)
694#define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
695#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
696#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
697
698/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
699#define MIU_TA_CTL_START 1
700#define MIU_TA_CTL_ENABLE 2
701#define MIU_TA_CTL_WRITE 4
702#define MIU_TA_CTL_BUSY 8
703
704#define SIU_TEST_AGT_CTRL (0x060)
705#define SIU_TEST_AGT_ADDR_LO (0x064)
706#define SIU_TEST_AGT_ADDR_HI (0x078)
707#define SIU_TEST_AGT_WRDATA_LO (0x068)
708#define SIU_TEST_AGT_WRDATA_HI (0x06c)
709#define SIU_TEST_AGT_WRDATA(i) (0x068+(4*(i)))
710#define SIU_TEST_AGT_RDDATA_LO (0x070)
711#define SIU_TEST_AGT_RDDATA_HI (0x074)
712#define SIU_TEST_AGT_RDDATA(i) (0x070+(4*(i)))
713
714#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
715#define SIU_TEST_AGT_UPPER_ADDR(off) ((off)>>22)
716
636/* XG Link status */ 717/* XG Link status */
637#define XG_LINK_UP 0x10 718#define XG_LINK_UP 0x10
638#define XG_LINK_DOWN 0x20 719#define XG_LINK_DOWN 0x20
@@ -643,6 +724,7 @@ enum {
643#define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154)) 724#define NETXEN_FW_VERSION_MINOR (NETXEN_CAM_RAM(0x154))
644#define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158)) 725#define NETXEN_FW_VERSION_SUB (NETXEN_CAM_RAM(0x158))
645#define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100)) 726#define NETXEN_ROM_LOCK_ID (NETXEN_CAM_RAM(0x100))
727#define NETXEN_CRB_WIN_LOCK_ID (NETXEN_CAM_RAM(0x124))
646 728
647#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120)) 729#define NETXEN_PHY_LOCK_ID (NETXEN_CAM_RAM(0x120))
648 730
@@ -657,30 +739,71 @@ enum {
657#define PCIX_INT_VECTOR (0x10100) 739#define PCIX_INT_VECTOR (0x10100)
658#define PCIX_INT_MASK (0x10104) 740#define PCIX_INT_MASK (0x10104)
659 741
660#define PCIX_MN_WINDOW_F0 (0x10200)
661#define PCIX_MN_WINDOW(_f) (PCIX_MN_WINDOW_F0 + (0x20 * (_f)))
662#define PCIX_MS_WINDOW (0x10204)
663#define PCIX_SN_WINDOW_F0 (0x10208)
664#define PCIX_SN_WINDOW(_f) (PCIX_SN_WINDOW_F0 + (0x20 * (_f)))
665#define PCIX_CRB_WINDOW (0x10210) 742#define PCIX_CRB_WINDOW (0x10210)
666#define PCIX_CRB_WINDOW_F0 (0x10210) 743#define PCIX_CRB_WINDOW_F0 (0x10210)
667#define PCIX_CRB_WINDOW_F1 (0x10230) 744#define PCIX_CRB_WINDOW_F1 (0x10230)
668#define PCIX_CRB_WINDOW_F2 (0x10250) 745#define PCIX_CRB_WINDOW_F2 (0x10250)
669#define PCIX_CRB_WINDOW_F3 (0x10270) 746#define PCIX_CRB_WINDOW_F3 (0x10270)
747#define PCIX_CRB_WINDOW_F4 (0x102ac)
748#define PCIX_CRB_WINDOW_F5 (0x102bc)
749#define PCIX_CRB_WINDOW_F6 (0x102cc)
750#define PCIX_CRB_WINDOW_F7 (0x102dc)
751#define PCIE_CRB_WINDOW_REG(func) (((func) < 4) ? \
752 (PCIX_CRB_WINDOW_F0 + (0x20 * (func))) :\
753 (PCIX_CRB_WINDOW_F4 + (0x10 * ((func)-4))))
754
755#define PCIX_MN_WINDOW (0x10200)
756#define PCIX_MN_WINDOW_F0 (0x10200)
757#define PCIX_MN_WINDOW_F1 (0x10220)
758#define PCIX_MN_WINDOW_F2 (0x10240)
759#define PCIX_MN_WINDOW_F3 (0x10260)
760#define PCIX_MN_WINDOW_F4 (0x102a0)
761#define PCIX_MN_WINDOW_F5 (0x102b0)
762#define PCIX_MN_WINDOW_F6 (0x102c0)
763#define PCIX_MN_WINDOW_F7 (0x102d0)
764#define PCIE_MN_WINDOW_REG(func) (((func) < 4) ? \
765 (PCIX_MN_WINDOW_F0 + (0x20 * (func))) :\
766 (PCIX_MN_WINDOW_F4 + (0x10 * ((func)-4))))
767
768#define PCIX_SN_WINDOW (0x10208)
769#define PCIX_SN_WINDOW_F0 (0x10208)
770#define PCIX_SN_WINDOW_F1 (0x10228)
771#define PCIX_SN_WINDOW_F2 (0x10248)
772#define PCIX_SN_WINDOW_F3 (0x10268)
773#define PCIX_SN_WINDOW_F4 (0x102a8)
774#define PCIX_SN_WINDOW_F5 (0x102b8)
775#define PCIX_SN_WINDOW_F6 (0x102c8)
776#define PCIX_SN_WINDOW_F7 (0x102d8)
777#define PCIE_SN_WINDOW_REG(func) (((func) < 4) ? \
778 (PCIX_SN_WINDOW_F0 + (0x20 * (func))) :\
779 (PCIX_SN_WINDOW_F4 + (0x10 * ((func)-4))))
670 780
671#define PCIX_TARGET_STATUS (0x10118) 781#define PCIX_TARGET_STATUS (0x10118)
782#define PCIX_TARGET_STATUS_F1 (0x10160)
783#define PCIX_TARGET_STATUS_F2 (0x10164)
784#define PCIX_TARGET_STATUS_F3 (0x10168)
785#define PCIX_TARGET_STATUS_F4 (0x10360)
786#define PCIX_TARGET_STATUS_F5 (0x10364)
787#define PCIX_TARGET_STATUS_F6 (0x10368)
788#define PCIX_TARGET_STATUS_F7 (0x1036c)
789
672#define PCIX_TARGET_MASK (0x10128) 790#define PCIX_TARGET_MASK (0x10128)
673#define PCIX_TARGET_STATUS_F1 (0x10160) 791#define PCIX_TARGET_MASK_F1 (0x10170)
674#define PCIX_TARGET_MASK_F1 (0x10170) 792#define PCIX_TARGET_MASK_F2 (0x10174)
675#define PCIX_TARGET_STATUS_F2 (0x10164) 793#define PCIX_TARGET_MASK_F3 (0x10178)
676#define PCIX_TARGET_MASK_F2 (0x10174) 794#define PCIX_TARGET_MASK_F4 (0x10370)
677#define PCIX_TARGET_STATUS_F3 (0x10168) 795#define PCIX_TARGET_MASK_F5 (0x10374)
678#define PCIX_TARGET_MASK_F3 (0x10178) 796#define PCIX_TARGET_MASK_F6 (0x10378)
797#define PCIX_TARGET_MASK_F7 (0x1037c)
679 798
680#define PCIX_MSI_F0 (0x13000) 799#define PCIX_MSI_F0 (0x13000)
681#define PCIX_MSI_F1 (0x13004) 800#define PCIX_MSI_F1 (0x13004)
682#define PCIX_MSI_F2 (0x13008) 801#define PCIX_MSI_F2 (0x13008)
683#define PCIX_MSI_F3 (0x1300c) 802#define PCIX_MSI_F3 (0x1300c)
803#define PCIX_MSI_F4 (0x13010)
804#define PCIX_MSI_F5 (0x13014)
805#define PCIX_MSI_F6 (0x13018)
806#define PCIX_MSI_F7 (0x1301c)
684#define PCIX_MSI_F(i) (0x13000+((i)*4)) 807#define PCIX_MSI_F(i) (0x13000+((i)*4))
685 808
686#define PCIX_PS_MEM_SPACE (0x90000) 809#define PCIX_PS_MEM_SPACE (0x90000)
@@ -698,11 +821,102 @@ enum {
698#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ 821#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
699#define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */ 822#define PCIE_SEM3_LOCK (0x1c018) /* Phy lock */
700#define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */ 823#define PCIE_SEM3_UNLOCK (0x1c01c) /* Phy unlock */
701 824#define PCIE_SEM5_LOCK (0x1c028) /* API lock */
825#define PCIE_SEM5_UNLOCK (0x1c02c) /* API unlock */
826#define PCIE_SEM6_LOCK (0x1c030) /* sw lock */
827#define PCIE_SEM6_UNLOCK (0x1c034) /* sw unlock */
828#define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
829#define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
830
831#define PCIE_SETUP_FUNCTION (0x12040)
832#define PCIE_SETUP_FUNCTION2 (0x12048)
702#define PCIE_TGT_SPLIT_CHICKEN (0x12080) 833#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
834#define PCIE_CHICKEN3 (0x120c8)
703 835
704#define PCIE_MAX_MASTER_SPLIT (0x14048) 836#define PCIE_MAX_MASTER_SPLIT (0x14048)
705 837
838#define NETXEN_PORT_MODE_NONE 0
839#define NETXEN_PORT_MODE_XG 1
840#define NETXEN_PORT_MODE_GB 2
841#define NETXEN_PORT_MODE_802_3_AP 3
842#define NETXEN_PORT_MODE_AUTO_NEG 4
843#define NETXEN_PORT_MODE_AUTO_NEG_1G 5
844#define NETXEN_PORT_MODE_AUTO_NEG_XG 6
845#define NETXEN_PORT_MODE_ADDR (NETXEN_CAM_RAM(0x24))
846#define NETXEN_WOL_PORT_MODE (NETXEN_CAM_RAM(0x198))
847
706#define NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL (0x14) 848#define NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL (0x14)
707 849
850#define ISR_MSI_INT_TRIGGER(FUNC) (NETXEN_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
851
852/*
853 * PCI Interrupt Vector Values.
854 */
855#define PCIX_INT_VECTOR_BIT_F0 0x0080
856#define PCIX_INT_VECTOR_BIT_F1 0x0100
857#define PCIX_INT_VECTOR_BIT_F2 0x0200
858#define PCIX_INT_VECTOR_BIT_F3 0x0400
859#define PCIX_INT_VECTOR_BIT_F4 0x0800
860#define PCIX_INT_VECTOR_BIT_F5 0x1000
861#define PCIX_INT_VECTOR_BIT_F6 0x2000
862#define PCIX_INT_VECTOR_BIT_F7 0x4000
863
864struct netxen_legacy_intr_set {
865 uint32_t int_vec_bit;
866 uint32_t tgt_status_reg;
867 uint32_t tgt_mask_reg;
868 uint32_t pci_int_reg;
869};
870
871#define NX_LEGACY_INTR_CONFIG \
872{ \
873 { \
874 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
875 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
876 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
877 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
878 \
879 { \
880 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
881 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
882 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
883 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
884 \
885 { \
886 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
887 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
888 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
889 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
890 \
891 { \
892 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
893 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
894 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
895 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
896 \
897 { \
898 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
899 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
900 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
901 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
902 \
903 { \
904 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
905 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
906 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
907 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
908 \
909 { \
910 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
911 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
912 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
913 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
914 \
915 { \
916 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
917 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
918 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
919 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
920}
921
708#endif /* __NETXEN_NIC_HDR_H_ */ 922#endif /* __NETXEN_NIC_HDR_H_ */
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 93466ec64074..a472873f48bd 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -609,33 +609,10 @@ void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
609 void __iomem *offset; 609 void __iomem *offset;
610 u32 tmp; 610 u32 tmp;
611 int count = 0; 611 int count = 0;
612 uint8_t func = adapter->ahw.pci_func;
612 613
613 if (adapter->curr_window == wndw) 614 if (adapter->curr_window == wndw)
614 return; 615 return;
615 switch(adapter->ahw.pci_func) {
616 case 0:
617 offset = PCI_OFFSET_SECOND_RANGE(adapter,
618 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
619 break;
620 case 1:
621 offset = PCI_OFFSET_SECOND_RANGE(adapter,
622 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
623 break;
624 case 2:
625 offset = PCI_OFFSET_SECOND_RANGE(adapter,
626 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
627 break;
628 case 3:
629 offset = PCI_OFFSET_SECOND_RANGE(adapter,
630 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
631 break;
632 default:
633 printk(KERN_INFO "Changing the window for PCI function "
634 "%d\n", adapter->ahw.pci_func);
635 offset = PCI_OFFSET_SECOND_RANGE(adapter,
636 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
637 break;
638 }
639 /* 616 /*
640 * Move the CRB window. 617 * Move the CRB window.
641 * We need to write to the "direct access" region of PCI 618 * We need to write to the "direct access" region of PCI
@@ -644,6 +621,8 @@ void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
644 * register address is received by PCI. The direct region bypasses 621 * register address is received by PCI. The direct region bypasses
645 * the CRB bus. 622 * the CRB bus.
646 */ 623 */
624 offset = PCI_OFFSET_SECOND_RANGE(adapter,
625 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
647 626
648 if (wndw & 0x1) 627 if (wndw & 0x1)
649 wndw = NETXEN_WINDOW_ONE; 628 wndw = NETXEN_WINDOW_ONE;
@@ -857,9 +836,11 @@ static int netxen_pci_set_window_warning_count;
857static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter, 836static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
858 unsigned long long addr) 837 unsigned long long addr)
859{ 838{
839 void __iomem *offset;
860 static int ddr_mn_window = -1; 840 static int ddr_mn_window = -1;
861 static int qdr_sn_window = -1; 841 static int qdr_sn_window = -1;
862 int window; 842 int window;
843 uint8_t func = adapter->ahw.pci_func;
863 844
864 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { 845 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
865 /* DDR network side */ 846 /* DDR network side */
@@ -867,13 +848,11 @@ static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
867 window = (addr >> 25) & 0x3ff; 848 window = (addr >> 25) & 0x3ff;
868 if (ddr_mn_window != window) { 849 if (ddr_mn_window != window) {
869 ddr_mn_window = window; 850 ddr_mn_window = window;
870 writel(window, PCI_OFFSET_SECOND_RANGE(adapter, 851 offset = PCI_OFFSET_SECOND_RANGE(adapter,
871 NETXEN_PCIX_PH_REG 852 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
872 (PCIX_MN_WINDOW(adapter->ahw.pci_func)))); 853 writel(window, offset);
873 /* MUST make sure window is set before we forge on... */ 854 /* MUST make sure window is set before we forge on... */
874 readl(PCI_OFFSET_SECOND_RANGE(adapter, 855 readl(offset);
875 NETXEN_PCIX_PH_REG
876 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
877 } 856 }
878 addr -= (window * NETXEN_WINDOW_ONE); 857 addr -= (window * NETXEN_WINDOW_ONE);
879 addr += NETXEN_PCI_DDR_NET; 858 addr += NETXEN_PCI_DDR_NET;
@@ -885,20 +864,17 @@ static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
885 addr += NETXEN_PCI_OCM1; 864 addr += NETXEN_PCI_OCM1;
886 } else 865 } else
887 if (ADDR_IN_RANGE 866 if (ADDR_IN_RANGE
888 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) { 867 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P2)) {
889 /* QDR network side */ 868 /* QDR network side */
890 addr -= NETXEN_ADDR_QDR_NET; 869 addr -= NETXEN_ADDR_QDR_NET;
891 window = (addr >> 22) & 0x3f; 870 window = (addr >> 22) & 0x3f;
892 if (qdr_sn_window != window) { 871 if (qdr_sn_window != window) {
893 qdr_sn_window = window; 872 qdr_sn_window = window;
894 writel((window << 22), 873 offset = PCI_OFFSET_SECOND_RANGE(adapter,
895 PCI_OFFSET_SECOND_RANGE(adapter, 874 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
896 NETXEN_PCIX_PH_REG 875 writel((window << 22), offset);
897 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
898 /* MUST make sure window is set before we forge on... */ 876 /* MUST make sure window is set before we forge on... */
899 readl(PCI_OFFSET_SECOND_RANGE(adapter, 877 readl(offset);
900 NETXEN_PCIX_PH_REG
901 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
902 } 878 }
903 addr -= (window * 0x400000); 879 addr -= (window * 0x400000);
904 addr += NETXEN_PCI_QDR_NET; 880 addr += NETXEN_PCI_QDR_NET;
@@ -972,12 +948,25 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
972 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: 948 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
973 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: 949 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
974 case NETXEN_BRDTYPE_P2_SB31_10G_CX4: 950 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
951 case NETXEN_BRDTYPE_P3_HMEZ:
952 case NETXEN_BRDTYPE_P3_XG_LOM:
953 case NETXEN_BRDTYPE_P3_10G_CX4:
954 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
955 case NETXEN_BRDTYPE_P3_IMEZ:
956 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
957 case NETXEN_BRDTYPE_P3_10G_XFP:
958 case NETXEN_BRDTYPE_P3_10000_BASE_T:
959
975 adapter->ahw.board_type = NETXEN_NIC_XGBE; 960 adapter->ahw.board_type = NETXEN_NIC_XGBE;
976 break; 961 break;
977 case NETXEN_BRDTYPE_P1_BD: 962 case NETXEN_BRDTYPE_P1_BD:
978 case NETXEN_BRDTYPE_P1_SB: 963 case NETXEN_BRDTYPE_P1_SB:
979 case NETXEN_BRDTYPE_P1_SMAX: 964 case NETXEN_BRDTYPE_P1_SMAX:
980 case NETXEN_BRDTYPE_P1_SOCK: 965 case NETXEN_BRDTYPE_P1_SOCK:
966 case NETXEN_BRDTYPE_P3_REF_QG:
967 case NETXEN_BRDTYPE_P3_4_GB:
968 case NETXEN_BRDTYPE_P3_4_GB_MM:
969
981 adapter->ahw.board_type = NETXEN_NIC_GBE; 970 adapter->ahw.board_type = NETXEN_NIC_GBE;
982 break; 971 break;
983 default: 972 default:
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index e35f1a4b4eb3..dfde59082096 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -115,6 +115,8 @@ static void crb_addr_transform_setup(void)
115 crb_addr_transform(C2C1); 115 crb_addr_transform(C2C1);
116 crb_addr_transform(C2C0); 116 crb_addr_transform(C2C0);
117 crb_addr_transform(SMB); 117 crb_addr_transform(SMB);
118 crb_addr_transform(OCM0);
119 crb_addr_transform(I2C0);
118} 120}
119 121
120int netxen_init_firmware(struct netxen_adapter *adapter) 122int netxen_init_firmware(struct netxen_adapter *adapter)
@@ -743,7 +745,6 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
743 NETXEN_ROMBUS_RESET); 745 NETXEN_ROMBUS_RESET);
744 746
745 if (verbose) { 747 if (verbose) {
746 int val;
747 if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0) 748 if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
748 printk("P2 ROM board type: 0x%08x\n", val); 749 printk("P2 ROM board type: 0x%08x\n", val);
749 else 750 else
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 0ec6e7ebf90f..192a22f89570 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -83,6 +83,7 @@ static struct pci_device_id netxen_pci_tbl[] __devinitdata = {
83 ENTRY(0x0005), 83 ENTRY(0x0005),
84 ENTRY(0x0024), 84 ENTRY(0x0024),
85 ENTRY(0x0025), 85 ENTRY(0x0025),
86 ENTRY(0x0100),
86 {0,} 87 {0,}
87}; 88};
88 89
@@ -526,7 +527,6 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
526 adapter->crb_addr_cmd_consumer = crb_cmd_consumer[adapter->portnum]; 527 adapter->crb_addr_cmd_consumer = crb_cmd_consumer[adapter->portnum];
527 netxen_nic_update_cmd_producer(adapter, 0); 528 netxen_nic_update_cmd_producer(adapter, 0);
528 netxen_nic_update_cmd_consumer(adapter, 0); 529 netxen_nic_update_cmd_consumer(adapter, 0);
529 writel(0, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
530 530
531 if (netxen_is_flash_supported(adapter) == 0 && 531 if (netxen_is_flash_supported(adapter) == 0 &&
532 netxen_get_flash_mac_addr(adapter, mac_addr) == 0) 532 netxen_get_flash_mac_addr(adapter, mac_addr) == 0)
@@ -1099,7 +1099,7 @@ netxen_handle_int(struct netxen_adapter *adapter)
1099 napi_schedule(&adapter->napi); 1099 napi_schedule(&adapter->napi);
1100} 1100}
1101 1101
1102irqreturn_t netxen_intr(int irq, void *data) 1102static irqreturn_t netxen_intr(int irq, void *data)
1103{ 1103{
1104 struct netxen_adapter *adapter = data; 1104 struct netxen_adapter *adapter = data;
1105 u32 our_int = 0; 1105 u32 our_int = 0;
@@ -1120,7 +1120,7 @@ irqreturn_t netxen_intr(int irq, void *data)
1120 return IRQ_HANDLED; 1120 return IRQ_HANDLED;
1121} 1121}
1122 1122
1123irqreturn_t netxen_msi_intr(int irq, void *data) 1123static irqreturn_t netxen_msi_intr(int irq, void *data)
1124{ 1124{
1125 struct netxen_adapter *adapter = data; 1125 struct netxen_adapter *adapter = data;
1126 1126
diff --git a/drivers/net/netxen/netxen_nic_phan_reg.h b/drivers/net/netxen/netxen_nic_phan_reg.h
index db2202aeb0d7..09d070512362 100644
--- a/drivers/net/netxen/netxen_nic_phan_reg.h
+++ b/drivers/net/netxen/netxen_nic_phan_reg.h
@@ -42,8 +42,11 @@
42#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c) 42#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c)
43#define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10) /* C0 EPG BUG */ 43#define CRB_PAUSE_ADDR_LO NETXEN_NIC_REG(0x10) /* C0 EPG BUG */
44#define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14) 44#define CRB_PAUSE_ADDR_HI NETXEN_NIC_REG(0x14)
45#define CRB_HOST_CMD_ADDR_HI NETXEN_NIC_REG(0x18) /* host add:cmd ring */ 45#define NX_CDRP_CRB_OFFSET NETXEN_NIC_REG(0x18)
46#define CRB_HOST_CMD_ADDR_LO NETXEN_NIC_REG(0x1c) 46#define NX_ARG1_CRB_OFFSET NETXEN_NIC_REG(0x1c)
47#define NX_ARG2_CRB_OFFSET NETXEN_NIC_REG(0x20)
48#define NX_ARG3_CRB_OFFSET NETXEN_NIC_REG(0x24)
49#define NX_SIGN_CRB_OFFSET NETXEN_NIC_REG(0x28)
47#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x20) /* 4 regs for perf */ 50#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x20) /* 4 regs for perf */
48#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x24) 51#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x24)
49#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x28) 52#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x28)
@@ -97,6 +100,7 @@
97#define CRB_HOST_BUFFER_CONS NETXEN_NIC_REG(0xf0) 100#define CRB_HOST_BUFFER_CONS NETXEN_NIC_REG(0xf0)
98#define CRB_JUMBO_BUFFER_PROD NETXEN_NIC_REG(0xf4) 101#define CRB_JUMBO_BUFFER_PROD NETXEN_NIC_REG(0xf4)
99#define CRB_JUMBO_BUFFER_CONS NETXEN_NIC_REG(0xf8) 102#define CRB_JUMBO_BUFFER_CONS NETXEN_NIC_REG(0xf8)
103#define CRB_HOST_DUMMY_BUF NETXEN_NIC_REG(0xfc)
100 104
101#define CRB_RCVPEG_STATE NETXEN_NIC_REG(0x13c) 105#define CRB_RCVPEG_STATE NETXEN_NIC_REG(0x13c)
102#define CRB_CMD_PRODUCER_OFFSET_1 NETXEN_NIC_REG(0x1ac) 106#define CRB_CMD_PRODUCER_OFFSET_1 NETXEN_NIC_REG(0x1ac)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 16:08:56 -0500