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-rw-r--r--arch/mips/lantiq/xway/sysctrl.c49
1 files changed, 28 insertions, 21 deletions
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 83780f7c842b..befbb760ab76 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -20,10 +20,12 @@
20 20
21/* clock control register */ 21/* clock control register */
22#define CGU_IFCCR 0x0018 22#define CGU_IFCCR 0x0018
23#define CGU_IFCCR_VR9 0x0024
23/* system clock register */ 24/* system clock register */
24#define CGU_SYS 0x0010 25#define CGU_SYS 0x0010
25/* pci control register */ 26/* pci control register */
26#define CGU_PCICR 0x0034 27#define CGU_PCICR 0x0034
28#define CGU_PCICR_VR9 0x0038
27/* ephy configuration register */ 29/* ephy configuration register */
28#define CGU_EPHY 0x10 30#define CGU_EPHY 0x10
29/* power control register */ 31/* power control register */
@@ -80,6 +82,9 @@ static void __iomem *pmu_membase;
80void __iomem *ltq_cgu_membase; 82void __iomem *ltq_cgu_membase;
81void __iomem *ltq_ebu_membase; 83void __iomem *ltq_ebu_membase;
82 84
85static u32 ifccr = CGU_IFCCR;
86static u32 pcicr = CGU_PCICR;
87
83/* legacy function kept alive to ease clkdev transition */ 88/* legacy function kept alive to ease clkdev transition */
84void ltq_pmu_enable(unsigned int module) 89void ltq_pmu_enable(unsigned int module)
85{ 90{
@@ -103,14 +108,14 @@ EXPORT_SYMBOL(ltq_pmu_disable);
103/* enable a hw clock */ 108/* enable a hw clock */
104static int cgu_enable(struct clk *clk) 109static int cgu_enable(struct clk *clk)
105{ 110{
106 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); 111 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
107 return 0; 112 return 0;
108} 113}
109 114
110/* disable a hw clock */ 115/* disable a hw clock */
111static void cgu_disable(struct clk *clk) 116static void cgu_disable(struct clk *clk)
112{ 117{
113 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); 118 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
114} 119}
115 120
116/* enable a clock gate */ 121/* enable a clock gate */
@@ -138,22 +143,22 @@ static void pmu_disable(struct clk *clk)
138/* the pci enable helper */ 143/* the pci enable helper */
139static int pci_enable(struct clk *clk) 144static int pci_enable(struct clk *clk)
140{ 145{
141 unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); 146 unsigned int val = ltq_cgu_r32(ifccr);
142 /* set bus clock speed */ 147 /* set bus clock speed */
143 if (of_machine_is_compatible("lantiq,ar9")) { 148 if (of_machine_is_compatible("lantiq,ar9")) {
144 ifccr &= ~0x1f00000; 149 val &= ~0x1f00000;
145 if (clk->rate == CLOCK_33M) 150 if (clk->rate == CLOCK_33M)
146 ifccr |= 0xe00000; 151 val |= 0xe00000;
147 else 152 else
148 ifccr |= 0x700000; /* 62.5M */ 153 val |= 0x700000; /* 62.5M */
149 } else { 154 } else {
150 ifccr &= ~0xf00000; 155 val &= ~0xf00000;
151 if (clk->rate == CLOCK_33M) 156 if (clk->rate == CLOCK_33M)
152 ifccr |= 0x800000; 157 val |= 0x800000;
153 else 158 else
154 ifccr |= 0x400000; /* 62.5M */ 159 val |= 0x400000; /* 62.5M */
155 } 160 }
156 ltq_cgu_w32(ifccr, CGU_IFCCR); 161 ltq_cgu_w32(val, ifccr);
157 pmu_enable(clk); 162 pmu_enable(clk);
158 return 0; 163 return 0;
159} 164}
@@ -161,18 +166,16 @@ static int pci_enable(struct clk *clk)
161/* enable the external clock as a source */ 166/* enable the external clock as a source */
162static int pci_ext_enable(struct clk *clk) 167static int pci_ext_enable(struct clk *clk)
163{ 168{
164 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), 169 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
165 CGU_IFCCR); 170 ltq_cgu_w32((1 << 30), pcicr);
166 ltq_cgu_w32((1 << 30), CGU_PCICR);
167 return 0; 171 return 0;
168} 172}
169 173
170/* disable the external clock as a source */ 174/* disable the external clock as a source */
171static void pci_ext_disable(struct clk *clk) 175static void pci_ext_disable(struct clk *clk)
172{ 176{
173 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), 177 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
174 CGU_IFCCR); 178 ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
175 ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
176} 179}
177 180
178/* enable a clockout source */ 181/* enable a clockout source */
@@ -184,11 +187,11 @@ static int clkout_enable(struct clk *clk)
184 for (i = 0; i < 4; i++) { 187 for (i = 0; i < 4; i++) {
185 if (clk->rates[i] == clk->rate) { 188 if (clk->rates[i] == clk->rate) {
186 int shift = 14 - (2 * clk->module); 189 int shift = 14 - (2 * clk->module);
187 unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); 190 unsigned int val = ltq_cgu_r32(ifccr);
188 191
189 ifccr &= ~(3 << shift); 192 val &= ~(3 << shift);
190 ifccr |= i << shift; 193 val |= i << shift;
191 ltq_cgu_w32(ifccr, CGU_IFCCR); 194 ltq_cgu_w32(val, ifccr);
192 return 0; 195 return 0;
193 } 196 }
194 } 197 }
@@ -336,8 +339,12 @@ void __init ltq_soc_init(void)
336 clkdev_add_clkout(); 339 clkdev_add_clkout();
337 340
338 /* add the soc dependent clocks */ 341 /* add the soc dependent clocks */
339 if (!of_machine_is_compatible("lantiq,vr9")) 342 if (of_machine_is_compatible("lantiq,vr9")) {
343 ifccr = CGU_IFCCR_VR9;
344 pcicr = CGU_PCICR_VR9;
345 } else {
340 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE); 346 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
347 }
341 348
342 if (!of_machine_is_compatible("lantiq,ase")) { 349 if (!of_machine_is_compatible("lantiq,ase")) {
343 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1); 350 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-01 03:48:18 -0400