aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-iis.h68
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-spi.h81
-rw-r--r--arch/arm/plat-samsung/include/plat/audio-simtec.h (renamed from arch/arm/plat-s3c24xx/include/plat/audio-simtec.h)2
-rw-r--r--arch/arm/plat-samsung/include/plat/common-smdk.h (renamed from arch/arm/plat-s3c24xx/include/plat/common-smdk.h)2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h (renamed from arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h)5
-rw-r--r--arch/arm/plat-samsung/include/plat/fiq.h (renamed from arch/arm/plat-s3c24xx/include/plat/fiq.h)2
-rw-r--r--arch/arm/plat-samsung/include/plat/irq.h (renamed from arch/arm/plat-s3c24xx/include/plat/irq.h)25
-rw-r--r--arch/arm/plat-samsung/include/plat/mci.h (renamed from arch/arm/plat-s3c24xx/include/plat/mci.h)10
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-dma.h (renamed from arch/arm/plat-s3c24xx/include/plat/regs-dma.h)112
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-iis.h70
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-spi.h48
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-udc.h (renamed from arch/arm/plat-s3c24xx/include/plat/regs-udc.h)132
-rw-r--r--arch/arm/plat-samsung/include/plat/udc.h (renamed from arch/arm/plat-s3c24xx/include/plat/udc.h)4
13 files changed, 268 insertions, 293 deletions
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
deleted file mode 100644
index cc44e0e931e9..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-iis.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_IIS_H
14#define __ASM_ARCH_REGS_IIS_H
15
16#define S3C2410_IISCON (0x00)
17
18#define S3C2410_IISCON_LRINDEX (1<<8)
19#define S3C2410_IISCON_TXFIFORDY (1<<7)
20#define S3C2410_IISCON_RXFIFORDY (1<<6)
21#define S3C2410_IISCON_TXDMAEN (1<<5)
22#define S3C2410_IISCON_RXDMAEN (1<<4)
23#define S3C2410_IISCON_TXIDLE (1<<3)
24#define S3C2410_IISCON_RXIDLE (1<<2)
25#define S3C2410_IISCON_PSCEN (1<<1)
26#define S3C2410_IISCON_IISEN (1<<0)
27
28#define S3C2410_IISMOD (0x04)
29
30#define S3C2440_IISMOD_MPLL (1<<9)
31#define S3C2410_IISMOD_SLAVE (1<<8)
32#define S3C2410_IISMOD_NOXFER (0<<6)
33#define S3C2410_IISMOD_RXMODE (1<<6)
34#define S3C2410_IISMOD_TXMODE (2<<6)
35#define S3C2410_IISMOD_TXRXMODE (3<<6)
36#define S3C2410_IISMOD_LR_LLOW (0<<5)
37#define S3C2410_IISMOD_LR_RLOW (1<<5)
38#define S3C2410_IISMOD_IIS (0<<4)
39#define S3C2410_IISMOD_MSB (1<<4)
40#define S3C2410_IISMOD_8BIT (0<<3)
41#define S3C2410_IISMOD_16BIT (1<<3)
42#define S3C2410_IISMOD_BITMASK (1<<3)
43#define S3C2410_IISMOD_256FS (0<<2)
44#define S3C2410_IISMOD_384FS (1<<2)
45#define S3C2410_IISMOD_16FS (0<<0)
46#define S3C2410_IISMOD_32FS (1<<0)
47#define S3C2410_IISMOD_48FS (2<<0)
48#define S3C2410_IISMOD_FS_MASK (3<<0)
49
50#define S3C2410_IISPSR (0x08)
51#define S3C2410_IISPSR_INTMASK (31<<5)
52#define S3C2410_IISPSR_INTSHIFT (5)
53#define S3C2410_IISPSR_EXTMASK (31<<0)
54#define S3C2410_IISPSR_EXTSHFIT (0)
55
56#define S3C2410_IISFCON (0x0c)
57
58#define S3C2410_IISFCON_TXDMA (1<<15)
59#define S3C2410_IISFCON_RXDMA (1<<14)
60#define S3C2410_IISFCON_TXENABLE (1<<13)
61#define S3C2410_IISFCON_RXENABLE (1<<12)
62#define S3C2410_IISFCON_TXMASK (0x3f << 6)
63#define S3C2410_IISFCON_TXSHIFT (6)
64#define S3C2410_IISFCON_RXMASK (0x3f)
65#define S3C2410_IISFCON_RXSHIFT (0)
66
67#define S3C2410_IISFIFO (0x10)
68#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
deleted file mode 100644
index 892e2f680fca..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2412_SPCON_RXFIFO_RB2 (0<<14)
21#define S3C2412_SPCON_RXFIFO_RB4 (1<<14)
22#define S3C2412_SPCON_RXFIFO_RB12 (2<<14)
23#define S3C2412_SPCON_RXFIFO_RB14 (3<<14)
24#define S3C2412_SPCON_TXFIFO_RB2 (0<<12)
25#define S3C2412_SPCON_TXFIFO_RB4 (1<<12)
26#define S3C2412_SPCON_TXFIFO_RB12 (2<<12)
27#define S3C2412_SPCON_TXFIFO_RB14 (3<<12)
28#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */
29#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */
30#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */
31#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */
32
33#define S3C2412_SPCON_DIRC_RX (1<<7)
34
35#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
36#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
37#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
38#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */
39#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select
40 0: slave, 1: master */
41#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */
42#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */
43
44#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */
45#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */
46
47#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */
48
49
50#define S3C2410_SPSTA (0x04)
51
52#define S3C2412_SPSTA_RXFIFO_AE (1<<11)
53#define S3C2412_SPSTA_TXFIFO_AE (1<<10)
54#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9)
55#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8)
56#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7)
57#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6)
58#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5)
59#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4)
60
61#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
62#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
63#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
64#define S3C2412_SPSTA_READY_ORG (1<<3)
65
66#define S3C2410_SPPIN (0x08)
67
68#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
69#define S3C2410_SPPIN_RESERVED (1<<1)
70#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
71
72#define S3C2410_SPPRE (0x0C)
73#define S3C2410_SPTDAT (0x10)
74#define S3C2410_SPRDAT (0x14)
75
76#define S3C2412_TXFIFO (0x18)
77#define S3C2412_RXFIFO (0x18)
78#define S3C2412_SPFIC (0x24)
79
80
81#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h
index de5e88fdcb31..5345364e7420 100644
--- a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h
+++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h
@@ -1,4 +1,4 @@
1/* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h 1/* arch/arm/plat-samsung/include/plat/audio-simtec.h
2 * 2 *
3 * Copyright 2008 Simtec Electronics 3 * Copyright 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
diff --git a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h b/arch/arm/plat-samsung/include/plat/common-smdk.h
index 58d9094c935c..ba028f1ed30b 100644
--- a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h
+++ b/arch/arm/plat-samsung/include/plat/common-smdk.h
@@ -1,4 +1,4 @@
1/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h 1/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
2 * 2 *
3 * Copyright (c) 2006 Simtec Electronics 3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index d623235ae961..dac4760c0f0a 100644
--- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -1,4 +1,4 @@
1/* arch/arm/plat-s3c/include/plat/cpu-freq.h 1/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
2 * 2 *
3 * Copyright (c) 2006-2009 Simtec Electronics 3 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
@@ -195,7 +195,8 @@ struct s3c_cpufreq_info {
195 195
196extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); 196extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
197 197
198extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no); 198extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
199 unsigned int plls_no);
199 200
200/* exports and utilities for debugfs */ 201/* exports and utilities for debugfs */
201extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); 202extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h
index 8521b8372c5f..535d06a35628 100644
--- a/arch/arm/plat-s3c24xx/include/plat/fiq.h
+++ b/arch/arm/plat-samsung/include/plat/fiq.h
@@ -1,4 +1,4 @@
1/* linux/include/asm-arm/plat-s3c24xx/fiq.h 1/* linux/arch/arm/plat-samsung/include/plat/fiq.h
2 * 2 *
3 * Copyright (c) 2009 Simtec Electronics 3 * Copyright (c) 2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
index ec087d6054b1..e21a89bc26c9 100644
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-samsung/include/plat/irq.h
@@ -1,4 +1,4 @@
1/* linux/include/asm-arm/plat-s3c24xx/irq.h 1/* linux/arch/arm/plat-samsung/include/plat/irq.h
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -25,9 +25,9 @@
25extern struct irq_chip s3c_irq_level_chip; 25extern struct irq_chip s3c_irq_level_chip;
26extern struct irq_chip s3c_irq_chip; 26extern struct irq_chip s3c_irq_chip;
27 27
28static inline void 28static inline void s3c_irqsub_mask(unsigned int irqno,
29s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, 29 unsigned int parentbit,
30 int subcheck) 30 int subcheck)
31{ 31{
32 unsigned long mask; 32 unsigned long mask;
33 unsigned long submask; 33 unsigned long submask;
@@ -39,17 +39,16 @@ s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
39 39
40 /* check to see if we need to mask the parent IRQ */ 40 /* check to see if we need to mask the parent IRQ */
41 41
42 if ((submask & subcheck) == subcheck) { 42 if ((submask & subcheck) == subcheck)
43 __raw_writel(mask | parentbit, S3C2410_INTMSK); 43 __raw_writel(mask | parentbit, S3C2410_INTMSK);
44 }
45 44
46 /* write back masks */ 45 /* write back masks */
47 __raw_writel(submask, S3C2410_INTSUBMSK); 46 __raw_writel(submask, S3C2410_INTSUBMSK);
48 47
49} 48}
50 49
51static inline void 50static inline void s3c_irqsub_unmask(unsigned int irqno,
52s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) 51 unsigned int parentbit)
53{ 52{
54 unsigned long mask; 53 unsigned long mask;
55 unsigned long submask; 54 unsigned long submask;
@@ -66,8 +65,9 @@ s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
66} 65}
67 66
68 67
69static inline void 68static inline void s3c_irqsub_maskack(unsigned int irqno,
70s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group) 69 unsigned int parentmask,
70 unsigned int group)
71{ 71{
72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); 72 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
73 73
@@ -86,8 +86,9 @@ s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int gro
86 } 86 }
87} 87}
88 88
89static inline void 89static inline void s3c_irqsub_ack(unsigned int irqno,
90s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group) 90 unsigned int parentmask,
91 unsigned int group)
91{ 92{
92 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); 93 unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
93 94
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-samsung/include/plat/mci.h
index 2ac2b21ec490..c42d31711944 100644
--- a/arch/arm/plat-s3c24xx/include/plat/mci.h
+++ b/arch/arm/plat-samsung/include/plat/mci.h
@@ -27,11 +27,11 @@
27 * to a non-zero value, otherwise the default of 3.2-3.4V is used. 27 * to a non-zero value, otherwise the default of 3.2-3.4V is used.
28 */ 28 */
29struct s3c24xx_mci_pdata { 29struct s3c24xx_mci_pdata {
30 unsigned int no_wprotect : 1; 30 unsigned int no_wprotect:1;
31 unsigned int no_detect : 1; 31 unsigned int no_detect:1;
32 unsigned int wprotect_invert : 1; 32 unsigned int wprotect_invert:1;
33 unsigned int detect_invert : 1; /* set => detect active high. */ 33 unsigned int detect_invert:1; /* set => detect active high */
34 unsigned int use_dma : 1; 34 unsigned int use_dma:1;
35 35
36 unsigned int gpio_detect; 36 unsigned int gpio_detect;
37 unsigned int gpio_wprotect; 37 unsigned int gpio_wprotect;
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h
index 1b0f4c36d384..178bccbe4804 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
+++ b/arch/arm/plat-samsung/include/plat/regs-dma.h
@@ -1,4 +1,4 @@
1/* arch/arm/mach-s3c2410/include/mach/dma.h 1/* arch/arm/plat-samsung/include/plat/regs-dma.h
2 * 2 *
3 * Copyright (C) 2003-2006 Simtec Electronics 3 * Copyright (C) 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
@@ -10,7 +10,8 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13/* DMA Register definitions */ 13#ifndef __ASM_PLAT_REGS_DMA_H
14#define __ASM_PLAT_REGS_DMA_H __FILE__
14 15
15#define S3C2410_DMA_DISRC (0x00) 16#define S3C2410_DMA_DISRC (0x00)
16#define S3C2410_DMA_DISRCC (0x04) 17#define S3C2410_DMA_DISRCC (0x04)
@@ -24,74 +25,75 @@
24#define S3C2412_DMA_DMAREQSEL (0x24) 25#define S3C2412_DMA_DMAREQSEL (0x24)
25#define S3C2443_DMA_DMAREQSEL (0x24) 26#define S3C2443_DMA_DMAREQSEL (0x24)
26 27
27#define S3C2410_DISRCC_INC (1<<0) 28#define S3C2410_DISRCC_INC (1 << 0)
28#define S3C2410_DISRCC_APB (1<<1) 29#define S3C2410_DISRCC_APB (1 << 1)
29 30
30#define S3C2410_DMASKTRIG_STOP (1<<2) 31#define S3C2410_DMASKTRIG_STOP (1 << 2)
31#define S3C2410_DMASKTRIG_ON (1<<1) 32#define S3C2410_DMASKTRIG_ON (1 << 1)
32#define S3C2410_DMASKTRIG_SWTRIG (1<<0) 33#define S3C2410_DMASKTRIG_SWTRIG (1 << 0)
33 34
34#define S3C2410_DCON_DEMAND (0<<31) 35#define S3C2410_DCON_DEMAND (0 << 31)
35#define S3C2410_DCON_HANDSHAKE (1<<31) 36#define S3C2410_DCON_HANDSHAKE (1 << 31)
36#define S3C2410_DCON_SYNC_PCLK (0<<30) 37#define S3C2410_DCON_SYNC_PCLK (0 << 30)
37#define S3C2410_DCON_SYNC_HCLK (1<<30) 38#define S3C2410_DCON_SYNC_HCLK (1 << 30)
38 39
39#define S3C2410_DCON_INTREQ (1<<29) 40#define S3C2410_DCON_INTREQ (1 << 29)
40 41
41#define S3C2410_DCON_CH0_XDREQ0 (0<<24) 42#define S3C2410_DCON_CH0_XDREQ0 (0 << 24)
42#define S3C2410_DCON_CH0_UART0 (1<<24) 43#define S3C2410_DCON_CH0_UART0 (1 << 24)
43#define S3C2410_DCON_CH0_SDI (2<<24) 44#define S3C2410_DCON_CH0_SDI (2 << 24)
44#define S3C2410_DCON_CH0_TIMER (3<<24) 45#define S3C2410_DCON_CH0_TIMER (3 << 24)
45#define S3C2410_DCON_CH0_USBEP1 (4<<24) 46#define S3C2410_DCON_CH0_USBEP1 (4 << 24)
46 47
47#define S3C2410_DCON_CH1_XDREQ1 (0<<24) 48#define S3C2410_DCON_CH1_XDREQ1 (0 << 24)
48#define S3C2410_DCON_CH1_UART1 (1<<24) 49#define S3C2410_DCON_CH1_UART1 (1 << 24)
49#define S3C2410_DCON_CH1_I2SSDI (2<<24) 50#define S3C2410_DCON_CH1_I2SSDI (2 << 24)
50#define S3C2410_DCON_CH1_SPI (3<<24) 51#define S3C2410_DCON_CH1_SPI (3 << 24)
51#define S3C2410_DCON_CH1_USBEP2 (4<<24) 52#define S3C2410_DCON_CH1_USBEP2 (4 << 24)
52 53
53#define S3C2410_DCON_CH2_I2SSDO (0<<24) 54#define S3C2410_DCON_CH2_I2SSDO (0 << 24)
54#define S3C2410_DCON_CH2_I2SSDI (1<<24) 55#define S3C2410_DCON_CH2_I2SSDI (1 << 24)
55#define S3C2410_DCON_CH2_SDI (2<<24) 56#define S3C2410_DCON_CH2_SDI (2 << 24)
56#define S3C2410_DCON_CH2_TIMER (3<<24) 57#define S3C2410_DCON_CH2_TIMER (3 << 24)
57#define S3C2410_DCON_CH2_USBEP3 (4<<24) 58#define S3C2410_DCON_CH2_USBEP3 (4 << 24)
58 59
59#define S3C2410_DCON_CH3_UART2 (0<<24) 60#define S3C2410_DCON_CH3_UART2 (0 << 24)
60#define S3C2410_DCON_CH3_SDI (1<<24) 61#define S3C2410_DCON_CH3_SDI (1 << 24)
61#define S3C2410_DCON_CH3_SPI (2<<24) 62#define S3C2410_DCON_CH3_SPI (2 << 24)
62#define S3C2410_DCON_CH3_TIMER (3<<24) 63#define S3C2410_DCON_CH3_TIMER (3 << 24)
63#define S3C2410_DCON_CH3_USBEP4 (4<<24) 64#define S3C2410_DCON_CH3_USBEP4 (4 << 24)
64 65
65#define S3C2410_DCON_SRCSHIFT (24) 66#define S3C2410_DCON_SRCSHIFT (24)
66#define S3C2410_DCON_SRCMASK (7<<24) 67#define S3C2410_DCON_SRCMASK (7 << 24)
67 68
68#define S3C2410_DCON_BYTE (0<<20) 69#define S3C2410_DCON_BYTE (0 << 20)
69#define S3C2410_DCON_HALFWORD (1<<20) 70#define S3C2410_DCON_HALFWORD (1 << 20)
70#define S3C2410_DCON_WORD (2<<20) 71#define S3C2410_DCON_WORD (2 << 20)
71 72
72#define S3C2410_DCON_AUTORELOAD (0<<22) 73#define S3C2410_DCON_AUTORELOAD (0 << 22)
73#define S3C2410_DCON_NORELOAD (1<<22) 74#define S3C2410_DCON_NORELOAD (1 << 22)
74#define S3C2410_DCON_HWTRIG (1<<23) 75#define S3C2410_DCON_HWTRIG (1 << 23)
75 76
76#ifdef CONFIG_CPU_S3C2440 77#ifdef CONFIG_CPU_S3C2440
77#define S3C2440_DIDSTC_CHKINT (1<<2)
78 78
79#define S3C2440_DCON_CH0_I2SSDO (5<<24) 79#define S3C2440_DIDSTC_CHKINT (1 << 2)
80#define S3C2440_DCON_CH0_PCMIN (6<<24)
81 80
82#define S3C2440_DCON_CH1_PCMOUT (5<<24) 81#define S3C2440_DCON_CH0_I2SSDO (5 << 24)
83#define S3C2440_DCON_CH1_SDI (6<<24) 82#define S3C2440_DCON_CH0_PCMIN (6 << 24)
84 83
85#define S3C2440_DCON_CH2_PCMIN (5<<24) 84#define S3C2440_DCON_CH1_PCMOUT (5 << 24)
86#define S3C2440_DCON_CH2_MICIN (6<<24) 85#define S3C2440_DCON_CH1_SDI (6 << 24)
87 86
88#define S3C2440_DCON_CH3_MICIN (5<<24) 87#define S3C2440_DCON_CH2_PCMIN (5 << 24)
89#define S3C2440_DCON_CH3_PCMOUT (6<<24) 88#define S3C2440_DCON_CH2_MICIN (6 << 24)
90#endif 89
90#define S3C2440_DCON_CH3_MICIN (5 << 24)
91#define S3C2440_DCON_CH3_PCMOUT (6 << 24)
92#endif /* CONFIG_CPU_S3C2440 */
91 93
92#ifdef CONFIG_CPU_S3C2412 94#ifdef CONFIG_CPU_S3C2412
93 95
94#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) 96#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1)
95 97
96#define S3C2412_DMAREQSEL_HW (1) 98#define S3C2412_DMAREQSEL_HW (1)
97 99
@@ -115,10 +117,11 @@
115#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) 117#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
116#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) 118#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
117#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) 119#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
120#endif /* CONFIG_CPU_S3C2412 */
118 121
119#endif 122#ifdef CONFIG_CPU_S3C2443
120 123
121#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) 124#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1)
122 125
123#define S3C2443_DMAREQSEL_HW (1) 126#define S3C2443_DMAREQSEL_HW (1)
124 127
@@ -141,5 +144,8 @@
141#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) 144#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25)
142#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) 145#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26)
143#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) 146#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27)
144#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) 147#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28)
145#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) 148#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29)
149#endif /* CONFIG_CPU_S3C2443 */
150
151#endif /* __ASM_PLAT_REGS_DMA_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h
new file mode 100644
index 000000000000..a18d35e7a735
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-iis.h
@@ -0,0 +1,70 @@
1/* arch/arm/plat-samsung/include/plat/regs-iis.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 IIS register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_IIS_H
14#define __ASM_ARCH_REGS_IIS_H
15
16#define S3C2410_IISCON (0x00)
17
18#define S3C2410_IISCON_LRINDEX (1 << 8)
19#define S3C2410_IISCON_TXFIFORDY (1 << 7)
20#define S3C2410_IISCON_RXFIFORDY (1 << 6)
21#define S3C2410_IISCON_TXDMAEN (1 << 5)
22#define S3C2410_IISCON_RXDMAEN (1 << 4)
23#define S3C2410_IISCON_TXIDLE (1 << 3)
24#define S3C2410_IISCON_RXIDLE (1 << 2)
25#define S3C2410_IISCON_PSCEN (1 << 1)
26#define S3C2410_IISCON_IISEN (1 << 0)
27
28#define S3C2410_IISMOD (0x04)
29
30#define S3C2440_IISMOD_MPLL (1 << 9)
31#define S3C2410_IISMOD_SLAVE (1 << 8)
32#define S3C2410_IISMOD_NOXFER (0 << 6)
33#define S3C2410_IISMOD_RXMODE (1 << 6)
34#define S3C2410_IISMOD_TXMODE (2 << 6)
35#define S3C2410_IISMOD_TXRXMODE (3 << 6)
36#define S3C2410_IISMOD_LR_LLOW (0 << 5)
37#define S3C2410_IISMOD_LR_RLOW (1 << 5)
38#define S3C2410_IISMOD_IIS (0 << 4)
39#define S3C2410_IISMOD_MSB (1 << 4)
40#define S3C2410_IISMOD_8BIT (0 << 3)
41#define S3C2410_IISMOD_16BIT (1 << 3)
42#define S3C2410_IISMOD_BITMASK (1 << 3)
43#define S3C2410_IISMOD_256FS (0 << 2)
44#define S3C2410_IISMOD_384FS (1 << 2)
45#define S3C2410_IISMOD_16FS (0 << 0)
46#define S3C2410_IISMOD_32FS (1 << 0)
47#define S3C2410_IISMOD_48FS (2 << 0)
48#define S3C2410_IISMOD_FS_MASK (3 << 0)
49
50#define S3C2410_IISPSR (0x08)
51
52#define S3C2410_IISPSR_INTMASK (31 << 5)
53#define S3C2410_IISPSR_INTSHIFT (5)
54#define S3C2410_IISPSR_EXTMASK (31 << 0)
55#define S3C2410_IISPSR_EXTSHFIT (0)
56
57#define S3C2410_IISFCON (0x0c)
58
59#define S3C2410_IISFCON_TXDMA (1 << 15)
60#define S3C2410_IISFCON_RXDMA (1 << 14)
61#define S3C2410_IISFCON_TXENABLE (1 << 13)
62#define S3C2410_IISFCON_RXENABLE (1 << 12)
63#define S3C2410_IISFCON_TXMASK (0x3f << 6)
64#define S3C2410_IISFCON_TXSHIFT (6)
65#define S3C2410_IISFCON_RXMASK (0x3f)
66#define S3C2410_IISFCON_RXSHIFT (0)
67
68#define S3C2410_IISFIFO (0x10)
69
70#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h
new file mode 100644
index 000000000000..552fe7cfe281
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-spi.h
@@ -0,0 +1,48 @@
1/* arch/arm/plat-samsung/include/plat/regs-spi.h
2 *
3 * Copyright (c) 2004 Fetron GmbH
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * S3C2410 SPI register definition
10*/
11
12#ifndef __ASM_ARCH_REGS_SPI_H
13#define __ASM_ARCH_REGS_SPI_H
14
15#define S3C2410_SPI1 (0x20)
16#define S3C2412_SPI1 (0x100)
17
18#define S3C2410_SPCON (0x00)
19
20#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
21#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
22#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
23#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
24#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
25#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
26#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
27
28#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
29#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
30
31#define S3C2410_SPSTA (0x04)
32
33#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
34#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
35#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
36#define S3C2412_SPSTA_READY_ORG (1 << 3)
37
38#define S3C2410_SPPIN (0x08)
39
40#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
41#define S3C2410_SPPIN_RESERVED (1 << 1)
42#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
43
44#define S3C2410_SPPRE (0x0C)
45#define S3C2410_SPTDAT (0x10)
46#define S3C2410_SPRDAT (0x14)
47
48#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h
index f0dd4a41b37b..4003d3dab4e7 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-udc.h
@@ -1,4 +1,4 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-udc.h 1/* arch/arm/plat-samsung/include/plat/regs-udc.h
2 * 2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> 3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 * 4 *
@@ -75,79 +75,77 @@
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) 75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) 76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77 77
78#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7) 78#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7)
79 79
80#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W 80#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */
81#define S3C2410_UDC_PWR_RESET (1<<3) // R 81#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */
82#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W 82#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */
83#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R 83#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */
84#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W 84#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */
85 85
86#define S3C2410_UDC_PWR_DEFAULT 0x00 86#define S3C2410_UDC_PWR_DEFAULT (0x00)
87 87
88#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only) 88#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
89#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only) 89#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
90#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only) 90#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
91#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only) 91#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
92#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only) 92#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
93 93
94#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only) 94#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
95#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only) 95#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
96#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only) 96#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
97 97
98#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W 98#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */
99#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W 99#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */
100#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W 100#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */
101#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W 101#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */
102#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W 102#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */
103
104#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W
105#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W
106 103
104#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */
105#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */
107 106
108#define S3C2410_UDC_INDEX_EP0 (0x00) 107#define S3C2410_UDC_INDEX_EP0 (0x00)
109#define S3C2410_UDC_INDEX_EP1 (0x01) // ?? 108#define S3C2410_UDC_INDEX_EP1 (0x01)
110#define S3C2410_UDC_INDEX_EP2 (0x02) // ?? 109#define S3C2410_UDC_INDEX_EP2 (0x02)
111#define S3C2410_UDC_INDEX_EP3 (0x03) // ?? 110#define S3C2410_UDC_INDEX_EP3 (0x03)
112#define S3C2410_UDC_INDEX_EP4 (0x04) // ?? 111#define S3C2410_UDC_INDEX_EP4 (0x04)
113 112
114#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W 113#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */
115#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only) 114#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
116#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W 115#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */
117#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only) 116#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
118#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only) 117#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
119#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only) 118#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
120 119
121#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W 120#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */
122#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W 121#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */
123#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W 122#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */
124#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W 123#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */
125 124
126#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W 125#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */
127#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only) 126#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
128#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W 127#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */
129#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W 128#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */
130#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R 129#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */
131#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only) 130#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
132#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only) 131#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
133 132
134#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W 133#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */
135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W 134#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */
136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W 135#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */
137 136
138#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) 137#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0)
139#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) 138#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1)
140#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) 139#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2)
141#define S3C2410_UDC_EP0_CSR_DE (1<<3) 140#define S3C2410_UDC_EP0_CSR_DE (1 << 3)
142#define S3C2410_UDC_EP0_CSR_SE (1<<4) 141#define S3C2410_UDC_EP0_CSR_SE (1 << 4)
143#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5) 142#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5)
144#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6) 143#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6)
145#define S3C2410_UDC_EP0_CSR_SSE (1<<7) 144#define S3C2410_UDC_EP0_CSR_SSE (1 << 7)
146 145
147#define S3C2410_UDC_MAXP_8 (1<<0) 146#define S3C2410_UDC_MAXP_8 (1 << 0)
148#define S3C2410_UDC_MAXP_16 (1<<1) 147#define S3C2410_UDC_MAXP_16 (1 << 1)
149#define S3C2410_UDC_MAXP_32 (1<<2) 148#define S3C2410_UDC_MAXP_32 (1 << 2)
150#define S3C2410_UDC_MAXP_64 (1<<3) 149#define S3C2410_UDC_MAXP_64 (1 << 3)
151
152 150
153#endif 151#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h
index f63884242506..8c22d586befb 100644
--- a/arch/arm/plat-s3c24xx/include/plat/udc.h
+++ b/arch/arm/plat-samsung/include/plat/udc.h
@@ -1,4 +1,4 @@
1/* arch/arm/mach-s3c2410/include/mach/udc.h 1/* arch/arm/plat-samsung/include/plat/udc.h
2 * 2 *
3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> 3 * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org>
4 * 4 *
@@ -26,7 +26,7 @@ enum s3c2410_udc_cmd_e {
26 26
27struct s3c2410_udc_mach_info { 27struct s3c2410_udc_mach_info {
28 void (*udc_command)(enum s3c2410_udc_cmd_e); 28 void (*udc_command)(enum s3c2410_udc_cmd_e);
29 void (*vbus_draw)(unsigned int ma); 29 void (*vbus_draw)(unsigned int ma);
30 30
31 unsigned int pullup_pin; 31 unsigned int pullup_pin;
32 unsigned int pullup_pin_inverted; 32 unsigned int pullup_pin_inverted;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 14:40:58 -0500