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-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h2480
1 files changed, 1 insertions, 2479 deletions
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index e1fa870ce782..bd5f80e58a23 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -73,7 +73,7 @@
73 * } sn; 73 * } sn;
74 * }; 74 * };
75 * 75 *
76 * (GEN Flags: mflags_opt=c undefs=0 UV23=UVXH) 76 * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH)
77 */ 77 */
78 78
79#define UV_MMR_ENABLE (1UL << 63) 79#define UV_MMR_ENABLE (1UL << 63)
@@ -92,64 +92,24 @@
92/* UVH_BAU_DATA_BROADCAST */ 92/* UVH_BAU_DATA_BROADCAST */
93/* ========================================================================= */ 93/* ========================================================================= */
94#define UVH_BAU_DATA_BROADCAST 0x61688UL 94#define UVH_BAU_DATA_BROADCAST 0x61688UL
95#define UV1H_BAU_DATA_BROADCAST 0x61688UL
96#define UV2H_BAU_DATA_BROADCAST 0x61688UL
97#define UV3H_BAU_DATA_BROADCAST 0x61688UL
98#define UVH_BAU_DATA_BROADCAST_32 0x440 95#define UVH_BAU_DATA_BROADCAST_32 0x440
99#define UV1H_BAU_DATA_BROADCAST_32 0x61688UL
100#define UV2H_BAU_DATA_BROADCAST_32 0x61688UL
101#define UV3H_BAU_DATA_BROADCAST_32 0x61688UL
102 96
103#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 97#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
104#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 98#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
105 99
106#define UV1H_BAU_DATA_BROADCAST_ENABLE_SHFT 0
107#define UV1H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
108
109#define UVXH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
110#define UVXH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
111
112#define UV2H_BAU_DATA_BROADCAST_ENABLE_SHFT 0
113#define UV2H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
114
115#define UV3H_BAU_DATA_BROADCAST_ENABLE_SHFT 0
116#define UV3H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
117
118union uvh_bau_data_broadcast_u { 100union uvh_bau_data_broadcast_u {
119 unsigned long v; 101 unsigned long v;
120 struct uvh_bau_data_broadcast_s { 102 struct uvh_bau_data_broadcast_s {
121 unsigned long enable:1; /* RW */ 103 unsigned long enable:1; /* RW */
122 unsigned long rsvd_1_63:63; 104 unsigned long rsvd_1_63:63;
123 } s; 105 } s;
124 struct uv1h_bau_data_broadcast_s {
125 unsigned long enable:1; /* RW */
126 unsigned long rsvd_1_63:63;
127 } s1;
128 struct uvxh_bau_data_broadcast_s {
129 unsigned long enable:1; /* RW */
130 unsigned long rsvd_1_63:63;
131 } sx;
132 struct uv2h_bau_data_broadcast_s {
133 unsigned long enable:1; /* RW */
134 unsigned long rsvd_1_63:63;
135 } s2;
136 struct uv3h_bau_data_broadcast_s {
137 unsigned long enable:1; /* RW */
138 unsigned long rsvd_1_63:63;
139 } s3;
140}; 106};
141 107
142/* ========================================================================= */ 108/* ========================================================================= */
143/* UVH_BAU_DATA_CONFIG */ 109/* UVH_BAU_DATA_CONFIG */
144/* ========================================================================= */ 110/* ========================================================================= */
145#define UVH_BAU_DATA_CONFIG 0x61680UL 111#define UVH_BAU_DATA_CONFIG 0x61680UL
146#define UV1H_BAU_DATA_CONFIG 0x61680UL
147#define UV2H_BAU_DATA_CONFIG 0x61680UL
148#define UV3H_BAU_DATA_CONFIG 0x61680UL
149#define UVH_BAU_DATA_CONFIG_32 0x438 112#define UVH_BAU_DATA_CONFIG_32 0x438
150#define UV1H_BAU_DATA_CONFIG_32 0x61680UL
151#define UV2H_BAU_DATA_CONFIG_32 0x61680UL
152#define UV3H_BAU_DATA_CONFIG_32 0x61680UL
153 113
154#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 114#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
155#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 115#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
@@ -168,74 +128,6 @@ union uvh_bau_data_broadcast_u {
168#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 128#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
169#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 129#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
170 130
171#define UV1H_BAU_DATA_CONFIG_VECTOR_SHFT 0
172#define UV1H_BAU_DATA_CONFIG_DM_SHFT 8
173#define UV1H_BAU_DATA_CONFIG_DESTMODE_SHFT 11
174#define UV1H_BAU_DATA_CONFIG_STATUS_SHFT 12
175#define UV1H_BAU_DATA_CONFIG_P_SHFT 13
176#define UV1H_BAU_DATA_CONFIG_T_SHFT 15
177#define UV1H_BAU_DATA_CONFIG_M_SHFT 16
178#define UV1H_BAU_DATA_CONFIG_APIC_ID_SHFT 32
179#define UV1H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
180#define UV1H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
181#define UV1H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
182#define UV1H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
183#define UV1H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
184#define UV1H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
185#define UV1H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
186#define UV1H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
187
188#define UVXH_BAU_DATA_CONFIG_VECTOR_SHFT 0
189#define UVXH_BAU_DATA_CONFIG_DM_SHFT 8
190#define UVXH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
191#define UVXH_BAU_DATA_CONFIG_STATUS_SHFT 12
192#define UVXH_BAU_DATA_CONFIG_P_SHFT 13
193#define UVXH_BAU_DATA_CONFIG_T_SHFT 15
194#define UVXH_BAU_DATA_CONFIG_M_SHFT 16
195#define UVXH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
196#define UVXH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
197#define UVXH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
198#define UVXH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
199#define UVXH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
200#define UVXH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
201#define UVXH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
202#define UVXH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
203#define UVXH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
204
205#define UV2H_BAU_DATA_CONFIG_VECTOR_SHFT 0
206#define UV2H_BAU_DATA_CONFIG_DM_SHFT 8
207#define UV2H_BAU_DATA_CONFIG_DESTMODE_SHFT 11
208#define UV2H_BAU_DATA_CONFIG_STATUS_SHFT 12
209#define UV2H_BAU_DATA_CONFIG_P_SHFT 13
210#define UV2H_BAU_DATA_CONFIG_T_SHFT 15
211#define UV2H_BAU_DATA_CONFIG_M_SHFT 16
212#define UV2H_BAU_DATA_CONFIG_APIC_ID_SHFT 32
213#define UV2H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
214#define UV2H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
215#define UV2H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
216#define UV2H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
217#define UV2H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
218#define UV2H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
219#define UV2H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
220#define UV2H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
221
222#define UV3H_BAU_DATA_CONFIG_VECTOR_SHFT 0
223#define UV3H_BAU_DATA_CONFIG_DM_SHFT 8
224#define UV3H_BAU_DATA_CONFIG_DESTMODE_SHFT 11
225#define UV3H_BAU_DATA_CONFIG_STATUS_SHFT 12
226#define UV3H_BAU_DATA_CONFIG_P_SHFT 13
227#define UV3H_BAU_DATA_CONFIG_T_SHFT 15
228#define UV3H_BAU_DATA_CONFIG_M_SHFT 16
229#define UV3H_BAU_DATA_CONFIG_APIC_ID_SHFT 32
230#define UV3H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
231#define UV3H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
232#define UV3H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
233#define UV3H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
234#define UV3H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
235#define UV3H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
236#define UV3H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
237#define UV3H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
238
239union uvh_bau_data_config_u { 131union uvh_bau_data_config_u {
240 unsigned long v; 132 unsigned long v;
241 struct uvh_bau_data_config_s { 133 struct uvh_bau_data_config_s {
@@ -250,74 +142,19 @@ union uvh_bau_data_config_u {
250 unsigned long rsvd_17_31:15; 142 unsigned long rsvd_17_31:15;
251 unsigned long apic_id:32; /* RW */ 143 unsigned long apic_id:32; /* RW */
252 } s; 144 } s;
253 struct uv1h_bau_data_config_s {
254 unsigned long vector_:8; /* RW */
255 unsigned long dm:3; /* RW */
256 unsigned long destmode:1; /* RW */
257 unsigned long status:1; /* RO */
258 unsigned long p:1; /* RO */
259 unsigned long rsvd_14:1;
260 unsigned long t:1; /* RO */
261 unsigned long m:1; /* RW */
262 unsigned long rsvd_17_31:15;
263 unsigned long apic_id:32; /* RW */
264 } s1;
265 struct uvxh_bau_data_config_s {
266 unsigned long vector_:8; /* RW */
267 unsigned long dm:3; /* RW */
268 unsigned long destmode:1; /* RW */
269 unsigned long status:1; /* RO */
270 unsigned long p:1; /* RO */
271 unsigned long rsvd_14:1;
272 unsigned long t:1; /* RO */
273 unsigned long m:1; /* RW */
274 unsigned long rsvd_17_31:15;
275 unsigned long apic_id:32; /* RW */
276 } sx;
277 struct uv2h_bau_data_config_s {
278 unsigned long vector_:8; /* RW */
279 unsigned long dm:3; /* RW */
280 unsigned long destmode:1; /* RW */
281 unsigned long status:1; /* RO */
282 unsigned long p:1; /* RO */
283 unsigned long rsvd_14:1;
284 unsigned long t:1; /* RO */
285 unsigned long m:1; /* RW */
286 unsigned long rsvd_17_31:15;
287 unsigned long apic_id:32; /* RW */
288 } s2;
289 struct uv3h_bau_data_config_s {
290 unsigned long vector_:8; /* RW */
291 unsigned long dm:3; /* RW */
292 unsigned long destmode:1; /* RW */
293 unsigned long status:1; /* RO */
294 unsigned long p:1; /* RO */
295 unsigned long rsvd_14:1;
296 unsigned long t:1; /* RO */
297 unsigned long m:1; /* RW */
298 unsigned long rsvd_17_31:15;
299 unsigned long apic_id:32; /* RW */
300 } s3;
301}; 145};
302 146
303/* ========================================================================= */ 147/* ========================================================================= */
304/* UVH_EVENT_OCCURRED0 */ 148/* UVH_EVENT_OCCURRED0 */
305/* ========================================================================= */ 149/* ========================================================================= */
306#define UVH_EVENT_OCCURRED0 0x70000UL 150#define UVH_EVENT_OCCURRED0 0x70000UL
307#define UV1H_EVENT_OCCURRED0 0x70000UL
308#define UV2H_EVENT_OCCURRED0 0x70000UL
309#define UV3H_EVENT_OCCURRED0 0x70000UL
310#define UVH_EVENT_OCCURRED0_32 0x5e8 151#define UVH_EVENT_OCCURRED0_32 0x5e8
311#define UV1H_EVENT_OCCURRED0_32 0x70000UL
312#define UV2H_EVENT_OCCURRED0_32 0x70000UL
313#define UV3H_EVENT_OCCURRED0_32 0x70000UL
314 152
315#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 153#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
316#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 154#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
317#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL 155#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
318#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL 156#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
319 157
320#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
321#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1 158#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
322#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2 159#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
323#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3 160#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
@@ -328,7 +165,6 @@ union uvh_bau_data_config_u {
328#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8 165#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
329#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9 166#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
330#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10 167#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
331#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
332#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12 168#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
333#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13 169#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
334#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14 170#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
@@ -374,7 +210,6 @@ union uvh_bau_data_config_u {
374#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54 210#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
375#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55 211#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
376#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56 212#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
377#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
378#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL 213#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
379#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL 214#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
380#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL 215#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
@@ -385,7 +220,6 @@ union uvh_bau_data_config_u {
385#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL 220#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
386#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL 221#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
387#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL 222#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
388#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
389#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL 223#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
390#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL 224#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
391#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL 225#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
@@ -432,7 +266,6 @@ union uvh_bau_data_config_u {
432#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 266#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
433#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 267#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
434 268
435#define UVXH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
436#define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1 269#define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1
437#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 270#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2
438#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 271#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
@@ -443,7 +276,6 @@ union uvh_bau_data_config_u {
443#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 276#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
444#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 277#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
445#define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 278#define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
446#define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
447#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 279#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
448#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 280#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
449#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 281#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
@@ -491,7 +323,6 @@ union uvh_bau_data_config_u {
491#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 323#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
492#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 324#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
493#define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 325#define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
494#define UVXH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
495#define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL 326#define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
496#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 327#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
497#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 328#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
@@ -502,7 +333,6 @@ union uvh_bau_data_config_u {
502#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 333#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
503#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 334#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
504#define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL 335#define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
505#define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
506#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 336#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
507#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 337#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
508#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 338#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
@@ -551,244 +381,6 @@ union uvh_bau_data_config_u {
551#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 381#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
552#define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 382#define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
553 383
554#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
555#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
556#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
557#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
558#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
559#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
560#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
561#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
562#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
563#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
564#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
565#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
566#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
567#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
568#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
569#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
570#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
571#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
572#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
573#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
574#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
575#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
576#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
577#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
578#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
579#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
580#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
581#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
582#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
583#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
584#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
585#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
586#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
587#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
588#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
589#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
590#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
591#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
592#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
593#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
594#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
595#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
596#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
597#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
598#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
599#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
600#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
601#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
602#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
603#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
604#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
605#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
606#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
607#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
608#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
609#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
610#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
611#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
612#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
613#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
614#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
615#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
616#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
617#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
618#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
619#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
620#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
621#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
622#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
623#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
624#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
625#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
626#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
627#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
628#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
629#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
630#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
631#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
632#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
633#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
634#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
635#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
636#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
637#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
638#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
639#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
640#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
641#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
642#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
643#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
644#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
645#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
646#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
647#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
648#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
649#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
650#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
651#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
652#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
653#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
654#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
655#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
656#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
657#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
658#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
659#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
660#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
661#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
662#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
663#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
664#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
665#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
666#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
667#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
668#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
669#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
670#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
671#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
672
673#define UV3H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
674#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
675#define UV3H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
676#define UV3H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
677#define UV3H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
678#define UV3H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
679#define UV3H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
680#define UV3H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
681#define UV3H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
682#define UV3H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
683#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
684#define UV3H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
685#define UV3H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
686#define UV3H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
687#define UV3H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
688#define UV3H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
689#define UV3H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
690#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
691#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
692#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
693#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
694#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
695#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
696#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
697#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
698#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
699#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
700#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
701#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
702#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
703#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
704#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
705#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
706#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
707#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
708#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
709#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
710#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
711#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
712#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
713#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
714#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
715#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
716#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
717#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
718#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
719#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
720#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
721#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
722#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
723#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
724#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
725#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
726#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53
727#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
728#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
729#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
730#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
731#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
732#define UV3H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
733#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
734#define UV3H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
735#define UV3H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
736#define UV3H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
737#define UV3H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
738#define UV3H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
739#define UV3H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
740#define UV3H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
741#define UV3H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
742#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
743#define UV3H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
744#define UV3H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
745#define UV3H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
746#define UV3H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
747#define UV3H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
748#define UV3H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
749#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
750#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
751#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
752#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
753#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
754#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
755#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
756#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
757#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
758#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
759#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
760#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
761#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
762#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
763#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
764#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
765#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
766#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
767#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
768#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
769#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
770#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
771#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
772#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
773#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
774#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
775#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
776#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
777#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
778#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
779#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
780#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
781#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
782#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
783#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
784#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
785#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
786#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
787#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
788#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
789#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
790#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
791
792union uvh_event_occurred0_u { 384union uvh_event_occurred0_u {
793 unsigned long v; 385 unsigned long v;
794 struct uvh_event_occurred0_s { 386 struct uvh_event_occurred0_s {
@@ -797,66 +389,6 @@ union uvh_event_occurred0_u {
797 unsigned long rh_aoerr0:1; /* RW, W1C */ 389 unsigned long rh_aoerr0:1; /* RW, W1C */
798 unsigned long rsvd_12_63:52; 390 unsigned long rsvd_12_63:52;
799 } s; 391 } s;
800 struct uv1h_event_occurred0_s {
801 unsigned long lb_hcerr:1; /* RW, W1C */
802 unsigned long gr0_hcerr:1; /* RW, W1C */
803 unsigned long gr1_hcerr:1; /* RW, W1C */
804 unsigned long lh_hcerr:1; /* RW, W1C */
805 unsigned long rh_hcerr:1; /* RW, W1C */
806 unsigned long xn_hcerr:1; /* RW, W1C */
807 unsigned long si_hcerr:1; /* RW, W1C */
808 unsigned long lb_aoerr0:1; /* RW, W1C */
809 unsigned long gr0_aoerr0:1; /* RW, W1C */
810 unsigned long gr1_aoerr0:1; /* RW, W1C */
811 unsigned long lh_aoerr0:1; /* RW, W1C */
812 unsigned long rh_aoerr0:1; /* RW, W1C */
813 unsigned long xn_aoerr0:1; /* RW, W1C */
814 unsigned long si_aoerr0:1; /* RW, W1C */
815 unsigned long lb_aoerr1:1; /* RW, W1C */
816 unsigned long gr0_aoerr1:1; /* RW, W1C */
817 unsigned long gr1_aoerr1:1; /* RW, W1C */
818 unsigned long lh_aoerr1:1; /* RW, W1C */
819 unsigned long rh_aoerr1:1; /* RW, W1C */
820 unsigned long xn_aoerr1:1; /* RW, W1C */
821 unsigned long si_aoerr1:1; /* RW, W1C */
822 unsigned long rh_vpi_int:1; /* RW, W1C */
823 unsigned long system_shutdown_int:1; /* RW, W1C */
824 unsigned long lb_irq_int_0:1; /* RW, W1C */
825 unsigned long lb_irq_int_1:1; /* RW, W1C */
826 unsigned long lb_irq_int_2:1; /* RW, W1C */
827 unsigned long lb_irq_int_3:1; /* RW, W1C */
828 unsigned long lb_irq_int_4:1; /* RW, W1C */
829 unsigned long lb_irq_int_5:1; /* RW, W1C */
830 unsigned long lb_irq_int_6:1; /* RW, W1C */
831 unsigned long lb_irq_int_7:1; /* RW, W1C */
832 unsigned long lb_irq_int_8:1; /* RW, W1C */
833 unsigned long lb_irq_int_9:1; /* RW, W1C */
834 unsigned long lb_irq_int_10:1; /* RW, W1C */
835 unsigned long lb_irq_int_11:1; /* RW, W1C */
836 unsigned long lb_irq_int_12:1; /* RW, W1C */
837 unsigned long lb_irq_int_13:1; /* RW, W1C */
838 unsigned long lb_irq_int_14:1; /* RW, W1C */
839 unsigned long lb_irq_int_15:1; /* RW, W1C */
840 unsigned long l1_nmi_int:1; /* RW, W1C */
841 unsigned long stop_clock:1; /* RW, W1C */
842 unsigned long asic_to_l1:1; /* RW, W1C */
843 unsigned long l1_to_asic:1; /* RW, W1C */
844 unsigned long ltc_int:1; /* RW, W1C */
845 unsigned long la_seq_trigger:1; /* RW, W1C */
846 unsigned long ipi_int:1; /* RW, W1C */
847 unsigned long extio_int0:1; /* RW, W1C */
848 unsigned long extio_int1:1; /* RW, W1C */
849 unsigned long extio_int2:1; /* RW, W1C */
850 unsigned long extio_int3:1; /* RW, W1C */
851 unsigned long profile_int:1; /* RW, W1C */
852 unsigned long rtc0:1; /* RW, W1C */
853 unsigned long rtc1:1; /* RW, W1C */
854 unsigned long rtc2:1; /* RW, W1C */
855 unsigned long rtc3:1; /* RW, W1C */
856 unsigned long bau_data:1; /* RW, W1C */
857 unsigned long power_management_req:1; /* RW, W1C */
858 unsigned long rsvd_57_63:7;
859 } s1;
860 struct uvxh_event_occurred0_s { 392 struct uvxh_event_occurred0_s {
861 unsigned long lb_hcerr:1; /* RW */ 393 unsigned long lb_hcerr:1; /* RW */
862 unsigned long qp_hcerr:1; /* RW */ 394 unsigned long qp_hcerr:1; /* RW */
@@ -919,152 +451,19 @@ union uvh_event_occurred0_u {
919 unsigned long profile_int:1; /* RW */ 451 unsigned long profile_int:1; /* RW */
920 unsigned long rsvd_59_63:5; 452 unsigned long rsvd_59_63:5;
921 } sx; 453 } sx;
922 struct uv2h_event_occurred0_s {
923 unsigned long lb_hcerr:1; /* RW */
924 unsigned long qp_hcerr:1; /* RW */
925 unsigned long rh_hcerr:1; /* RW */
926 unsigned long lh0_hcerr:1; /* RW */
927 unsigned long lh1_hcerr:1; /* RW */
928 unsigned long gr0_hcerr:1; /* RW */
929 unsigned long gr1_hcerr:1; /* RW */
930 unsigned long ni0_hcerr:1; /* RW */
931 unsigned long ni1_hcerr:1; /* RW */
932 unsigned long lb_aoerr0:1; /* RW */
933 unsigned long qp_aoerr0:1; /* RW */
934 unsigned long rh_aoerr0:1; /* RW */
935 unsigned long lh0_aoerr0:1; /* RW */
936 unsigned long lh1_aoerr0:1; /* RW */
937 unsigned long gr0_aoerr0:1; /* RW */
938 unsigned long gr1_aoerr0:1; /* RW */
939 unsigned long xb_aoerr0:1; /* RW */
940 unsigned long rt_aoerr0:1; /* RW */
941 unsigned long ni0_aoerr0:1; /* RW */
942 unsigned long ni1_aoerr0:1; /* RW */
943 unsigned long lb_aoerr1:1; /* RW */
944 unsigned long qp_aoerr1:1; /* RW */
945 unsigned long rh_aoerr1:1; /* RW */
946 unsigned long lh0_aoerr1:1; /* RW */
947 unsigned long lh1_aoerr1:1; /* RW */
948 unsigned long gr0_aoerr1:1; /* RW */
949 unsigned long gr1_aoerr1:1; /* RW */
950 unsigned long xb_aoerr1:1; /* RW */
951 unsigned long rt_aoerr1:1; /* RW */
952 unsigned long ni0_aoerr1:1; /* RW */
953 unsigned long ni1_aoerr1:1; /* RW */
954 unsigned long system_shutdown_int:1; /* RW */
955 unsigned long lb_irq_int_0:1; /* RW */
956 unsigned long lb_irq_int_1:1; /* RW */
957 unsigned long lb_irq_int_2:1; /* RW */
958 unsigned long lb_irq_int_3:1; /* RW */
959 unsigned long lb_irq_int_4:1; /* RW */
960 unsigned long lb_irq_int_5:1; /* RW */
961 unsigned long lb_irq_int_6:1; /* RW */
962 unsigned long lb_irq_int_7:1; /* RW */
963 unsigned long lb_irq_int_8:1; /* RW */
964 unsigned long lb_irq_int_9:1; /* RW */
965 unsigned long lb_irq_int_10:1; /* RW */
966 unsigned long lb_irq_int_11:1; /* RW */
967 unsigned long lb_irq_int_12:1; /* RW */
968 unsigned long lb_irq_int_13:1; /* RW */
969 unsigned long lb_irq_int_14:1; /* RW */
970 unsigned long lb_irq_int_15:1; /* RW */
971 unsigned long l1_nmi_int:1; /* RW */
972 unsigned long stop_clock:1; /* RW */
973 unsigned long asic_to_l1:1; /* RW */
974 unsigned long l1_to_asic:1; /* RW */
975 unsigned long la_seq_trigger:1; /* RW */
976 unsigned long ipi_int:1; /* RW */
977 unsigned long extio_int0:1; /* RW */
978 unsigned long extio_int1:1; /* RW */
979 unsigned long extio_int2:1; /* RW */
980 unsigned long extio_int3:1; /* RW */
981 unsigned long profile_int:1; /* RW */
982 unsigned long rsvd_59_63:5;
983 } s2;
984 struct uv3h_event_occurred0_s {
985 unsigned long lb_hcerr:1; /* RW */
986 unsigned long qp_hcerr:1; /* RW */
987 unsigned long rh_hcerr:1; /* RW */
988 unsigned long lh0_hcerr:1; /* RW */
989 unsigned long lh1_hcerr:1; /* RW */
990 unsigned long gr0_hcerr:1; /* RW */
991 unsigned long gr1_hcerr:1; /* RW */
992 unsigned long ni0_hcerr:1; /* RW */
993 unsigned long ni1_hcerr:1; /* RW */
994 unsigned long lb_aoerr0:1; /* RW */
995 unsigned long qp_aoerr0:1; /* RW */
996 unsigned long rh_aoerr0:1; /* RW */
997 unsigned long lh0_aoerr0:1; /* RW */
998 unsigned long lh1_aoerr0:1; /* RW */
999 unsigned long gr0_aoerr0:1; /* RW */
1000 unsigned long gr1_aoerr0:1; /* RW */
1001 unsigned long xb_aoerr0:1; /* RW */
1002 unsigned long rt_aoerr0:1; /* RW */
1003 unsigned long ni0_aoerr0:1; /* RW */
1004 unsigned long ni1_aoerr0:1; /* RW */
1005 unsigned long lb_aoerr1:1; /* RW */
1006 unsigned long qp_aoerr1:1; /* RW */
1007 unsigned long rh_aoerr1:1; /* RW */
1008 unsigned long lh0_aoerr1:1; /* RW */
1009 unsigned long lh1_aoerr1:1; /* RW */
1010 unsigned long gr0_aoerr1:1; /* RW */
1011 unsigned long gr1_aoerr1:1; /* RW */
1012 unsigned long xb_aoerr1:1; /* RW */
1013 unsigned long rt_aoerr1:1; /* RW */
1014 unsigned long ni0_aoerr1:1; /* RW */
1015 unsigned long ni1_aoerr1:1; /* RW */
1016 unsigned long system_shutdown_int:1; /* RW */
1017 unsigned long lb_irq_int_0:1; /* RW */
1018 unsigned long lb_irq_int_1:1; /* RW */
1019 unsigned long lb_irq_int_2:1; /* RW */
1020 unsigned long lb_irq_int_3:1; /* RW */
1021 unsigned long lb_irq_int_4:1; /* RW */
1022 unsigned long lb_irq_int_5:1; /* RW */
1023 unsigned long lb_irq_int_6:1; /* RW */
1024 unsigned long lb_irq_int_7:1; /* RW */
1025 unsigned long lb_irq_int_8:1; /* RW */
1026 unsigned long lb_irq_int_9:1; /* RW */
1027 unsigned long lb_irq_int_10:1; /* RW */
1028 unsigned long lb_irq_int_11:1; /* RW */
1029 unsigned long lb_irq_int_12:1; /* RW */
1030 unsigned long lb_irq_int_13:1; /* RW */
1031 unsigned long lb_irq_int_14:1; /* RW */
1032 unsigned long lb_irq_int_15:1; /* RW */
1033 unsigned long l1_nmi_int:1; /* RW */
1034 unsigned long stop_clock:1; /* RW */
1035 unsigned long asic_to_l1:1; /* RW */
1036 unsigned long l1_to_asic:1; /* RW */
1037 unsigned long la_seq_trigger:1; /* RW */
1038 unsigned long ipi_int:1; /* RW */
1039 unsigned long extio_int0:1; /* RW */
1040 unsigned long extio_int1:1; /* RW */
1041 unsigned long extio_int2:1; /* RW */
1042 unsigned long extio_int3:1; /* RW */
1043 unsigned long profile_int:1; /* RW */
1044 unsigned long rsvd_59_63:5;
1045 } s3;
1046}; 454};
1047 455
1048/* ========================================================================= */ 456/* ========================================================================= */
1049/* UVH_EVENT_OCCURRED0_ALIAS */ 457/* UVH_EVENT_OCCURRED0_ALIAS */
1050/* ========================================================================= */ 458/* ========================================================================= */
1051#define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL 459#define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
1052#define UV1H_EVENT_OCCURRED0_ALIAS 0x70008UL
1053#define UV2H_EVENT_OCCURRED0_ALIAS 0x70008UL
1054#define UV3H_EVENT_OCCURRED0_ALIAS 0x70008UL
1055#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0 460#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
1056#define UV1H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
1057#define UV2H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
1058#define UV3H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
1059 461
1060 462
1061/* ========================================================================= */ 463/* ========================================================================= */
1062/* UVH_GR0_TLB_INT0_CONFIG */ 464/* UVH_GR0_TLB_INT0_CONFIG */
1063/* ========================================================================= */ 465/* ========================================================================= */
1064#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL 466#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
1065#define UV1H_GR0_TLB_INT0_CONFIG 0x61b00UL
1066#define UV2H_GR0_TLB_INT0_CONFIG 0x61b00UL
1067#define UV3H_GR0_TLB_INT0_CONFIG 0x61b00UL
1068 467
1069#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 468#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
1070#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 469#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
@@ -1083,74 +482,6 @@ union uvh_event_occurred0_u {
1083#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 482#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1084#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 483#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1085 484
1086#define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
1087#define UV1H_GR0_TLB_INT0_CONFIG_DM_SHFT 8
1088#define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1089#define UV1H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
1090#define UV1H_GR0_TLB_INT0_CONFIG_P_SHFT 13
1091#define UV1H_GR0_TLB_INT0_CONFIG_T_SHFT 15
1092#define UV1H_GR0_TLB_INT0_CONFIG_M_SHFT 16
1093#define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1094#define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1095#define UV1H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1096#define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1097#define UV1H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1098#define UV1H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1099#define UV1H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1100#define UV1H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1101#define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1102
1103#define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
1104#define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
1105#define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1106#define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
1107#define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT 13
1108#define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT 15
1109#define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT 16
1110#define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1111#define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1112#define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1113#define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1114#define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1115#define UVXH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1116#define UVXH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1117#define UVXH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1118#define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1119
1120#define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
1121#define UV2H_GR0_TLB_INT0_CONFIG_DM_SHFT 8
1122#define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1123#define UV2H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
1124#define UV2H_GR0_TLB_INT0_CONFIG_P_SHFT 13
1125#define UV2H_GR0_TLB_INT0_CONFIG_T_SHFT 15
1126#define UV2H_GR0_TLB_INT0_CONFIG_M_SHFT 16
1127#define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1128#define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1129#define UV2H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1130#define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1131#define UV2H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1132#define UV2H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1133#define UV2H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1134#define UV2H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1135#define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1136
1137#define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
1138#define UV3H_GR0_TLB_INT0_CONFIG_DM_SHFT 8
1139#define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1140#define UV3H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
1141#define UV3H_GR0_TLB_INT0_CONFIG_P_SHFT 13
1142#define UV3H_GR0_TLB_INT0_CONFIG_T_SHFT 15
1143#define UV3H_GR0_TLB_INT0_CONFIG_M_SHFT 16
1144#define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1145#define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1146#define UV3H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1147#define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1148#define UV3H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1149#define UV3H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1150#define UV3H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1151#define UV3H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1152#define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1153
1154union uvh_gr0_tlb_int0_config_u { 485union uvh_gr0_tlb_int0_config_u {
1155 unsigned long v; 486 unsigned long v;
1156 struct uvh_gr0_tlb_int0_config_s { 487 struct uvh_gr0_tlb_int0_config_s {
@@ -1165,63 +496,12 @@ union uvh_gr0_tlb_int0_config_u {
1165 unsigned long rsvd_17_31:15; 496 unsigned long rsvd_17_31:15;
1166 unsigned long apic_id:32; /* RW */ 497 unsigned long apic_id:32; /* RW */
1167 } s; 498 } s;
1168 struct uv1h_gr0_tlb_int0_config_s {
1169 unsigned long vector_:8; /* RW */
1170 unsigned long dm:3; /* RW */
1171 unsigned long destmode:1; /* RW */
1172 unsigned long status:1; /* RO */
1173 unsigned long p:1; /* RO */
1174 unsigned long rsvd_14:1;
1175 unsigned long t:1; /* RO */
1176 unsigned long m:1; /* RW */
1177 unsigned long rsvd_17_31:15;
1178 unsigned long apic_id:32; /* RW */
1179 } s1;
1180 struct uvxh_gr0_tlb_int0_config_s {
1181 unsigned long vector_:8; /* RW */
1182 unsigned long dm:3; /* RW */
1183 unsigned long destmode:1; /* RW */
1184 unsigned long status:1; /* RO */
1185 unsigned long p:1; /* RO */
1186 unsigned long rsvd_14:1;
1187 unsigned long t:1; /* RO */
1188 unsigned long m:1; /* RW */
1189 unsigned long rsvd_17_31:15;
1190 unsigned long apic_id:32; /* RW */
1191 } sx;
1192 struct uv2h_gr0_tlb_int0_config_s {
1193 unsigned long vector_:8; /* RW */
1194 unsigned long dm:3; /* RW */
1195 unsigned long destmode:1; /* RW */
1196 unsigned long status:1; /* RO */
1197 unsigned long p:1; /* RO */
1198 unsigned long rsvd_14:1;
1199 unsigned long t:1; /* RO */
1200 unsigned long m:1; /* RW */
1201 unsigned long rsvd_17_31:15;
1202 unsigned long apic_id:32; /* RW */
1203 } s2;
1204 struct uv3h_gr0_tlb_int0_config_s {
1205 unsigned long vector_:8; /* RW */
1206 unsigned long dm:3; /* RW */
1207 unsigned long destmode:1; /* RW */
1208 unsigned long status:1; /* RO */
1209 unsigned long p:1; /* RO */
1210 unsigned long rsvd_14:1;
1211 unsigned long t:1; /* RO */
1212 unsigned long m:1; /* RW */
1213 unsigned long rsvd_17_31:15;
1214 unsigned long apic_id:32; /* RW */
1215 } s3;
1216}; 499};
1217 500
1218/* ========================================================================= */ 501/* ========================================================================= */
1219/* UVH_GR0_TLB_INT1_CONFIG */ 502/* UVH_GR0_TLB_INT1_CONFIG */
1220/* ========================================================================= */ 503/* ========================================================================= */
1221#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL 504#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
1222#define UV1H_GR0_TLB_INT1_CONFIG 0x61b40UL
1223#define UV2H_GR0_TLB_INT1_CONFIG 0x61b40UL
1224#define UV3H_GR0_TLB_INT1_CONFIG 0x61b40UL
1225 505
1226#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 506#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
1227#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 507#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
@@ -1240,74 +520,6 @@ union uvh_gr0_tlb_int0_config_u {
1240#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 520#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1241#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 521#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1242 522
1243#define UV1H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
1244#define UV1H_GR0_TLB_INT1_CONFIG_DM_SHFT 8
1245#define UV1H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1246#define UV1H_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
1247#define UV1H_GR0_TLB_INT1_CONFIG_P_SHFT 13
1248#define UV1H_GR0_TLB_INT1_CONFIG_T_SHFT 15
1249#define UV1H_GR0_TLB_INT1_CONFIG_M_SHFT 16
1250#define UV1H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1251#define UV1H_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1252#define UV1H_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1253#define UV1H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1254#define UV1H_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1255#define UV1H_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1256#define UV1H_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1257#define UV1H_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1258#define UV1H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1259
1260#define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
1261#define UVXH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
1262#define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1263#define UVXH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
1264#define UVXH_GR0_TLB_INT1_CONFIG_P_SHFT 13
1265#define UVXH_GR0_TLB_INT1_CONFIG_T_SHFT 15
1266#define UVXH_GR0_TLB_INT1_CONFIG_M_SHFT 16
1267#define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1268#define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1269#define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1270#define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1271#define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1272#define UVXH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1273#define UVXH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1274#define UVXH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1275#define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1276
1277#define UV2H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
1278#define UV2H_GR0_TLB_INT1_CONFIG_DM_SHFT 8
1279#define UV2H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1280#define UV2H_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
1281#define UV2H_GR0_TLB_INT1_CONFIG_P_SHFT 13
1282#define UV2H_GR0_TLB_INT1_CONFIG_T_SHFT 15
1283#define UV2H_GR0_TLB_INT1_CONFIG_M_SHFT 16
1284#define UV2H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1285#define UV2H_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1286#define UV2H_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1287#define UV2H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1288#define UV2H_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1289#define UV2H_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1290#define UV2H_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1291#define UV2H_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1292#define UV2H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1293
1294#define UV3H_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
1295#define UV3H_GR0_TLB_INT1_CONFIG_DM_SHFT 8
1296#define UV3H_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1297#define UV3H_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
1298#define UV3H_GR0_TLB_INT1_CONFIG_P_SHFT 13
1299#define UV3H_GR0_TLB_INT1_CONFIG_T_SHFT 15
1300#define UV3H_GR0_TLB_INT1_CONFIG_M_SHFT 16
1301#define UV3H_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1302#define UV3H_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1303#define UV3H_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1304#define UV3H_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1305#define UV3H_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1306#define UV3H_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1307#define UV3H_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1308#define UV3H_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1309#define UV3H_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1310
1311union uvh_gr0_tlb_int1_config_u { 523union uvh_gr0_tlb_int1_config_u {
1312 unsigned long v; 524 unsigned long v;
1313 struct uvh_gr0_tlb_int1_config_s { 525 struct uvh_gr0_tlb_int1_config_s {
@@ -1322,54 +534,6 @@ union uvh_gr0_tlb_int1_config_u {
1322 unsigned long rsvd_17_31:15; 534 unsigned long rsvd_17_31:15;
1323 unsigned long apic_id:32; /* RW */ 535 unsigned long apic_id:32; /* RW */
1324 } s; 536 } s;
1325 struct uv1h_gr0_tlb_int1_config_s {
1326 unsigned long vector_:8; /* RW */
1327 unsigned long dm:3; /* RW */
1328 unsigned long destmode:1; /* RW */
1329 unsigned long status:1; /* RO */
1330 unsigned long p:1; /* RO */
1331 unsigned long rsvd_14:1;
1332 unsigned long t:1; /* RO */
1333 unsigned long m:1; /* RW */
1334 unsigned long rsvd_17_31:15;
1335 unsigned long apic_id:32; /* RW */
1336 } s1;
1337 struct uvxh_gr0_tlb_int1_config_s {
1338 unsigned long vector_:8; /* RW */
1339 unsigned long dm:3; /* RW */
1340 unsigned long destmode:1; /* RW */
1341 unsigned long status:1; /* RO */
1342 unsigned long p:1; /* RO */
1343 unsigned long rsvd_14:1;
1344 unsigned long t:1; /* RO */
1345 unsigned long m:1; /* RW */
1346 unsigned long rsvd_17_31:15;
1347 unsigned long apic_id:32; /* RW */
1348 } sx;
1349 struct uv2h_gr0_tlb_int1_config_s {
1350 unsigned long vector_:8; /* RW */
1351 unsigned long dm:3; /* RW */
1352 unsigned long destmode:1; /* RW */
1353 unsigned long status:1; /* RO */
1354 unsigned long p:1; /* RO */
1355 unsigned long rsvd_14:1;
1356 unsigned long t:1; /* RO */
1357 unsigned long m:1; /* RW */
1358 unsigned long rsvd_17_31:15;
1359 unsigned long apic_id:32; /* RW */
1360 } s2;
1361 struct uv3h_gr0_tlb_int1_config_s {
1362 unsigned long vector_:8; /* RW */
1363 unsigned long dm:3; /* RW */
1364 unsigned long destmode:1; /* RW */
1365 unsigned long status:1; /* RO */
1366 unsigned long p:1; /* RO */
1367 unsigned long rsvd_14:1;
1368 unsigned long t:1; /* RO */
1369 unsigned long m:1; /* RW */
1370 unsigned long rsvd_17_31:15;
1371 unsigned long apic_id:32; /* RW */
1372 } s3;
1373}; 537};
1374 538
1375/* ========================================================================= */ 539/* ========================================================================= */
@@ -1742,9 +906,6 @@ union uvh_gr0_tlb_mmr_read_data_lo_u {
1742/* UVH_GR1_TLB_INT0_CONFIG */ 906/* UVH_GR1_TLB_INT0_CONFIG */
1743/* ========================================================================= */ 907/* ========================================================================= */
1744#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 908#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
1745#define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
1746#define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
1747#define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
1748 909
1749#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 910#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
1750#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 911#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
@@ -1763,74 +924,6 @@ union uvh_gr0_tlb_mmr_read_data_lo_u {
1763#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 924#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1764#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 925#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1765 926
1766#define UV1H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
1767#define UV1H_GR1_TLB_INT0_CONFIG_DM_SHFT 8
1768#define UV1H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1769#define UV1H_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
1770#define UV1H_GR1_TLB_INT0_CONFIG_P_SHFT 13
1771#define UV1H_GR1_TLB_INT0_CONFIG_T_SHFT 15
1772#define UV1H_GR1_TLB_INT0_CONFIG_M_SHFT 16
1773#define UV1H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1774#define UV1H_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1775#define UV1H_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1776#define UV1H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1777#define UV1H_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1778#define UV1H_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1779#define UV1H_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1780#define UV1H_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1781#define UV1H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1782
1783#define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
1784#define UVXH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
1785#define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1786#define UVXH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
1787#define UVXH_GR1_TLB_INT0_CONFIG_P_SHFT 13
1788#define UVXH_GR1_TLB_INT0_CONFIG_T_SHFT 15
1789#define UVXH_GR1_TLB_INT0_CONFIG_M_SHFT 16
1790#define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1791#define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1792#define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1793#define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1794#define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1795#define UVXH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1796#define UVXH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1797#define UVXH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1798#define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1799
1800#define UV2H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
1801#define UV2H_GR1_TLB_INT0_CONFIG_DM_SHFT 8
1802#define UV2H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1803#define UV2H_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
1804#define UV2H_GR1_TLB_INT0_CONFIG_P_SHFT 13
1805#define UV2H_GR1_TLB_INT0_CONFIG_T_SHFT 15
1806#define UV2H_GR1_TLB_INT0_CONFIG_M_SHFT 16
1807#define UV2H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1808#define UV2H_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1809#define UV2H_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1810#define UV2H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1811#define UV2H_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1812#define UV2H_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1813#define UV2H_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1814#define UV2H_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1815#define UV2H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1816
1817#define UV3H_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
1818#define UV3H_GR1_TLB_INT0_CONFIG_DM_SHFT 8
1819#define UV3H_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
1820#define UV3H_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
1821#define UV3H_GR1_TLB_INT0_CONFIG_P_SHFT 13
1822#define UV3H_GR1_TLB_INT0_CONFIG_T_SHFT 15
1823#define UV3H_GR1_TLB_INT0_CONFIG_M_SHFT 16
1824#define UV3H_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
1825#define UV3H_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1826#define UV3H_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
1827#define UV3H_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1828#define UV3H_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
1829#define UV3H_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
1830#define UV3H_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
1831#define UV3H_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
1832#define UV3H_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1833
1834union uvh_gr1_tlb_int0_config_u { 927union uvh_gr1_tlb_int0_config_u {
1835 unsigned long v; 928 unsigned long v;
1836 struct uvh_gr1_tlb_int0_config_s { 929 struct uvh_gr1_tlb_int0_config_s {
@@ -1845,63 +938,12 @@ union uvh_gr1_tlb_int0_config_u {
1845 unsigned long rsvd_17_31:15; 938 unsigned long rsvd_17_31:15;
1846 unsigned long apic_id:32; /* RW */ 939 unsigned long apic_id:32; /* RW */
1847 } s; 940 } s;
1848 struct uv1h_gr1_tlb_int0_config_s {
1849 unsigned long vector_:8; /* RW */
1850 unsigned long dm:3; /* RW */
1851 unsigned long destmode:1; /* RW */
1852 unsigned long status:1; /* RO */
1853 unsigned long p:1; /* RO */
1854 unsigned long rsvd_14:1;
1855 unsigned long t:1; /* RO */
1856 unsigned long m:1; /* RW */
1857 unsigned long rsvd_17_31:15;
1858 unsigned long apic_id:32; /* RW */
1859 } s1;
1860 struct uvxh_gr1_tlb_int0_config_s {
1861 unsigned long vector_:8; /* RW */
1862 unsigned long dm:3; /* RW */
1863 unsigned long destmode:1; /* RW */
1864 unsigned long status:1; /* RO */
1865 unsigned long p:1; /* RO */
1866 unsigned long rsvd_14:1;
1867 unsigned long t:1; /* RO */
1868 unsigned long m:1; /* RW */
1869 unsigned long rsvd_17_31:15;
1870 unsigned long apic_id:32; /* RW */
1871 } sx;
1872 struct uv2h_gr1_tlb_int0_config_s {
1873 unsigned long vector_:8; /* RW */
1874 unsigned long dm:3; /* RW */
1875 unsigned long destmode:1; /* RW */
1876 unsigned long status:1; /* RO */
1877 unsigned long p:1; /* RO */
1878 unsigned long rsvd_14:1;
1879 unsigned long t:1; /* RO */
1880 unsigned long m:1; /* RW */
1881 unsigned long rsvd_17_31:15;
1882 unsigned long apic_id:32; /* RW */
1883 } s2;
1884 struct uv3h_gr1_tlb_int0_config_s {
1885 unsigned long vector_:8; /* RW */
1886 unsigned long dm:3; /* RW */
1887 unsigned long destmode:1; /* RW */
1888 unsigned long status:1; /* RO */
1889 unsigned long p:1; /* RO */
1890 unsigned long rsvd_14:1;
1891 unsigned long t:1; /* RO */
1892 unsigned long m:1; /* RW */
1893 unsigned long rsvd_17_31:15;
1894 unsigned long apic_id:32; /* RW */
1895 } s3;
1896}; 941};
1897 942
1898/* ========================================================================= */ 943/* ========================================================================= */
1899/* UVH_GR1_TLB_INT1_CONFIG */ 944/* UVH_GR1_TLB_INT1_CONFIG */
1900/* ========================================================================= */ 945/* ========================================================================= */
1901#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 946#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
1902#define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
1903#define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
1904#define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
1905 947
1906#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 948#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
1907#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 949#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
@@ -1920,74 +962,6 @@ union uvh_gr1_tlb_int0_config_u {
1920#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 962#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1921#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 963#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1922 964
1923#define UV1H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
1924#define UV1H_GR1_TLB_INT1_CONFIG_DM_SHFT 8
1925#define UV1H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1926#define UV1H_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
1927#define UV1H_GR1_TLB_INT1_CONFIG_P_SHFT 13
1928#define UV1H_GR1_TLB_INT1_CONFIG_T_SHFT 15
1929#define UV1H_GR1_TLB_INT1_CONFIG_M_SHFT 16
1930#define UV1H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1931#define UV1H_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1932#define UV1H_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1933#define UV1H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1934#define UV1H_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1935#define UV1H_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1936#define UV1H_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1937#define UV1H_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1938#define UV1H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1939
1940#define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
1941#define UVXH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
1942#define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1943#define UVXH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
1944#define UVXH_GR1_TLB_INT1_CONFIG_P_SHFT 13
1945#define UVXH_GR1_TLB_INT1_CONFIG_T_SHFT 15
1946#define UVXH_GR1_TLB_INT1_CONFIG_M_SHFT 16
1947#define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1948#define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1949#define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1950#define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1951#define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1952#define UVXH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1953#define UVXH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1954#define UVXH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1955#define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1956
1957#define UV2H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
1958#define UV2H_GR1_TLB_INT1_CONFIG_DM_SHFT 8
1959#define UV2H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1960#define UV2H_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
1961#define UV2H_GR1_TLB_INT1_CONFIG_P_SHFT 13
1962#define UV2H_GR1_TLB_INT1_CONFIG_T_SHFT 15
1963#define UV2H_GR1_TLB_INT1_CONFIG_M_SHFT 16
1964#define UV2H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1965#define UV2H_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1966#define UV2H_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1967#define UV2H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1968#define UV2H_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1969#define UV2H_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1970#define UV2H_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1971#define UV2H_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1972#define UV2H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1973
1974#define UV3H_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
1975#define UV3H_GR1_TLB_INT1_CONFIG_DM_SHFT 8
1976#define UV3H_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
1977#define UV3H_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
1978#define UV3H_GR1_TLB_INT1_CONFIG_P_SHFT 13
1979#define UV3H_GR1_TLB_INT1_CONFIG_T_SHFT 15
1980#define UV3H_GR1_TLB_INT1_CONFIG_M_SHFT 16
1981#define UV3H_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
1982#define UV3H_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1983#define UV3H_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
1984#define UV3H_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1985#define UV3H_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
1986#define UV3H_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
1987#define UV3H_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
1988#define UV3H_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
1989#define UV3H_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1990
1991union uvh_gr1_tlb_int1_config_u { 965union uvh_gr1_tlb_int1_config_u {
1992 unsigned long v; 966 unsigned long v;
1993 struct uvh_gr1_tlb_int1_config_s { 967 struct uvh_gr1_tlb_int1_config_s {
@@ -2002,54 +976,6 @@ union uvh_gr1_tlb_int1_config_u {
2002 unsigned long rsvd_17_31:15; 976 unsigned long rsvd_17_31:15;
2003 unsigned long apic_id:32; /* RW */ 977 unsigned long apic_id:32; /* RW */
2004 } s; 978 } s;
2005 struct uv1h_gr1_tlb_int1_config_s {
2006 unsigned long vector_:8; /* RW */
2007 unsigned long dm:3; /* RW */
2008 unsigned long destmode:1; /* RW */
2009 unsigned long status:1; /* RO */
2010 unsigned long p:1; /* RO */
2011 unsigned long rsvd_14:1;
2012 unsigned long t:1; /* RO */
2013 unsigned long m:1; /* RW */
2014 unsigned long rsvd_17_31:15;
2015 unsigned long apic_id:32; /* RW */
2016 } s1;
2017 struct uvxh_gr1_tlb_int1_config_s {
2018 unsigned long vector_:8; /* RW */
2019 unsigned long dm:3; /* RW */
2020 unsigned long destmode:1; /* RW */
2021 unsigned long status:1; /* RO */
2022 unsigned long p:1; /* RO */
2023 unsigned long rsvd_14:1;
2024 unsigned long t:1; /* RO */
2025 unsigned long m:1; /* RW */
2026 unsigned long rsvd_17_31:15;
2027 unsigned long apic_id:32; /* RW */
2028 } sx;
2029 struct uv2h_gr1_tlb_int1_config_s {
2030 unsigned long vector_:8; /* RW */
2031 unsigned long dm:3; /* RW */
2032 unsigned long destmode:1; /* RW */
2033 unsigned long status:1; /* RO */
2034 unsigned long p:1; /* RO */
2035 unsigned long rsvd_14:1;
2036 unsigned long t:1; /* RO */
2037 unsigned long m:1; /* RW */
2038 unsigned long rsvd_17_31:15;
2039 unsigned long apic_id:32; /* RW */
2040 } s2;
2041 struct uv3h_gr1_tlb_int1_config_s {
2042 unsigned long vector_:8; /* RW */
2043 unsigned long dm:3; /* RW */
2044 unsigned long destmode:1; /* RW */
2045 unsigned long status:1; /* RO */
2046 unsigned long p:1; /* RO */
2047 unsigned long rsvd_14:1;
2048 unsigned long t:1; /* RO */
2049 unsigned long m:1; /* RW */
2050 unsigned long rsvd_17_31:15;
2051 unsigned long apic_id:32; /* RW */
2052 } s3;
2053}; 979};
2054 980
2055/* ========================================================================= */ 981/* ========================================================================= */
@@ -2422,56 +1348,22 @@ union uvh_gr1_tlb_mmr_read_data_lo_u {
2422/* UVH_INT_CMPB */ 1348/* UVH_INT_CMPB */
2423/* ========================================================================= */ 1349/* ========================================================================= */
2424#define UVH_INT_CMPB 0x22080UL 1350#define UVH_INT_CMPB 0x22080UL
2425#define UV1H_INT_CMPB 0x22080UL
2426#define UV2H_INT_CMPB 0x22080UL
2427#define UV3H_INT_CMPB 0x22080UL
2428 1351
2429#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1352#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
2430#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1353#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
2431 1354
2432#define UV1H_INT_CMPB_REAL_TIME_CMPB_SHFT 0
2433#define UV1H_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
2434
2435#define UVXH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
2436#define UVXH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
2437
2438#define UV2H_INT_CMPB_REAL_TIME_CMPB_SHFT 0
2439#define UV2H_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
2440
2441#define UV3H_INT_CMPB_REAL_TIME_CMPB_SHFT 0
2442#define UV3H_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
2443
2444union uvh_int_cmpb_u { 1355union uvh_int_cmpb_u {
2445 unsigned long v; 1356 unsigned long v;
2446 struct uvh_int_cmpb_s { 1357 struct uvh_int_cmpb_s {
2447 unsigned long real_time_cmpb:56; /* RW */ 1358 unsigned long real_time_cmpb:56; /* RW */
2448 unsigned long rsvd_56_63:8; 1359 unsigned long rsvd_56_63:8;
2449 } s; 1360 } s;
2450 struct uv1h_int_cmpb_s {
2451 unsigned long real_time_cmpb:56; /* RW */
2452 unsigned long rsvd_56_63:8;
2453 } s1;
2454 struct uvxh_int_cmpb_s {
2455 unsigned long real_time_cmpb:56; /* RW */
2456 unsigned long rsvd_56_63:8;
2457 } sx;
2458 struct uv2h_int_cmpb_s {
2459 unsigned long real_time_cmpb:56; /* RW */
2460 unsigned long rsvd_56_63:8;
2461 } s2;
2462 struct uv3h_int_cmpb_s {
2463 unsigned long real_time_cmpb:56; /* RW */
2464 unsigned long rsvd_56_63:8;
2465 } s3;
2466}; 1361};
2467 1362
2468/* ========================================================================= */ 1363/* ========================================================================= */
2469/* UVH_INT_CMPC */ 1364/* UVH_INT_CMPC */
2470/* ========================================================================= */ 1365/* ========================================================================= */
2471#define UVH_INT_CMPC 0x22100UL 1366#define UVH_INT_CMPC 0x22100UL
2472#define UV1H_INT_CMPC 0x22100UL
2473#define UV2H_INT_CMPC 0x22100UL
2474#define UV3H_INT_CMPC 0x22100UL
2475 1367
2476#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1368#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0
2477#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 1369#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
@@ -2479,43 +1371,18 @@ union uvh_int_cmpb_u {
2479#define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1371#define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0
2480#define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1372#define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL
2481 1373
2482#define UV2H_INT_CMPC_REAL_TIME_CMP_2_SHFT 0
2483#define UV2H_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL
2484
2485#define UV3H_INT_CMPC_REAL_TIME_CMP_2_SHFT 0
2486#define UV3H_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL
2487
2488union uvh_int_cmpc_u { 1374union uvh_int_cmpc_u {
2489 unsigned long v; 1375 unsigned long v;
2490 struct uvh_int_cmpc_s { 1376 struct uvh_int_cmpc_s {
2491 unsigned long real_time_cmpc:56; /* RW */ 1377 unsigned long real_time_cmpc:56; /* RW */
2492 unsigned long rsvd_56_63:8; 1378 unsigned long rsvd_56_63:8;
2493 } s; 1379 } s;
2494 struct uv1h_int_cmpc_s {
2495 unsigned long real_time_cmpc:56; /* RW */
2496 unsigned long rsvd_56_63:8;
2497 } s1;
2498 struct uvxh_int_cmpc_s {
2499 unsigned long real_time_cmpc:56; /* RW */
2500 unsigned long rsvd_56_63:8;
2501 } sx;
2502 struct uv2h_int_cmpc_s {
2503 unsigned long real_time_cmpc:56; /* RW */
2504 unsigned long rsvd_56_63:8;
2505 } s2;
2506 struct uv3h_int_cmpc_s {
2507 unsigned long real_time_cmpc:56; /* RW */
2508 unsigned long rsvd_56_63:8;
2509 } s3;
2510}; 1380};
2511 1381
2512/* ========================================================================= */ 1382/* ========================================================================= */
2513/* UVH_INT_CMPD */ 1383/* UVH_INT_CMPD */
2514/* ========================================================================= */ 1384/* ========================================================================= */
2515#define UVH_INT_CMPD 0x22180UL 1385#define UVH_INT_CMPD 0x22180UL
2516#define UV1H_INT_CMPD 0x22180UL
2517#define UV2H_INT_CMPD 0x22180UL
2518#define UV3H_INT_CMPD 0x22180UL
2519 1386
2520#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1387#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0
2521#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 1388#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
@@ -2523,47 +1390,19 @@ union uvh_int_cmpc_u {
2523#define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1390#define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0
2524#define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1391#define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL
2525 1392
2526#define UV2H_INT_CMPD_REAL_TIME_CMP_3_SHFT 0
2527#define UV2H_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL
2528
2529#define UV3H_INT_CMPD_REAL_TIME_CMP_3_SHFT 0
2530#define UV3H_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL
2531
2532union uvh_int_cmpd_u { 1393union uvh_int_cmpd_u {
2533 unsigned long v; 1394 unsigned long v;
2534 struct uvh_int_cmpd_s { 1395 struct uvh_int_cmpd_s {
2535 unsigned long real_time_cmpd:56; /* RW */ 1396 unsigned long real_time_cmpd:56; /* RW */
2536 unsigned long rsvd_56_63:8; 1397 unsigned long rsvd_56_63:8;
2537 } s; 1398 } s;
2538 struct uv1h_int_cmpd_s {
2539 unsigned long real_time_cmpd:56; /* RW */
2540 unsigned long rsvd_56_63:8;
2541 } s1;
2542 struct uvxh_int_cmpd_s {
2543 unsigned long real_time_cmpd:56; /* RW */
2544 unsigned long rsvd_56_63:8;
2545 } sx;
2546 struct uv2h_int_cmpd_s {
2547 unsigned long real_time_cmpd:56; /* RW */
2548 unsigned long rsvd_56_63:8;
2549 } s2;
2550 struct uv3h_int_cmpd_s {
2551 unsigned long real_time_cmpd:56; /* RW */
2552 unsigned long rsvd_56_63:8;
2553 } s3;
2554}; 1399};
2555 1400
2556/* ========================================================================= */ 1401/* ========================================================================= */
2557/* UVH_IPI_INT */ 1402/* UVH_IPI_INT */
2558/* ========================================================================= */ 1403/* ========================================================================= */
2559#define UVH_IPI_INT 0x60500UL 1404#define UVH_IPI_INT 0x60500UL
2560#define UV1H_IPI_INT 0x60500UL
2561#define UV2H_IPI_INT 0x60500UL
2562#define UV3H_IPI_INT 0x60500UL
2563#define UVH_IPI_INT_32 0x348 1405#define UVH_IPI_INT_32 0x348
2564#define UV1H_IPI_INT_32 0x60500UL
2565#define UV2H_IPI_INT_32 0x60500UL
2566#define UV3H_IPI_INT_32 0x60500UL
2567 1406
2568#define UVH_IPI_INT_VECTOR_SHFT 0 1407#define UVH_IPI_INT_VECTOR_SHFT 0
2569#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1408#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
@@ -2576,50 +1415,6 @@ union uvh_int_cmpd_u {
2576#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1415#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
2577#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1416#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
2578 1417
2579#define UV1H_IPI_INT_VECTOR_SHFT 0
2580#define UV1H_IPI_INT_DELIVERY_MODE_SHFT 8
2581#define UV1H_IPI_INT_DESTMODE_SHFT 11
2582#define UV1H_IPI_INT_APIC_ID_SHFT 16
2583#define UV1H_IPI_INT_SEND_SHFT 63
2584#define UV1H_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
2585#define UV1H_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
2586#define UV1H_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
2587#define UV1H_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
2588#define UV1H_IPI_INT_SEND_MASK 0x8000000000000000UL
2589
2590#define UVXH_IPI_INT_VECTOR_SHFT 0
2591#define UVXH_IPI_INT_DELIVERY_MODE_SHFT 8
2592#define UVXH_IPI_INT_DESTMODE_SHFT 11
2593#define UVXH_IPI_INT_APIC_ID_SHFT 16
2594#define UVXH_IPI_INT_SEND_SHFT 63
2595#define UVXH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
2596#define UVXH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
2597#define UVXH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
2598#define UVXH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
2599#define UVXH_IPI_INT_SEND_MASK 0x8000000000000000UL
2600
2601#define UV2H_IPI_INT_VECTOR_SHFT 0
2602#define UV2H_IPI_INT_DELIVERY_MODE_SHFT 8
2603#define UV2H_IPI_INT_DESTMODE_SHFT 11
2604#define UV2H_IPI_INT_APIC_ID_SHFT 16
2605#define UV2H_IPI_INT_SEND_SHFT 63
2606#define UV2H_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
2607#define UV2H_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
2608#define UV2H_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
2609#define UV2H_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
2610#define UV2H_IPI_INT_SEND_MASK 0x8000000000000000UL
2611
2612#define UV3H_IPI_INT_VECTOR_SHFT 0
2613#define UV3H_IPI_INT_DELIVERY_MODE_SHFT 8
2614#define UV3H_IPI_INT_DESTMODE_SHFT 11
2615#define UV3H_IPI_INT_APIC_ID_SHFT 16
2616#define UV3H_IPI_INT_SEND_SHFT 63
2617#define UV3H_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
2618#define UV3H_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL
2619#define UV3H_IPI_INT_DESTMODE_MASK 0x0000000000000800UL
2620#define UV3H_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
2621#define UV3H_IPI_INT_SEND_MASK 0x8000000000000000UL
2622
2623union uvh_ipi_int_u { 1418union uvh_ipi_int_u {
2624 unsigned long v; 1419 unsigned long v;
2625 struct uvh_ipi_int_s { 1420 struct uvh_ipi_int_s {
@@ -2631,81 +1426,19 @@ union uvh_ipi_int_u {
2631 unsigned long rsvd_48_62:15; 1426 unsigned long rsvd_48_62:15;
2632 unsigned long send:1; /* WP */ 1427 unsigned long send:1; /* WP */
2633 } s; 1428 } s;
2634 struct uv1h_ipi_int_s {
2635 unsigned long vector_:8; /* RW */
2636 unsigned long delivery_mode:3; /* RW */
2637 unsigned long destmode:1; /* RW */
2638 unsigned long rsvd_12_15:4;
2639 unsigned long apic_id:32; /* RW */
2640 unsigned long rsvd_48_62:15;
2641 unsigned long send:1; /* WP */
2642 } s1;
2643 struct uvxh_ipi_int_s {
2644 unsigned long vector_:8; /* RW */
2645 unsigned long delivery_mode:3; /* RW */
2646 unsigned long destmode:1; /* RW */
2647 unsigned long rsvd_12_15:4;
2648 unsigned long apic_id:32; /* RW */
2649 unsigned long rsvd_48_62:15;
2650 unsigned long send:1; /* WP */
2651 } sx;
2652 struct uv2h_ipi_int_s {
2653 unsigned long vector_:8; /* RW */
2654 unsigned long delivery_mode:3; /* RW */
2655 unsigned long destmode:1; /* RW */
2656 unsigned long rsvd_12_15:4;
2657 unsigned long apic_id:32; /* RW */
2658 unsigned long rsvd_48_62:15;
2659 unsigned long send:1; /* WP */
2660 } s2;
2661 struct uv3h_ipi_int_s {
2662 unsigned long vector_:8; /* RW */
2663 unsigned long delivery_mode:3; /* RW */
2664 unsigned long destmode:1; /* RW */
2665 unsigned long rsvd_12_15:4;
2666 unsigned long apic_id:32; /* RW */
2667 unsigned long rsvd_48_62:15;
2668 unsigned long send:1; /* WP */
2669 } s3;
2670}; 1429};
2671 1430
2672/* ========================================================================= */ 1431/* ========================================================================= */
2673/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1432/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
2674/* ========================================================================= */ 1433/* ========================================================================= */
2675#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1434#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2676#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2677#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2678#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
2679#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1435#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
2680#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL
2681#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL
2682#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x320050UL
2683 1436
2684#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1437#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2685#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1438#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2686#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1439#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2687#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1440#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2688 1441
2689#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2690#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2691#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2692#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2693
2694#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2695#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2696#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2697#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2698
2699#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2700#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2701#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2702#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2703
2704#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
2705#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
2706#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
2707#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
2708
2709union uvh_lb_bau_intd_payload_queue_first_u { 1442union uvh_lb_bau_intd_payload_queue_first_u {
2710 unsigned long v; 1443 unsigned long v;
2711 struct uvh_lb_bau_intd_payload_queue_first_s { 1444 struct uvh_lb_bau_intd_payload_queue_first_s {
@@ -2715,63 +1448,17 @@ union uvh_lb_bau_intd_payload_queue_first_u {
2715 unsigned long node_id:14; /* RW */ 1448 unsigned long node_id:14; /* RW */
2716 unsigned long rsvd_63:1; 1449 unsigned long rsvd_63:1;
2717 } s; 1450 } s;
2718 struct uv1h_lb_bau_intd_payload_queue_first_s {
2719 unsigned long rsvd_0_3:4;
2720 unsigned long address:39; /* RW */
2721 unsigned long rsvd_43_48:6;
2722 unsigned long node_id:14; /* RW */
2723 unsigned long rsvd_63:1;
2724 } s1;
2725 struct uvxh_lb_bau_intd_payload_queue_first_s {
2726 unsigned long rsvd_0_3:4;
2727 unsigned long address:39; /* RW */
2728 unsigned long rsvd_43_48:6;
2729 unsigned long node_id:14; /* RW */
2730 unsigned long rsvd_63:1;
2731 } sx;
2732 struct uv2h_lb_bau_intd_payload_queue_first_s {
2733 unsigned long rsvd_0_3:4;
2734 unsigned long address:39; /* RW */
2735 unsigned long rsvd_43_48:6;
2736 unsigned long node_id:14; /* RW */
2737 unsigned long rsvd_63:1;
2738 } s2;
2739 struct uv3h_lb_bau_intd_payload_queue_first_s {
2740 unsigned long rsvd_0_3:4;
2741 unsigned long address:39; /* RW */
2742 unsigned long rsvd_43_48:6;
2743 unsigned long node_id:14; /* RW */
2744 unsigned long rsvd_63:1;
2745 } s3;
2746}; 1451};
2747 1452
2748/* ========================================================================= */ 1453/* ========================================================================= */
2749/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1454/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
2750/* ========================================================================= */ 1455/* ========================================================================= */
2751#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1456#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2752#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2753#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2754#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
2755#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1457#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
2756#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL
2757#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL
2758#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x320060UL
2759 1458
2760#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1459#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2761#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1460#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2762 1461
2763#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2764#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2765
2766#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2767#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2768
2769#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2770#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2771
2772#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
2773#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
2774
2775union uvh_lb_bau_intd_payload_queue_last_u { 1462union uvh_lb_bau_intd_payload_queue_last_u {
2776 unsigned long v; 1463 unsigned long v;
2777 struct uvh_lb_bau_intd_payload_queue_last_s { 1464 struct uvh_lb_bau_intd_payload_queue_last_s {
@@ -2779,55 +1466,17 @@ union uvh_lb_bau_intd_payload_queue_last_u {
2779 unsigned long address:39; /* RW */ 1466 unsigned long address:39; /* RW */
2780 unsigned long rsvd_43_63:21; 1467 unsigned long rsvd_43_63:21;
2781 } s; 1468 } s;
2782 struct uv1h_lb_bau_intd_payload_queue_last_s {
2783 unsigned long rsvd_0_3:4;
2784 unsigned long address:39; /* RW */
2785 unsigned long rsvd_43_63:21;
2786 } s1;
2787 struct uvxh_lb_bau_intd_payload_queue_last_s {
2788 unsigned long rsvd_0_3:4;
2789 unsigned long address:39; /* RW */
2790 unsigned long rsvd_43_63:21;
2791 } sx;
2792 struct uv2h_lb_bau_intd_payload_queue_last_s {
2793 unsigned long rsvd_0_3:4;
2794 unsigned long address:39; /* RW */
2795 unsigned long rsvd_43_63:21;
2796 } s2;
2797 struct uv3h_lb_bau_intd_payload_queue_last_s {
2798 unsigned long rsvd_0_3:4;
2799 unsigned long address:39; /* RW */
2800 unsigned long rsvd_43_63:21;
2801 } s3;
2802}; 1469};
2803 1470
2804/* ========================================================================= */ 1471/* ========================================================================= */
2805/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1472/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
2806/* ========================================================================= */ 1473/* ========================================================================= */
2807#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1474#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2808#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2809#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2810#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
2811#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1475#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
2812#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL
2813#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL
2814#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x320070UL
2815 1476
2816#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1477#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2817#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1478#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2818 1479
2819#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2820#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2821
2822#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2823#define UVXH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2824
2825#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2826#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2827
2828#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
2829#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
2830
2831union uvh_lb_bau_intd_payload_queue_tail_u { 1480union uvh_lb_bau_intd_payload_queue_tail_u {
2832 unsigned long v; 1481 unsigned long v;
2833 struct uvh_lb_bau_intd_payload_queue_tail_s { 1482 struct uvh_lb_bau_intd_payload_queue_tail_s {
@@ -2835,39 +1484,13 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
2835 unsigned long address:39; /* RW */ 1484 unsigned long address:39; /* RW */
2836 unsigned long rsvd_43_63:21; 1485 unsigned long rsvd_43_63:21;
2837 } s; 1486 } s;
2838 struct uv1h_lb_bau_intd_payload_queue_tail_s {
2839 unsigned long rsvd_0_3:4;
2840 unsigned long address:39; /* RW */
2841 unsigned long rsvd_43_63:21;
2842 } s1;
2843 struct uvxh_lb_bau_intd_payload_queue_tail_s {
2844 unsigned long rsvd_0_3:4;
2845 unsigned long address:39; /* RW */
2846 unsigned long rsvd_43_63:21;
2847 } sx;
2848 struct uv2h_lb_bau_intd_payload_queue_tail_s {
2849 unsigned long rsvd_0_3:4;
2850 unsigned long address:39; /* RW */
2851 unsigned long rsvd_43_63:21;
2852 } s2;
2853 struct uv3h_lb_bau_intd_payload_queue_tail_s {
2854 unsigned long rsvd_0_3:4;
2855 unsigned long address:39; /* RW */
2856 unsigned long rsvd_43_63:21;
2857 } s3;
2858}; 1487};
2859 1488
2860/* ========================================================================= */ 1489/* ========================================================================= */
2861/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1490/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
2862/* ========================================================================= */ 1491/* ========================================================================= */
2863#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 1492#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2864#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2865#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2866#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2867#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 1493#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
2868#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL
2869#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL
2870#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x320080UL
2871 1494
2872#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 1495#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2873#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 1496#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
@@ -2902,138 +1525,6 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
2902#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 1525#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2903#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 1526#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2904 1527
2905#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2906#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2907#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2908#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2909#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2910#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2911#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2912#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2913#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2914#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2915#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2916#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2917#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2918#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2919#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2920#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2921#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2922#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2923#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2924#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2925#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2926#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2927#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2928#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2929#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2930#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2931#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2932#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2933#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2934#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2935#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2936#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2937
2938#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2939#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2940#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2941#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2942#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2943#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2944#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2945#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2946#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2947#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2948#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2949#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2950#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2951#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2952#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2953#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2954#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2955#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2956#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2957#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2958#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2959#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2960#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2961#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2962#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2963#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2964#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2965#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2966#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2967#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2968#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2969#define UVXH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2970
2971#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2972#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2973#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2974#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2975#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2976#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2977#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2978#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2979#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2980#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2981#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2982#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2983#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2984#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2985#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2986#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2987#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2988#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2989#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2990#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2991#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2992#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2993#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2994#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2995#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2996#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2997#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2998#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2999#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
3000#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
3001#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
3002#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
3003
3004#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
3005#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
3006#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
3007#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
3008#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
3009#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
3010#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
3011#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
3012#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
3013#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
3014#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
3015#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
3016#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
3017#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
3018#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
3019#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
3020#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
3021#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
3022#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
3023#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
3024#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
3025#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
3026#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
3027#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
3028#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
3029#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
3030#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
3031#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
3032#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
3033#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
3034#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
3035#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
3036
3037union uvh_lb_bau_intd_software_acknowledge_u { 1528union uvh_lb_bau_intd_software_acknowledge_u {
3038 unsigned long v; 1529 unsigned long v;
3039 struct uvh_lb_bau_intd_software_acknowledge_s { 1530 struct uvh_lb_bau_intd_software_acknowledge_s {
@@ -3055,95 +1546,13 @@ union uvh_lb_bau_intd_software_acknowledge_u {
3055 unsigned long timeout_7:1; /* RW, W1C */ 1546 unsigned long timeout_7:1; /* RW, W1C */
3056 unsigned long rsvd_16_63:48; 1547 unsigned long rsvd_16_63:48;
3057 } s; 1548 } s;
3058 struct uv1h_lb_bau_intd_software_acknowledge_s {
3059 unsigned long pending_0:1; /* RW, W1C */
3060 unsigned long pending_1:1; /* RW, W1C */
3061 unsigned long pending_2:1; /* RW, W1C */
3062 unsigned long pending_3:1; /* RW, W1C */
3063 unsigned long pending_4:1; /* RW, W1C */
3064 unsigned long pending_5:1; /* RW, W1C */
3065 unsigned long pending_6:1; /* RW, W1C */
3066 unsigned long pending_7:1; /* RW, W1C */
3067 unsigned long timeout_0:1; /* RW, W1C */
3068 unsigned long timeout_1:1; /* RW, W1C */
3069 unsigned long timeout_2:1; /* RW, W1C */
3070 unsigned long timeout_3:1; /* RW, W1C */
3071 unsigned long timeout_4:1; /* RW, W1C */
3072 unsigned long timeout_5:1; /* RW, W1C */
3073 unsigned long timeout_6:1; /* RW, W1C */
3074 unsigned long timeout_7:1; /* RW, W1C */
3075 unsigned long rsvd_16_63:48;
3076 } s1;
3077 struct uvxh_lb_bau_intd_software_acknowledge_s {
3078 unsigned long pending_0:1; /* RW */
3079 unsigned long pending_1:1; /* RW */
3080 unsigned long pending_2:1; /* RW */
3081 unsigned long pending_3:1; /* RW */
3082 unsigned long pending_4:1; /* RW */
3083 unsigned long pending_5:1; /* RW */
3084 unsigned long pending_6:1; /* RW */
3085 unsigned long pending_7:1; /* RW */
3086 unsigned long timeout_0:1; /* RW */
3087 unsigned long timeout_1:1; /* RW */
3088 unsigned long timeout_2:1; /* RW */
3089 unsigned long timeout_3:1; /* RW */
3090 unsigned long timeout_4:1; /* RW */
3091 unsigned long timeout_5:1; /* RW */
3092 unsigned long timeout_6:1; /* RW */
3093 unsigned long timeout_7:1; /* RW */
3094 unsigned long rsvd_16_63:48;
3095 } sx;
3096 struct uv2h_lb_bau_intd_software_acknowledge_s {
3097 unsigned long pending_0:1; /* RW */
3098 unsigned long pending_1:1; /* RW */
3099 unsigned long pending_2:1; /* RW */
3100 unsigned long pending_3:1; /* RW */
3101 unsigned long pending_4:1; /* RW */
3102 unsigned long pending_5:1; /* RW */
3103 unsigned long pending_6:1; /* RW */
3104 unsigned long pending_7:1; /* RW */
3105 unsigned long timeout_0:1; /* RW */
3106 unsigned long timeout_1:1; /* RW */
3107 unsigned long timeout_2:1; /* RW */
3108 unsigned long timeout_3:1; /* RW */
3109 unsigned long timeout_4:1; /* RW */
3110 unsigned long timeout_5:1; /* RW */
3111 unsigned long timeout_6:1; /* RW */
3112 unsigned long timeout_7:1; /* RW */
3113 unsigned long rsvd_16_63:48;
3114 } s2;
3115 struct uv3h_lb_bau_intd_software_acknowledge_s {
3116 unsigned long pending_0:1; /* RW */
3117 unsigned long pending_1:1; /* RW */
3118 unsigned long pending_2:1; /* RW */
3119 unsigned long pending_3:1; /* RW */
3120 unsigned long pending_4:1; /* RW */
3121 unsigned long pending_5:1; /* RW */
3122 unsigned long pending_6:1; /* RW */
3123 unsigned long pending_7:1; /* RW */
3124 unsigned long timeout_0:1; /* RW */
3125 unsigned long timeout_1:1; /* RW */
3126 unsigned long timeout_2:1; /* RW */
3127 unsigned long timeout_3:1; /* RW */
3128 unsigned long timeout_4:1; /* RW */
3129 unsigned long timeout_5:1; /* RW */
3130 unsigned long timeout_6:1; /* RW */
3131 unsigned long timeout_7:1; /* RW */
3132 unsigned long rsvd_16_63:48;
3133 } s3;
3134}; 1549};
3135 1550
3136/* ========================================================================= */ 1551/* ========================================================================= */
3137/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 1552/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
3138/* ========================================================================= */ 1553/* ========================================================================= */
3139#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 1554#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
3140#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
3141#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
3142#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
3143#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 1555#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
3144#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x320088UL
3145#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x320088UL
3146#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x320088UL
3147 1556
3148 1557
3149/* ========================================================================= */ 1558/* ========================================================================= */
@@ -3498,13 +1907,7 @@ union uvh_lb_bau_misc_control_u {
3498/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 1907/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
3499/* ========================================================================= */ 1908/* ========================================================================= */
3500#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 1909#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
3501#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
3502#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
3503#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
3504#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 1910#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
3505#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x320020UL
3506#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x320020UL
3507#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x320020UL
3508 1911
3509#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 1912#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
3510#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 1913#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
@@ -3513,34 +1916,6 @@ union uvh_lb_bau_misc_control_u {
3513#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 1916#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
3514#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 1917#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
3515 1918
3516#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
3517#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
3518#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
3519#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
3520#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
3521#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
3522
3523#define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
3524#define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
3525#define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
3526#define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
3527#define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
3528#define UVXH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
3529
3530#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
3531#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
3532#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
3533#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
3534#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
3535#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
3536
3537#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
3538#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
3539#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT 63
3540#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
3541#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
3542#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
3543
3544union uvh_lb_bau_sb_activation_control_u { 1919union uvh_lb_bau_sb_activation_control_u {
3545 unsigned long v; 1920 unsigned long v;
3546 struct uvh_lb_bau_sb_activation_control_s { 1921 struct uvh_lb_bau_sb_activation_control_s {
@@ -3549,161 +1924,51 @@ union uvh_lb_bau_sb_activation_control_u {
3549 unsigned long push:1; /* WP */ 1924 unsigned long push:1; /* WP */
3550 unsigned long init:1; /* WP */ 1925 unsigned long init:1; /* WP */
3551 } s; 1926 } s;
3552 struct uv1h_lb_bau_sb_activation_control_s {
3553 unsigned long index:6; /* RW */
3554 unsigned long rsvd_6_61:56;
3555 unsigned long push:1; /* WP */
3556 unsigned long init:1; /* WP */
3557 } s1;
3558 struct uvxh_lb_bau_sb_activation_control_s {
3559 unsigned long index:6; /* RW */
3560 unsigned long rsvd_6_61:56;
3561 unsigned long push:1; /* WP */
3562 unsigned long init:1; /* WP */
3563 } sx;
3564 struct uv2h_lb_bau_sb_activation_control_s {
3565 unsigned long index:6; /* RW */
3566 unsigned long rsvd_6_61:56;
3567 unsigned long push:1; /* WP */
3568 unsigned long init:1; /* WP */
3569 } s2;
3570 struct uv3h_lb_bau_sb_activation_control_s {
3571 unsigned long index:6; /* RW */
3572 unsigned long rsvd_6_61:56;
3573 unsigned long push:1; /* WP */
3574 unsigned long init:1; /* WP */
3575 } s3;
3576}; 1927};
3577 1928
3578/* ========================================================================= */ 1929/* ========================================================================= */
3579/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 1930/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
3580/* ========================================================================= */ 1931/* ========================================================================= */
3581#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 1932#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
3582#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
3583#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
3584#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
3585#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 1933#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
3586#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x320030UL
3587#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x320030UL
3588#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x320030UL
3589 1934
3590#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 1935#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
3591#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 1936#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
3592 1937
3593#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
3594#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
3595
3596#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
3597#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
3598
3599#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
3600#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
3601
3602#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
3603#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
3604
3605union uvh_lb_bau_sb_activation_status_0_u { 1938union uvh_lb_bau_sb_activation_status_0_u {
3606 unsigned long v; 1939 unsigned long v;
3607 struct uvh_lb_bau_sb_activation_status_0_s { 1940 struct uvh_lb_bau_sb_activation_status_0_s {
3608 unsigned long status:64; /* RW */ 1941 unsigned long status:64; /* RW */
3609 } s; 1942 } s;
3610 struct uv1h_lb_bau_sb_activation_status_0_s {
3611 unsigned long status:64; /* RW */
3612 } s1;
3613 struct uvxh_lb_bau_sb_activation_status_0_s {
3614 unsigned long status:64; /* RW */
3615 } sx;
3616 struct uv2h_lb_bau_sb_activation_status_0_s {
3617 unsigned long status:64; /* RW */
3618 } s2;
3619 struct uv3h_lb_bau_sb_activation_status_0_s {
3620 unsigned long status:64; /* RW */
3621 } s3;
3622}; 1943};
3623 1944
3624/* ========================================================================= */ 1945/* ========================================================================= */
3625/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 1946/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
3626/* ========================================================================= */ 1947/* ========================================================================= */
3627#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 1948#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
3628#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
3629#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
3630#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
3631#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 1949#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
3632#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x320040UL
3633#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x320040UL
3634#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x320040UL
3635 1950
3636#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 1951#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
3637#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 1952#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
3638 1953
3639#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
3640#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
3641
3642#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
3643#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
3644
3645#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
3646#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
3647
3648#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
3649#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
3650
3651union uvh_lb_bau_sb_activation_status_1_u { 1954union uvh_lb_bau_sb_activation_status_1_u {
3652 unsigned long v; 1955 unsigned long v;
3653 struct uvh_lb_bau_sb_activation_status_1_s { 1956 struct uvh_lb_bau_sb_activation_status_1_s {
3654 unsigned long status:64; /* RW */ 1957 unsigned long status:64; /* RW */
3655 } s; 1958 } s;
3656 struct uv1h_lb_bau_sb_activation_status_1_s {
3657 unsigned long status:64; /* RW */
3658 } s1;
3659 struct uvxh_lb_bau_sb_activation_status_1_s {
3660 unsigned long status:64; /* RW */
3661 } sx;
3662 struct uv2h_lb_bau_sb_activation_status_1_s {
3663 unsigned long status:64; /* RW */
3664 } s2;
3665 struct uv3h_lb_bau_sb_activation_status_1_s {
3666 unsigned long status:64; /* RW */
3667 } s3;
3668}; 1959};
3669 1960
3670/* ========================================================================= */ 1961/* ========================================================================= */
3671/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 1962/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
3672/* ========================================================================= */ 1963/* ========================================================================= */
3673#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 1964#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
3674#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
3675#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
3676#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
3677#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 1965#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
3678#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x320010UL
3679#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x320010UL
3680#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x320010UL
3681 1966
3682#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 1967#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
3683#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 1968#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
3684#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 1969#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
3685#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 1970#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
3686 1971
3687#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
3688#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
3689#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
3690#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
3691
3692#define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
3693#define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
3694#define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
3695#define UVXH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
3696
3697#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
3698#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
3699#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
3700#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
3701
3702#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
3703#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
3704#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
3705#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
3706
3707union uvh_lb_bau_sb_descriptor_base_u { 1972union uvh_lb_bau_sb_descriptor_base_u {
3708 unsigned long v; 1973 unsigned long v;
3709 struct uvh_lb_bau_sb_descriptor_base_s { 1974 struct uvh_lb_bau_sb_descriptor_base_s {
@@ -3713,34 +1978,6 @@ union uvh_lb_bau_sb_descriptor_base_u {
3713 unsigned long node_id:14; /* RW */ 1978 unsigned long node_id:14; /* RW */
3714 unsigned long rsvd_63:1; 1979 unsigned long rsvd_63:1;
3715 } s; 1980 } s;
3716 struct uv1h_lb_bau_sb_descriptor_base_s {
3717 unsigned long rsvd_0_11:12;
3718 unsigned long page_address:31; /* RW */
3719 unsigned long rsvd_43_48:6;
3720 unsigned long node_id:14; /* RW */
3721 unsigned long rsvd_63:1;
3722 } s1;
3723 struct uvxh_lb_bau_sb_descriptor_base_s {
3724 unsigned long rsvd_0_11:12;
3725 unsigned long page_address:31; /* RW */
3726 unsigned long rsvd_43_48:6;
3727 unsigned long node_id:14; /* RW */
3728 unsigned long rsvd_63:1;
3729 } sx;
3730 struct uv2h_lb_bau_sb_descriptor_base_s {
3731 unsigned long rsvd_0_11:12;
3732 unsigned long page_address:31; /* RW */
3733 unsigned long rsvd_43_48:6;
3734 unsigned long node_id:14; /* RW */
3735 unsigned long rsvd_63:1;
3736 } s2;
3737 struct uv3h_lb_bau_sb_descriptor_base_s {
3738 unsigned long rsvd_0_11:12;
3739 unsigned long page_address:31; /* RW */
3740 unsigned long rsvd_43_48:6;
3741 unsigned long node_id:14; /* RW */
3742 unsigned long rsvd_63:1;
3743 } s3;
3744}; 1981};
3745 1982
3746/* ========================================================================= */ 1983/* ========================================================================= */
@@ -3889,55 +2126,22 @@ union uvh_node_id_u {
3889/* UVH_NODE_PRESENT_TABLE */ 2126/* UVH_NODE_PRESENT_TABLE */
3890/* ========================================================================= */ 2127/* ========================================================================= */
3891#define UVH_NODE_PRESENT_TABLE 0x1400UL 2128#define UVH_NODE_PRESENT_TABLE 0x1400UL
3892#define UV1H_NODE_PRESENT_TABLE 0x1400UL
3893#define UV2H_NODE_PRESENT_TABLE 0x1400UL
3894#define UV3H_NODE_PRESENT_TABLE 0x1400UL
3895#define UVH_NODE_PRESENT_TABLE_DEPTH 16 2129#define UVH_NODE_PRESENT_TABLE_DEPTH 16
3896#define UV1H_NODE_PRESENT_TABLE_DEPTH 0x1400UL
3897#define UV2H_NODE_PRESENT_TABLE_DEPTH 0x1400UL
3898#define UV3H_NODE_PRESENT_TABLE_DEPTH 0x1400UL
3899 2130
3900#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 2131#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
3901#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 2132#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
3902 2133
3903#define UV1H_NODE_PRESENT_TABLE_NODES_SHFT 0
3904#define UV1H_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
3905
3906#define UVXH_NODE_PRESENT_TABLE_NODES_SHFT 0
3907#define UVXH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
3908
3909#define UV2H_NODE_PRESENT_TABLE_NODES_SHFT 0
3910#define UV2H_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
3911
3912#define UV3H_NODE_PRESENT_TABLE_NODES_SHFT 0
3913#define UV3H_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
3914
3915union uvh_node_present_table_u { 2134union uvh_node_present_table_u {
3916 unsigned long v; 2135 unsigned long v;
3917 struct uvh_node_present_table_s { 2136 struct uvh_node_present_table_s {
3918 unsigned long nodes:64; /* RW */ 2137 unsigned long nodes:64; /* RW */
3919 } s; 2138 } s;
3920 struct uv1h_node_present_table_s {
3921 unsigned long nodes:64; /* RW */
3922 } s1;
3923 struct uvxh_node_present_table_s {
3924 unsigned long nodes:64; /* RW */
3925 } sx;
3926 struct uv2h_node_present_table_s {
3927 unsigned long nodes:64; /* RW */
3928 } s2;
3929 struct uv3h_node_present_table_s {
3930 unsigned long nodes:64; /* RW */
3931 } s3;
3932}; 2139};
3933 2140
3934/* ========================================================================= */ 2141/* ========================================================================= */
3935/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 2142/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
3936/* ========================================================================= */ 2143/* ========================================================================= */
3937#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 2144#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3938#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3939#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3940#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3941 2145
3942#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 2146#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3943#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 2147#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
@@ -3946,34 +2150,6 @@ union uvh_node_present_table_u {
3946#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 2150#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3947#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 2151#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3948 2152
3949#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3950#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3951#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3952#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3953#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3954#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3955
3956#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3957#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3958#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3959#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3960#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3961#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3962
3963#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3964#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3965#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3966#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3967#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3968#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3969
3970#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
3971#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
3972#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT 63
3973#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK 0x00000000ff000000UL
3974#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
3975#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
3976
3977union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 2153union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
3978 unsigned long v; 2154 unsigned long v;
3979 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 2155 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
@@ -3984,47 +2160,12 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
3984 unsigned long rsvd_53_62:10; 2160 unsigned long rsvd_53_62:10;
3985 unsigned long enable:1; /* RW */ 2161 unsigned long enable:1; /* RW */
3986 } s; 2162 } s;
3987 struct uv1h_rh_gam_alias210_overlay_config_0_mmr_s {
3988 unsigned long rsvd_0_23:24;
3989 unsigned long base:8; /* RW */
3990 unsigned long rsvd_32_47:16;
3991 unsigned long m_alias:5; /* RW */
3992 unsigned long rsvd_53_62:10;
3993 unsigned long enable:1; /* RW */
3994 } s1;
3995 struct uvxh_rh_gam_alias210_overlay_config_0_mmr_s {
3996 unsigned long rsvd_0_23:24;
3997 unsigned long base:8; /* RW */
3998 unsigned long rsvd_32_47:16;
3999 unsigned long m_alias:5; /* RW */
4000 unsigned long rsvd_53_62:10;
4001 unsigned long enable:1; /* RW */
4002 } sx;
4003 struct uv2h_rh_gam_alias210_overlay_config_0_mmr_s {
4004 unsigned long rsvd_0_23:24;
4005 unsigned long base:8; /* RW */
4006 unsigned long rsvd_32_47:16;
4007 unsigned long m_alias:5; /* RW */
4008 unsigned long rsvd_53_62:10;
4009 unsigned long enable:1; /* RW */
4010 } s2;
4011 struct uv3h_rh_gam_alias210_overlay_config_0_mmr_s {
4012 unsigned long rsvd_0_23:24;
4013 unsigned long base:8; /* RW */
4014 unsigned long rsvd_32_47:16;
4015 unsigned long m_alias:5; /* RW */
4016 unsigned long rsvd_53_62:10;
4017 unsigned long enable:1; /* RW */
4018 } s3;
4019}; 2163};
4020 2164
4021/* ========================================================================= */ 2165/* ========================================================================= */
4022/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 2166/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
4023/* ========================================================================= */ 2167/* ========================================================================= */
4024#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 2168#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
4025#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
4026#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
4027#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
4028 2169
4029#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 2170#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
4030#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 2171#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
@@ -4033,34 +2174,6 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
4033#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 2174#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
4034#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 2175#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
4035 2176
4036#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
4037#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
4038#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
4039#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
4040#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
4041#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
4042
4043#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
4044#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
4045#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
4046#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
4047#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
4048#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
4049
4050#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
4051#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
4052#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
4053#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
4054#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
4055#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
4056
4057#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
4058#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
4059#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT 63
4060#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK 0x00000000ff000000UL
4061#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
4062#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
4063
4064union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 2177union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
4065 unsigned long v; 2178 unsigned long v;
4066 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 2179 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
@@ -4071,47 +2184,12 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
4071 unsigned long rsvd_53_62:10; 2184 unsigned long rsvd_53_62:10;
4072 unsigned long enable:1; /* RW */ 2185 unsigned long enable:1; /* RW */
4073 } s; 2186 } s;
4074 struct uv1h_rh_gam_alias210_overlay_config_1_mmr_s {
4075 unsigned long rsvd_0_23:24;
4076 unsigned long base:8; /* RW */
4077 unsigned long rsvd_32_47:16;
4078 unsigned long m_alias:5; /* RW */
4079 unsigned long rsvd_53_62:10;
4080 unsigned long enable:1; /* RW */
4081 } s1;
4082 struct uvxh_rh_gam_alias210_overlay_config_1_mmr_s {
4083 unsigned long rsvd_0_23:24;
4084 unsigned long base:8; /* RW */
4085 unsigned long rsvd_32_47:16;
4086 unsigned long m_alias:5; /* RW */
4087 unsigned long rsvd_53_62:10;
4088 unsigned long enable:1; /* RW */
4089 } sx;
4090 struct uv2h_rh_gam_alias210_overlay_config_1_mmr_s {
4091 unsigned long rsvd_0_23:24;
4092 unsigned long base:8; /* RW */
4093 unsigned long rsvd_32_47:16;
4094 unsigned long m_alias:5; /* RW */
4095 unsigned long rsvd_53_62:10;
4096 unsigned long enable:1; /* RW */
4097 } s2;
4098 struct uv3h_rh_gam_alias210_overlay_config_1_mmr_s {
4099 unsigned long rsvd_0_23:24;
4100 unsigned long base:8; /* RW */
4101 unsigned long rsvd_32_47:16;
4102 unsigned long m_alias:5; /* RW */
4103 unsigned long rsvd_53_62:10;
4104 unsigned long enable:1; /* RW */
4105 } s3;
4106}; 2187};
4107 2188
4108/* ========================================================================= */ 2189/* ========================================================================= */
4109/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 2190/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
4110/* ========================================================================= */ 2191/* ========================================================================= */
4111#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 2192#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
4112#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
4113#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
4114#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
4115 2193
4116#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 2194#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
4117#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 2195#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
@@ -4120,34 +2198,6 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
4120#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 2198#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
4121#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 2199#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
4122 2200
4123#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
4124#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
4125#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
4126#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
4127#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
4128#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
4129
4130#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
4131#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
4132#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
4133#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
4134#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
4135#define UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
4136
4137#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
4138#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
4139#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
4140#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
4141#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
4142#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
4143
4144#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
4145#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
4146#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT 63
4147#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK 0x00000000ff000000UL
4148#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
4149#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
4150
4151union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 2201union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
4152 unsigned long v; 2202 unsigned long v;
4153 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 2203 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
@@ -4158,63 +2208,16 @@ union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
4158 unsigned long rsvd_53_62:10; 2208 unsigned long rsvd_53_62:10;
4159 unsigned long enable:1; /* RW */ 2209 unsigned long enable:1; /* RW */
4160 } s; 2210 } s;
4161 struct uv1h_rh_gam_alias210_overlay_config_2_mmr_s {
4162 unsigned long rsvd_0_23:24;
4163 unsigned long base:8; /* RW */
4164 unsigned long rsvd_32_47:16;
4165 unsigned long m_alias:5; /* RW */
4166 unsigned long rsvd_53_62:10;
4167 unsigned long enable:1; /* RW */
4168 } s1;
4169 struct uvxh_rh_gam_alias210_overlay_config_2_mmr_s {
4170 unsigned long rsvd_0_23:24;
4171 unsigned long base:8; /* RW */
4172 unsigned long rsvd_32_47:16;
4173 unsigned long m_alias:5; /* RW */
4174 unsigned long rsvd_53_62:10;
4175 unsigned long enable:1; /* RW */
4176 } sx;
4177 struct uv2h_rh_gam_alias210_overlay_config_2_mmr_s {
4178 unsigned long rsvd_0_23:24;
4179 unsigned long base:8; /* RW */
4180 unsigned long rsvd_32_47:16;
4181 unsigned long m_alias:5; /* RW */
4182 unsigned long rsvd_53_62:10;
4183 unsigned long enable:1; /* RW */
4184 } s2;
4185 struct uv3h_rh_gam_alias210_overlay_config_2_mmr_s {
4186 unsigned long rsvd_0_23:24;
4187 unsigned long base:8; /* RW */
4188 unsigned long rsvd_32_47:16;
4189 unsigned long m_alias:5; /* RW */
4190 unsigned long rsvd_53_62:10;
4191 unsigned long enable:1; /* RW */
4192 } s3;
4193}; 2211};
4194 2212
4195/* ========================================================================= */ 2213/* ========================================================================= */
4196/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 2214/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
4197/* ========================================================================= */ 2215/* ========================================================================= */
4198#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 2216#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
4199#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
4200#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
4201#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
4202 2217
4203#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 2218#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
4204#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2219#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4205 2220
4206#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
4207#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4208
4209#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
4210#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4211
4212#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
4213#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4214
4215#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
4216#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4217
4218union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 2221union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
4219 unsigned long v; 2222 unsigned long v;
4220 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 2223 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
@@ -4222,51 +2225,16 @@ union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
4222 unsigned long dest_base:22; /* RW */ 2225 unsigned long dest_base:22; /* RW */
4223 unsigned long rsvd_46_63:18; 2226 unsigned long rsvd_46_63:18;
4224 } s; 2227 } s;
4225 struct uv1h_rh_gam_alias210_redirect_config_0_mmr_s {
4226 unsigned long rsvd_0_23:24;
4227 unsigned long dest_base:22; /* RW */
4228 unsigned long rsvd_46_63:18;
4229 } s1;
4230 struct uvxh_rh_gam_alias210_redirect_config_0_mmr_s {
4231 unsigned long rsvd_0_23:24;
4232 unsigned long dest_base:22; /* RW */
4233 unsigned long rsvd_46_63:18;
4234 } sx;
4235 struct uv2h_rh_gam_alias210_redirect_config_0_mmr_s {
4236 unsigned long rsvd_0_23:24;
4237 unsigned long dest_base:22; /* RW */
4238 unsigned long rsvd_46_63:18;
4239 } s2;
4240 struct uv3h_rh_gam_alias210_redirect_config_0_mmr_s {
4241 unsigned long rsvd_0_23:24;
4242 unsigned long dest_base:22; /* RW */
4243 unsigned long rsvd_46_63:18;
4244 } s3;
4245}; 2228};
4246 2229
4247/* ========================================================================= */ 2230/* ========================================================================= */
4248/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 2231/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
4249/* ========================================================================= */ 2232/* ========================================================================= */
4250#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 2233#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
4251#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
4252#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
4253#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
4254 2234
4255#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 2235#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
4256#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2236#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4257 2237
4258#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
4259#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4260
4261#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
4262#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4263
4264#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
4265#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4266
4267#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
4268#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4269
4270union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 2238union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
4271 unsigned long v; 2239 unsigned long v;
4272 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 2240 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
@@ -4274,51 +2242,16 @@ union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
4274 unsigned long dest_base:22; /* RW */ 2242 unsigned long dest_base:22; /* RW */
4275 unsigned long rsvd_46_63:18; 2243 unsigned long rsvd_46_63:18;
4276 } s; 2244 } s;
4277 struct uv1h_rh_gam_alias210_redirect_config_1_mmr_s {
4278 unsigned long rsvd_0_23:24;
4279 unsigned long dest_base:22; /* RW */
4280 unsigned long rsvd_46_63:18;
4281 } s1;
4282 struct uvxh_rh_gam_alias210_redirect_config_1_mmr_s {
4283 unsigned long rsvd_0_23:24;
4284 unsigned long dest_base:22; /* RW */
4285 unsigned long rsvd_46_63:18;
4286 } sx;
4287 struct uv2h_rh_gam_alias210_redirect_config_1_mmr_s {
4288 unsigned long rsvd_0_23:24;
4289 unsigned long dest_base:22; /* RW */
4290 unsigned long rsvd_46_63:18;
4291 } s2;
4292 struct uv3h_rh_gam_alias210_redirect_config_1_mmr_s {
4293 unsigned long rsvd_0_23:24;
4294 unsigned long dest_base:22; /* RW */
4295 unsigned long rsvd_46_63:18;
4296 } s3;
4297}; 2245};
4298 2246
4299/* ========================================================================= */ 2247/* ========================================================================= */
4300/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 2248/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
4301/* ========================================================================= */ 2249/* ========================================================================= */
4302#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 2250#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
4303#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
4304#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
4305#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
4306 2251
4307#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 2252#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
4308#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 2253#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4309 2254
4310#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
4311#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4312
4313#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
4314#define UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4315
4316#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
4317#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4318
4319#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
4320#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
4321
4322union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 2255union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
4323 unsigned long v; 2256 unsigned long v;
4324 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 2257 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
@@ -4326,26 +2259,6 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
4326 unsigned long dest_base:22; /* RW */ 2259 unsigned long dest_base:22; /* RW */
4327 unsigned long rsvd_46_63:18; 2260 unsigned long rsvd_46_63:18;
4328 } s; 2261 } s;
4329 struct uv1h_rh_gam_alias210_redirect_config_2_mmr_s {
4330 unsigned long rsvd_0_23:24;
4331 unsigned long dest_base:22; /* RW */
4332 unsigned long rsvd_46_63:18;
4333 } s1;
4334 struct uvxh_rh_gam_alias210_redirect_config_2_mmr_s {
4335 unsigned long rsvd_0_23:24;
4336 unsigned long dest_base:22; /* RW */
4337 unsigned long rsvd_46_63:18;
4338 } sx;
4339 struct uv2h_rh_gam_alias210_redirect_config_2_mmr_s {
4340 unsigned long rsvd_0_23:24;
4341 unsigned long dest_base:22; /* RW */
4342 unsigned long rsvd_46_63:18;
4343 } s2;
4344 struct uv3h_rh_gam_alias210_redirect_config_2_mmr_s {
4345 unsigned long rsvd_0_23:24;
4346 unsigned long dest_base:22; /* RW */
4347 unsigned long rsvd_46_63:18;
4348 } s3;
4349}; 2262};
4350 2263
4351/* ========================================================================= */ 2264/* ========================================================================= */
@@ -4513,9 +2426,6 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
4513/* ========================================================================= */ 2426/* ========================================================================= */
4514#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 2427#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
4515#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 2428#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
4516#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR \
4517 (is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \
4518 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR)
4519 2429
4520#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 2430#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
4521#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 2431#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
@@ -4629,56 +2539,22 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u {
4629/* UVH_RTC */ 2539/* UVH_RTC */
4630/* ========================================================================= */ 2540/* ========================================================================= */
4631#define UVH_RTC 0x340000UL 2541#define UVH_RTC 0x340000UL
4632#define UV1H_RTC 0x340000UL
4633#define UV2H_RTC 0x340000UL
4634#define UV3H_RTC 0x340000UL
4635 2542
4636#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 2543#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
4637#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 2544#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
4638 2545
4639#define UV1H_RTC_REAL_TIME_CLOCK_SHFT 0
4640#define UV1H_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
4641
4642#define UVXH_RTC_REAL_TIME_CLOCK_SHFT 0
4643#define UVXH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
4644
4645#define UV2H_RTC_REAL_TIME_CLOCK_SHFT 0
4646#define UV2H_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
4647
4648#define UV3H_RTC_REAL_TIME_CLOCK_SHFT 0
4649#define UV3H_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
4650
4651union uvh_rtc_u { 2546union uvh_rtc_u {
4652 unsigned long v; 2547 unsigned long v;
4653 struct uvh_rtc_s { 2548 struct uvh_rtc_s {
4654 unsigned long real_time_clock:56; /* RW */ 2549 unsigned long real_time_clock:56; /* RW */
4655 unsigned long rsvd_56_63:8; 2550 unsigned long rsvd_56_63:8;
4656 } s; 2551 } s;
4657 struct uv1h_rtc_s {
4658 unsigned long real_time_clock:56; /* RW */
4659 unsigned long rsvd_56_63:8;
4660 } s1;
4661 struct uvxh_rtc_s {
4662 unsigned long real_time_clock:56; /* RW */
4663 unsigned long rsvd_56_63:8;
4664 } sx;
4665 struct uv2h_rtc_s {
4666 unsigned long real_time_clock:56; /* RW */
4667 unsigned long rsvd_56_63:8;
4668 } s2;
4669 struct uv3h_rtc_s {
4670 unsigned long real_time_clock:56; /* RW */
4671 unsigned long rsvd_56_63:8;
4672 } s3;
4673}; 2552};
4674 2553
4675/* ========================================================================= */ 2554/* ========================================================================= */
4676/* UVH_RTC1_INT_CONFIG */ 2555/* UVH_RTC1_INT_CONFIG */
4677/* ========================================================================= */ 2556/* ========================================================================= */
4678#define UVH_RTC1_INT_CONFIG 0x615c0UL 2557#define UVH_RTC1_INT_CONFIG 0x615c0UL
4679#define UV1H_RTC1_INT_CONFIG 0x615c0UL
4680#define UV2H_RTC1_INT_CONFIG 0x615c0UL
4681#define UV3H_RTC1_INT_CONFIG 0x615c0UL
4682 2558
4683#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 2559#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
4684#define UVH_RTC1_INT_CONFIG_DM_SHFT 8 2560#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
@@ -4697,74 +2573,6 @@ union uvh_rtc_u {
4697#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 2573#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
4698#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 2574#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
4699 2575
4700#define UV1H_RTC1_INT_CONFIG_VECTOR_SHFT 0
4701#define UV1H_RTC1_INT_CONFIG_DM_SHFT 8
4702#define UV1H_RTC1_INT_CONFIG_DESTMODE_SHFT 11
4703#define UV1H_RTC1_INT_CONFIG_STATUS_SHFT 12
4704#define UV1H_RTC1_INT_CONFIG_P_SHFT 13
4705#define UV1H_RTC1_INT_CONFIG_T_SHFT 15
4706#define UV1H_RTC1_INT_CONFIG_M_SHFT 16
4707#define UV1H_RTC1_INT_CONFIG_APIC_ID_SHFT 32
4708#define UV1H_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
4709#define UV1H_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
4710#define UV1H_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
4711#define UV1H_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
4712#define UV1H_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
4713#define UV1H_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
4714#define UV1H_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
4715#define UV1H_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
4716
4717#define UVXH_RTC1_INT_CONFIG_VECTOR_SHFT 0
4718#define UVXH_RTC1_INT_CONFIG_DM_SHFT 8
4719#define UVXH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
4720#define UVXH_RTC1_INT_CONFIG_STATUS_SHFT 12
4721#define UVXH_RTC1_INT_CONFIG_P_SHFT 13
4722#define UVXH_RTC1_INT_CONFIG_T_SHFT 15
4723#define UVXH_RTC1_INT_CONFIG_M_SHFT 16
4724#define UVXH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
4725#define UVXH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
4726#define UVXH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
4727#define UVXH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
4728#define UVXH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
4729#define UVXH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
4730#define UVXH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
4731#define UVXH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
4732#define UVXH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
4733
4734#define UV2H_RTC1_INT_CONFIG_VECTOR_SHFT 0
4735#define UV2H_RTC1_INT_CONFIG_DM_SHFT 8
4736#define UV2H_RTC1_INT_CONFIG_DESTMODE_SHFT 11
4737#define UV2H_RTC1_INT_CONFIG_STATUS_SHFT 12
4738#define UV2H_RTC1_INT_CONFIG_P_SHFT 13
4739#define UV2H_RTC1_INT_CONFIG_T_SHFT 15
4740#define UV2H_RTC1_INT_CONFIG_M_SHFT 16
4741#define UV2H_RTC1_INT_CONFIG_APIC_ID_SHFT 32
4742#define UV2H_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
4743#define UV2H_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
4744#define UV2H_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
4745#define UV2H_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
4746#define UV2H_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
4747#define UV2H_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
4748#define UV2H_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
4749#define UV2H_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
4750
4751#define UV3H_RTC1_INT_CONFIG_VECTOR_SHFT 0
4752#define UV3H_RTC1_INT_CONFIG_DM_SHFT 8
4753#define UV3H_RTC1_INT_CONFIG_DESTMODE_SHFT 11
4754#define UV3H_RTC1_INT_CONFIG_STATUS_SHFT 12
4755#define UV3H_RTC1_INT_CONFIG_P_SHFT 13
4756#define UV3H_RTC1_INT_CONFIG_T_SHFT 15
4757#define UV3H_RTC1_INT_CONFIG_M_SHFT 16
4758#define UV3H_RTC1_INT_CONFIG_APIC_ID_SHFT 32
4759#define UV3H_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
4760#define UV3H_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
4761#define UV3H_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
4762#define UV3H_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
4763#define UV3H_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
4764#define UV3H_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
4765#define UV3H_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
4766#define UV3H_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
4767
4768union uvh_rtc1_int_config_u { 2576union uvh_rtc1_int_config_u {
4769 unsigned long v; 2577 unsigned long v;
4770 struct uvh_rtc1_int_config_s { 2578 struct uvh_rtc1_int_config_s {
@@ -4779,111 +2587,29 @@ union uvh_rtc1_int_config_u {
4779 unsigned long rsvd_17_31:15; 2587 unsigned long rsvd_17_31:15;
4780 unsigned long apic_id:32; /* RW */ 2588 unsigned long apic_id:32; /* RW */
4781 } s; 2589 } s;
4782 struct uv1h_rtc1_int_config_s {
4783 unsigned long vector_:8; /* RW */
4784 unsigned long dm:3; /* RW */
4785 unsigned long destmode:1; /* RW */
4786 unsigned long status:1; /* RO */
4787 unsigned long p:1; /* RO */
4788 unsigned long rsvd_14:1;
4789 unsigned long t:1; /* RO */
4790 unsigned long m:1; /* RW */
4791 unsigned long rsvd_17_31:15;
4792 unsigned long apic_id:32; /* RW */
4793 } s1;
4794 struct uvxh_rtc1_int_config_s {
4795 unsigned long vector_:8; /* RW */
4796 unsigned long dm:3; /* RW */
4797 unsigned long destmode:1; /* RW */
4798 unsigned long status:1; /* RO */
4799 unsigned long p:1; /* RO */
4800 unsigned long rsvd_14:1;
4801 unsigned long t:1; /* RO */
4802 unsigned long m:1; /* RW */
4803 unsigned long rsvd_17_31:15;
4804 unsigned long apic_id:32; /* RW */
4805 } sx;
4806 struct uv2h_rtc1_int_config_s {
4807 unsigned long vector_:8; /* RW */
4808 unsigned long dm:3; /* RW */
4809 unsigned long destmode:1; /* RW */
4810 unsigned long status:1; /* RO */
4811 unsigned long p:1; /* RO */
4812 unsigned long rsvd_14:1;
4813 unsigned long t:1; /* RO */
4814 unsigned long m:1; /* RW */
4815 unsigned long rsvd_17_31:15;
4816 unsigned long apic_id:32; /* RW */
4817 } s2;
4818 struct uv3h_rtc1_int_config_s {
4819 unsigned long vector_:8; /* RW */
4820 unsigned long dm:3; /* RW */
4821 unsigned long destmode:1; /* RW */
4822 unsigned long status:1; /* RO */
4823 unsigned long p:1; /* RO */
4824 unsigned long rsvd_14:1;
4825 unsigned long t:1; /* RO */
4826 unsigned long m:1; /* RW */
4827 unsigned long rsvd_17_31:15;
4828 unsigned long apic_id:32; /* RW */
4829 } s3;
4830}; 2590};
4831 2591
4832/* ========================================================================= */ 2592/* ========================================================================= */
4833/* UVH_SCRATCH5 */ 2593/* UVH_SCRATCH5 */
4834/* ========================================================================= */ 2594/* ========================================================================= */
4835#define UVH_SCRATCH5 0x2d0200UL 2595#define UVH_SCRATCH5 0x2d0200UL
4836#define UV1H_SCRATCH5 0x2d0200UL
4837#define UV2H_SCRATCH5 0x2d0200UL
4838#define UV3H_SCRATCH5 0x2d0200UL
4839#define UVH_SCRATCH5_32 0x778 2596#define UVH_SCRATCH5_32 0x778
4840#define UV1H_SCRATCH5_32 0x2d0200UL
4841#define UV2H_SCRATCH5_32 0x2d0200UL
4842#define UV3H_SCRATCH5_32 0x2d0200UL
4843 2597
4844#define UVH_SCRATCH5_SCRATCH5_SHFT 0 2598#define UVH_SCRATCH5_SCRATCH5_SHFT 0
4845#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 2599#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4846 2600
4847#define UV1H_SCRATCH5_SCRATCH5_SHFT 0
4848#define UV1H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4849
4850#define UVXH_SCRATCH5_SCRATCH5_SHFT 0
4851#define UVXH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4852
4853#define UV2H_SCRATCH5_SCRATCH5_SHFT 0
4854#define UV2H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4855
4856#define UV3H_SCRATCH5_SCRATCH5_SHFT 0
4857#define UV3H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
4858
4859union uvh_scratch5_u { 2601union uvh_scratch5_u {
4860 unsigned long v; 2602 unsigned long v;
4861 struct uvh_scratch5_s { 2603 struct uvh_scratch5_s {
4862 unsigned long scratch5:64; /* RW, W1CS */ 2604 unsigned long scratch5:64; /* RW, W1CS */
4863 } s; 2605 } s;
4864 struct uv1h_scratch5_s {
4865 unsigned long scratch5:64; /* RW, W1CS */
4866 } s1;
4867 struct uvxh_scratch5_s {
4868 unsigned long scratch5:64; /* RW */
4869 } sx;
4870 struct uv2h_scratch5_s {
4871 unsigned long scratch5:64; /* RW */
4872 } s2;
4873 struct uv3h_scratch5_s {
4874 unsigned long scratch5:64; /* RW */
4875 } s3;
4876}; 2606};
4877 2607
4878/* ========================================================================= */ 2608/* ========================================================================= */
4879/* UVXH_EVENT_OCCURRED2 */ 2609/* UVXH_EVENT_OCCURRED2 */
4880/* ========================================================================= */ 2610/* ========================================================================= */
4881#define UVXH_EVENT_OCCURRED2 0x70100UL 2611#define UVXH_EVENT_OCCURRED2 0x70100UL
4882#define UV2H_EVENT_OCCURRED2 0x70100UL
4883#define UV3H_EVENT_OCCURRED2 0x70100UL
4884#define UVXH_EVENT_OCCURRED2_32 0xb68 2612#define UVXH_EVENT_OCCURRED2_32 0xb68
4885#define UV2H_EVENT_OCCURRED2_32 0x70100UL
4886#define UV3H_EVENT_OCCURRED2_32 0x70100UL
4887 2613
4888#define UVXH_EVENT_OCCURRED2_RTC_0_SHFT 0 2614#define UVXH_EVENT_OCCURRED2_RTC_0_SHFT 0
4889#define UVXH_EVENT_OCCURRED2_RTC_1_SHFT 1 2615#define UVXH_EVENT_OCCURRED2_RTC_1_SHFT 1
@@ -4950,136 +2676,6 @@ union uvh_scratch5_u {
4950#define UVXH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 2676#define UVXH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
4951#define UVXH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 2677#define UVXH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
4952 2678
4953#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
4954#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
4955#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
4956#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
4957#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
4958#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
4959#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
4960#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
4961#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
4962#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
4963#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
4964#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
4965#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
4966#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
4967#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
4968#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
4969#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
4970#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
4971#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
4972#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
4973#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
4974#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
4975#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
4976#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
4977#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
4978#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
4979#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
4980#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
4981#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
4982#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
4983#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
4984#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
4985#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
4986#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
4987#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
4988#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
4989#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
4990#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
4991#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
4992#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
4993#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
4994#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
4995#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
4996#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
4997#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
4998#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
4999#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
5000#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
5001#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
5002#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
5003#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
5004#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
5005#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
5006#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
5007#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
5008#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
5009#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
5010#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
5011#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
5012#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
5013#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
5014#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
5015#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
5016#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
5017
5018#define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0
5019#define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1
5020#define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2
5021#define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3
5022#define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4
5023#define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5
5024#define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6
5025#define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7
5026#define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8
5027#define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9
5028#define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10
5029#define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11
5030#define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12
5031#define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13
5032#define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14
5033#define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15
5034#define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16
5035#define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17
5036#define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18
5037#define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19
5038#define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20
5039#define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21
5040#define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22
5041#define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23
5042#define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24
5043#define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25
5044#define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26
5045#define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27
5046#define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28
5047#define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29
5048#define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30
5049#define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31
5050#define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
5051#define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
5052#define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
5053#define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
5054#define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
5055#define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
5056#define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
5057#define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
5058#define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
5059#define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
5060#define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
5061#define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
5062#define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
5063#define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
5064#define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
5065#define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
5066#define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
5067#define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
5068#define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
5069#define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
5070#define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
5071#define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
5072#define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
5073#define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
5074#define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
5075#define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
5076#define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
5077#define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
5078#define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
5079#define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
5080#define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
5081#define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
5082
5083union uvxh_event_occurred2_u { 2679union uvxh_event_occurred2_u {
5084 unsigned long v; 2680 unsigned long v;
5085 struct uvxh_event_occurred2_s { 2681 struct uvxh_event_occurred2_s {
@@ -5117,87 +2713,13 @@ union uvxh_event_occurred2_u {
5117 unsigned long rtc_31:1; /* RW */ 2713 unsigned long rtc_31:1; /* RW */
5118 unsigned long rsvd_32_63:32; 2714 unsigned long rsvd_32_63:32;
5119 } sx; 2715 } sx;
5120 struct uv2h_event_occurred2_s {
5121 unsigned long rtc_0:1; /* RW */
5122 unsigned long rtc_1:1; /* RW */
5123 unsigned long rtc_2:1; /* RW */
5124 unsigned long rtc_3:1; /* RW */
5125 unsigned long rtc_4:1; /* RW */
5126 unsigned long rtc_5:1; /* RW */
5127 unsigned long rtc_6:1; /* RW */
5128 unsigned long rtc_7:1; /* RW */
5129 unsigned long rtc_8:1; /* RW */
5130 unsigned long rtc_9:1; /* RW */
5131 unsigned long rtc_10:1; /* RW */
5132 unsigned long rtc_11:1; /* RW */
5133 unsigned long rtc_12:1; /* RW */
5134 unsigned long rtc_13:1; /* RW */
5135 unsigned long rtc_14:1; /* RW */
5136 unsigned long rtc_15:1; /* RW */
5137 unsigned long rtc_16:1; /* RW */
5138 unsigned long rtc_17:1; /* RW */
5139 unsigned long rtc_18:1; /* RW */
5140 unsigned long rtc_19:1; /* RW */
5141 unsigned long rtc_20:1; /* RW */
5142 unsigned long rtc_21:1; /* RW */
5143 unsigned long rtc_22:1; /* RW */
5144 unsigned long rtc_23:1; /* RW */
5145 unsigned long rtc_24:1; /* RW */
5146 unsigned long rtc_25:1; /* RW */
5147 unsigned long rtc_26:1; /* RW */
5148 unsigned long rtc_27:1; /* RW */
5149 unsigned long rtc_28:1; /* RW */
5150 unsigned long rtc_29:1; /* RW */
5151 unsigned long rtc_30:1; /* RW */
5152 unsigned long rtc_31:1; /* RW */
5153 unsigned long rsvd_32_63:32;
5154 } s2;
5155 struct uv3h_event_occurred2_s {
5156 unsigned long rtc_0:1; /* RW */
5157 unsigned long rtc_1:1; /* RW */
5158 unsigned long rtc_2:1; /* RW */
5159 unsigned long rtc_3:1; /* RW */
5160 unsigned long rtc_4:1; /* RW */
5161 unsigned long rtc_5:1; /* RW */
5162 unsigned long rtc_6:1; /* RW */
5163 unsigned long rtc_7:1; /* RW */
5164 unsigned long rtc_8:1; /* RW */
5165 unsigned long rtc_9:1; /* RW */
5166 unsigned long rtc_10:1; /* RW */
5167 unsigned long rtc_11:1; /* RW */
5168 unsigned long rtc_12:1; /* RW */
5169 unsigned long rtc_13:1; /* RW */
5170 unsigned long rtc_14:1; /* RW */
5171 unsigned long rtc_15:1; /* RW */
5172 unsigned long rtc_16:1; /* RW */
5173 unsigned long rtc_17:1; /* RW */
5174 unsigned long rtc_18:1; /* RW */
5175 unsigned long rtc_19:1; /* RW */
5176 unsigned long rtc_20:1; /* RW */
5177 unsigned long rtc_21:1; /* RW */
5178 unsigned long rtc_22:1; /* RW */
5179 unsigned long rtc_23:1; /* RW */
5180 unsigned long rtc_24:1; /* RW */
5181 unsigned long rtc_25:1; /* RW */
5182 unsigned long rtc_26:1; /* RW */
5183 unsigned long rtc_27:1; /* RW */
5184 unsigned long rtc_28:1; /* RW */
5185 unsigned long rtc_29:1; /* RW */
5186 unsigned long rtc_30:1; /* RW */
5187 unsigned long rtc_31:1; /* RW */
5188 unsigned long rsvd_32_63:32;
5189 } s3;
5190}; 2716};
5191 2717
5192/* ========================================================================= */ 2718/* ========================================================================= */
5193/* UVXH_EVENT_OCCURRED2_ALIAS */ 2719/* UVXH_EVENT_OCCURRED2_ALIAS */
5194/* ========================================================================= */ 2720/* ========================================================================= */
5195#define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 2721#define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
5196#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
5197#define UV3H_EVENT_OCCURRED2_ALIAS 0x70108UL
5198#define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70 2722#define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70
5199#define UV2H_EVENT_OCCURRED2_ALIAS_32 0x70108UL
5200#define UV3H_EVENT_OCCURRED2_ALIAS_32 0x70108UL
5201 2723
5202 2724
5203/* ========================================================================= */ 2725/* ========================================================================= */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-30 23:27:00 -0400