3 files changed, 63 insertions, 21 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index c337cf3a71bf..07277735252e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -35,11 +35,21 @@
 #define PHY1_COMMON_ON_N                (1 << 7)
 #define PHY0_COMMON_ON_N                (1 << 4)
 #define PHY0_ID_PULLUP                  (1 << 2)
-#define CLKSEL_MASK                     (0x3 << 0)
-#define CLKSEL_SHIFT                    (0)
+#define EXYNOS4_CLKSEL_SHIFT            (0)
-#define CLKSEL_48M                      (0x0 << 0)
-#define CLKSEL_12M                      (0x2 << 0)
+#define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
-#define CLKSEL_24M                      (0x3 << 0)
+#define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
+#define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
+#define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
+#define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
+#define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
+#define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
+#define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
+#define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
+#define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
+#define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
 #define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
 #define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1af0a7f44e00..b81cc569a8dd 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
        struct clk *xusbxti_clk;
        u32 phyclk;
-        /* set clock frequency for PLL */
-        phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                switch (clk_get_rate(xusbxti_clk)) {
+                if (soc_is_exynos4210()) {
-                case 12 * MHZ:
+                        /* set clock frequency for PLL */
-                        phyclk |= CLKSEL_12M;
+                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
-                        break;
-                case 24 * MHZ:
+                        switch (clk_get_rate(xusbxti_clk)) {
-                        phyclk |= CLKSEL_24M;
+                        case 12 * MHZ:
-                        break;
+                                phyclk |= EXYNOS4210_CLKSEL_12M;
-                default:
+                                break;
-                case 48 * MHZ:
+                        case 48 * MHZ:
-                        /* default reference clock */
+                                phyclk |= EXYNOS4210_CLKSEL_48M;
-                        break;
+                                break;
+                        default:
+                        case 24 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_24M;
+                                break;
+                        }
+                        writel(phyclk, EXYNOS4_PHYCLK);
+                } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                        /* set clock frequency for PLL */
+                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
+                        switch (clk_get_rate(xusbxti_clk)) {
+                        case 9600 * KHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_9600K;
+                                break;
+                        case 10 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_10M;
+                                break;
+                        case 12 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_12M;
+                                break;
+                        case 19200 * KHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_19200K;
+                                break;
+                        case 20 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_20M;
+                                break;
+                        default:
+                        case 24 * MHZ:
+                                /* default reference clock */
+                                phyclk |= EXYNOS4X12_CLKSEL_24M;
+                                break;
+                        }
+                        writel(phyclk, EXYNOS4_PHYCLK);
                }
                clk_put(xusbxti_clk);
        }
-        writel(phyclk, EXYNOS4_PHYCLK);
 }
 static int exynos4210_usb_phy0_init(struct platform_device *pdev)
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 0721293fad63..ace4451b7651 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
+#ifndef KHZ
+#define KHZ (1000)
+#endif
 #ifndef MHZ
 #define MHZ (1000*1000)
 #endif

diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3a71bf..07277735252e 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -35,11 +35,21 @@
35	#define PHY1_COMMON_ON_N (1 << 7)	35	#define PHY1_COMMON_ON_N (1 << 7)
36	#define PHY0_COMMON_ON_N (1 << 4)	36	#define PHY0_COMMON_ON_N (1 << 4)
37	#define PHY0_ID_PULLUP (1 << 2)	37	#define PHY0_ID_PULLUP (1 << 2)
38	#define CLKSEL_MASK (0x3 << 0)	38
39	#define CLKSEL_SHIFT (0)	39	#define EXYNOS4_CLKSEL_SHIFT (0)
40	#define CLKSEL_48M (0x0 << 0)	40
41	#define CLKSEL_12M (0x2 << 0)	41	#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
42	#define CLKSEL_24M (0x3 << 0)	42	#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
		43	#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
		44	#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
		45
		46	#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
		47	#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
		48	#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
		49	#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
		50	#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
		51	#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
		52	#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
43		53
44	#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)	54	#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
45	#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)	55	#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)


diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f44e00..b81cc569a8dd 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
31	struct clk *xusbxti_clk;	31	struct clk *xusbxti_clk;
32	u32 phyclk;	32	u32 phyclk;
33		33
34	/* set clock frequency for PLL */
35	phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
36
37	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");	34	xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
38	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {	35	if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
39	switch (clk_get_rate(xusbxti_clk)) {	36	if (soc_is_exynos4210()) {
40	case 12 * MHZ:	37	/* set clock frequency for PLL */
41	phyclk \|= CLKSEL_12M;	38	phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
42	break;	39
43	case 24 * MHZ:	40	switch (clk_get_rate(xusbxti_clk)) {
44	phyclk \|= CLKSEL_24M;	41	case 12 * MHZ:
45	break;	42	phyclk \|= EXYNOS4210_CLKSEL_12M;
46	default:	43	break;
47	case 48 * MHZ:	44	case 48 * MHZ:
48	/* default reference clock */	45	phyclk \|= EXYNOS4210_CLKSEL_48M;
49	break;	46	break;
		47	default:
		48	case 24 * MHZ:
		49	phyclk \|= EXYNOS4210_CLKSEL_24M;
		50	break;
		51	}
		52	writel(phyclk, EXYNOS4_PHYCLK);
		53	} else if (soc_is_exynos4212() \|\| soc_is_exynos4412()) {
		54	/* set clock frequency for PLL */
		55	phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
		56
		57	switch (clk_get_rate(xusbxti_clk)) {
		58	case 9600 * KHZ:
		59	phyclk \|= EXYNOS4X12_CLKSEL_9600K;
		60	break;
		61	case 10 * MHZ:
		62	phyclk \|= EXYNOS4X12_CLKSEL_10M;
		63	break;
		64	case 12 * MHZ:
		65	phyclk \|= EXYNOS4X12_CLKSEL_12M;
		66	break;
		67	case 19200 * KHZ:
		68	phyclk \|= EXYNOS4X12_CLKSEL_19200K;
		69	break;
		70	case 20 * MHZ:
		71	phyclk \|= EXYNOS4X12_CLKSEL_20M;
		72	break;
		73	default:
		74	case 24 * MHZ:
		75	/* default reference clock */
		76	phyclk \|= EXYNOS4X12_CLKSEL_24M;
		77	break;
		78	}
		79	writel(phyclk, EXYNOS4_PHYCLK);
50	}	80	}
51	clk_put(xusbxti_clk);	81	clk_put(xusbxti_clk);
52	}	82	}
53
54	writel(phyclk, EXYNOS4_PHYCLK);
55	}	83	}
56		84
57	static int exynos4210_usb_phy0_init(struct platform_device *pdev)	85	static int exynos4210_usb_phy0_init(struct platform_device *pdev)


diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 0721293fad63..ace4451b7651 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
132		132
133	#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }	133	#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
134		134
		135	#ifndef KHZ
		136	#define KHZ (1000)
		137	#endif
		138
135	#ifndef MHZ	139	#ifndef MHZ
136	#define MHZ (1000*1000)	140	#define MHZ (1000*1000)
137	#endif	141	#endif