1 files changed, 41 insertions, 3 deletions

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 4dc0028086a3..4557aa1567a5 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -34,6 +34,14 @@
 #define  SDHCI_VENDOR_SPEC_SDIO_QUIRK   0x00000002
 
 /*
+ * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
+ * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
+ * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
+ * Define this macro DMA error INT for fsl eSDHC
+ */
+#define SDHCI_INT_VENDOR_SPEC_DMA_ERR   0x10000000
+
+/*
  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  * "11" when the STOP CMD12 is issued on imx53 to abort one
  * open ended multi-blk IO. Otherwise the TC INT wouldn't
@@ -135,6 +143,27 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
                         val |= SDHCI_CARD_PRESENT;
         }
 
+        if (unlikely(reg == SDHCI_CAPABILITIES)) {
+                /* In FSL esdhc IC module, only bit20 is used to indicate the
+                 * ADMA2 capability of esdhc, but this bit is messed up on
+                 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
+                 * don't actually support ADMA2). So set the BROKEN_ADMA
+                 * uirk on MX25/35 platforms.
+                 */
+
+                if (val & SDHCI_CAN_DO_ADMA1) {
+                        val &= ~SDHCI_CAN_DO_ADMA1;
+                        val |= SDHCI_CAN_DO_ADMA2;
+                }
+        }
+
+        if (unlikely(reg == SDHCI_INT_STATUS)) {
+                if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
+                        val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
+                        val |= SDHCI_INT_ADMA_ERROR;
+                }
+        }
+
         return val;
 }
 
@@ -179,6 +208,13 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
                         writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
         }
 
+        if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
+                if (val & SDHCI_INT_ADMA_ERROR) {
+                        val &= ~SDHCI_INT_ADMA_ERROR;
+                        val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
+                }
+        }
+
         writel(val, host->ioaddr + reg);
 }
 
@@ -311,9 +347,10 @@ static struct sdhci_ops sdhci_esdhc_ops = {
 };
 
 static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
-        .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
+        .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
+                        | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
+                        | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
-        /* ADMA has issues. Might be fixable */
         .ops = &sdhci_esdhc_ops,
 };
 
@@ -405,7 +442,8 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
 
         if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
-                host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
+                host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
+                        | SDHCI_QUIRK_BROKEN_ADMA;
 
         if (is_imx53_esdhc(imx_data))
                 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;