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-rw-r--r--Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt60
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt120
-rw-r--r--Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt140
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--Documentation/pinctrl.txt18
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/dbx5x0.dtsi10
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi30
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts2
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi23
-rw-r--r--arch/arm/mach-sunxi/Kconfig1
-rw-r--r--arch/arm/mach-ux500/Kconfig6
-rw-r--r--arch/arm/mach-ux500/board-mop500.c20
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c2
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h10
-rw-r--r--drivers/base/Makefile1
-rw-r--r--drivers/base/dd.c7
-rw-r--r--drivers/base/pinctrl.c69
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-ab8500.c520
-rw-r--r--drivers/gpio/gpiolib-of.c2
-rw-r--r--drivers/pinctrl/Kconfig32
-rw-r--r--drivers/pinctrl/Makefile7
-rw-r--r--drivers/pinctrl/core.c118
-rw-r--r--drivers/pinctrl/core.h29
-rw-r--r--drivers/pinctrl/devicetree.c5
-rw-r--r--drivers/pinctrl/pinconf-generic.c4
-rw-r--r--drivers/pinctrl/pinconf.c207
-rw-r--r--drivers/pinctrl/pinctrl-ab8500.c484
-rw-r--r--drivers/pinctrl/pinctrl-ab8505.c380
-rw-r--r--drivers/pinctrl/pinctrl-ab8540.c407
-rw-r--r--drivers/pinctrl/pinctrl-ab9540.c485
-rw-r--r--drivers/pinctrl/pinctrl-abx500.c1012
-rw-r--r--drivers/pinctrl/pinctrl-abx500.h234
-rw-r--r--drivers/pinctrl/pinctrl-falcon.c38
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.c56
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.h1
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c390
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c1
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c1505
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.h478
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c14
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h16
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c2769
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c6
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c4
-rw-r--r--drivers/pinctrl/pinctrl-xway.c60
-rw-r--r--include/linux/device.h7
-rw-r--r--include/linux/mfd/abx500/ab8500-gpio.h16
-rw-r--r--include/linux/mfd/abx500/ab8500.h279
-rw-r--r--include/linux/pinctrl/devinfo.h45
-rw-r--r--include/linux/pinctrl/pinconf-generic.h16
-rw-r--r--include/linux/pinctrl/pinctrl.h1
54 files changed, 9415 insertions, 742 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
new file mode 100644
index 000000000000..dff0e5f995e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -0,0 +1,60 @@
1* Allwinner A1X Pin Controller
2
3The pins controlled by sunXi pin controller are organized in banks,
4each bank has 32 pins. Each pin has 7 multiplexing functions, with
5the first two functions being GPIO in and out. The configuration on
6the pins includes drive strength and pull-up.
7
8Required properties:
9- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:
10 sun5i-a13.
11- reg: Should contain the register physical address and length for the
12 pin controller.
13
14Please refer to pinctrl-bindings.txt in this directory for details of the
15common pinctrl bindings used by client devices.
16
17A pinctrl node should contain at least one subnodes representing the
18pinctrl groups available on the machine. Each subnode will list the
19pins it needs, and how they should be configured, with regard to muxer
20configuration, drive strength and pullups. If one of these options is
21not set, its actual value will be unspecified.
22
23Required subnode-properties:
24
25- allwinner,pins: List of strings containing the pin name.
26- allwinner,function: Function to mux the pins listed above to.
27
28Optional subnode-properties:
29- allwinner,drive: Integer. Represents the current sent to the pin
30 0: 10 mA
31 1: 20 mA
32 2: 30 mA
33 3: 40 mA
34- allwinner,pull: Integer.
35 0: No resistor
36 1: Pull-up resistor
37 2: Pull-down resistor
38
39Examples:
40
41pinctrl@01c20800 {
42 compatible = "allwinner,sun5i-a13-pinctrl";
43 reg = <0x01c20800 0x400>;
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 uart1_pins_a: uart1@0 {
48 allwinner,pins = "PE10", "PE11";
49 allwinner,function = "uart1";
50 allwinner,drive = <0>;
51 allwinner,pull = <0>;
52 };
53
54 uart1_pins_b: uart1@1 {
55 allwinner,pins = "PG3", "PG4";
56 allwinner,function = "uart1";
57 allwinner,drive = <0>;
58 allwinner,pull = <0>;
59 };
60};
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
new file mode 100644
index 000000000000..e204d009f16c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
@@ -0,0 +1,120 @@
1NVIDIA Tegra114 pinmux controller
2
3The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
4pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
5nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
6a baseline, and only documents the differences between the two bindings.
7
8Required properties:
9- compatible: "nvidia,tegra114-pinmux"
10- reg: Should contain the register physical address and length for each of
11 the pad control and mux registers. The first bank of address must be the
12 driver strength pad control register address and second bank address must
13 be pinmux register address.
14
15Tegra114 adds the following optional properties for pin configuration subnodes:
16- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
17- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
18- nvidia,lock: Integer. Lock the pin configuration against further changes
19 until reset. 0: no, 1: yes.
20- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
21- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
22- nvidia,drive-type: Integer. Valid range 0...3.
23
24As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
25which groups support which functionality.
26
27Valid values for pin and group names are:
28
29 per-pin mux groups:
30
31 These all support nvidia,function, nvidia,tristate, nvidia,pull,
32 nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
33 nvidia,io-reset and nvidia,rcv-sel.
34
35 ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
36 ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
37 ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
38 dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
39 sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
40 sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
41 ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
42 uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
43 uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
44 gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
45 clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
46 gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
47 gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
48 gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
49 gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
50 gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
51 gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
52 gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
53 gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
54 sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
55 sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
56 pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
57 pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
58 kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
59 kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
60 kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
61 kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
62 cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
63 dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
64 dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
65 gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
66 gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
67 sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
68 sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
69 gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
70 sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
71
72 drive groups:
73
74 These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
75 nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
76 support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
77 and nvidia,drive-type.
78
79 ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
80 dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
81 gmh, owr, uda.
82
83Example:
84
85 pinmux: pinmux {
86 compatible = "nvidia,tegra114-pinmux";
87 reg = <0x70000868 0x148 /* Pad control registers */
88 0x70003000 0x40c>; /* PinMux registers */
89 };
90
91Example board file extract:
92
93 pinctrl {
94 sdmmc4_default: pinmux {
95 sdmmc4_clk_pcc4 {
96 nvidia,pins = "sdmmc4_clk_pcc4",
97 nvidia,function = "sdmmc4";
98 nvidia,pull = <0>;
99 nvidia,tristate = <0>;
100 };
101 sdmmc4_dat0_paa0 {
102 nvidia,pins = "sdmmc4_dat0_paa0",
103 "sdmmc4_dat1_paa1",
104 "sdmmc4_dat2_paa2",
105 "sdmmc4_dat3_paa3",
106 "sdmmc4_dat4_paa4",
107 "sdmmc4_dat5_paa5",
108 "sdmmc4_dat6_paa6",
109 "sdmmc4_dat7_paa7";
110 nvidia,function = "sdmmc4";
111 nvidia,pull = <2>;
112 nvidia,tristate = <0>;
113 };
114 };
115 };
116
117 sdhci@78000400 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&sdmmc4_default>;
120 };
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
new file mode 100644
index 000000000000..9a2f3f420526
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
@@ -0,0 +1,140 @@
1ST Ericsson Nomadik pinmux controller
2
3Required properties:
4- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
5 "stericsson,nmk-pinctrl-stn8815"
6- reg: Should contain the register physical address and length of the PRCMU.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as input, output, pull up, pull down...
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Required subnode-properties:
22- ste,pins : An array of strings. Each string contains the name of a pin or
23 group.
24
25Optional subnode-properties:
26- ste,function: A string containing the name of the function to mux to the
27 pin or group.
28
29- ste,config: Handle of pin configuration node (e.g. ste,config = <&slpm_in_wkup_pdis>)
30
31- ste,input : <0/1/2>
32 0: input with no pull
33 1: input with pull up,
34 2: input with pull down,
35
36- ste,output: <0/1/2>
37 0: output low,
38 1: output high,
39 2: output (value is not specified).
40
41- ste,sleep: <0/1>
42 0: sleep mode disable,
43 1: sleep mode enable.
44
45- ste,sleep-input: <0/1/2/3>
46 0: sleep input with no pull,
47 1: sleep input with pull up,
48 2: sleep input with pull down.
49 3: sleep input and keep last input configuration (no pull, pull up or pull down).
50
51- ste,sleep-output: <0/1/2>
52 0: sleep output low,
53 1: sleep output high,
54 2: sleep output (value is not specified).
55
56- ste,sleep-gpio: <0/1>
57 0: disable sleep gpio mode,
58 1: enable sleep gpio mode.
59
60- ste,sleep-wakeup: <0/1>
61 0: wake-up detection enabled,
62 1: wake-up detection disabled.
63
64- ste,sleep-pull-disable: <0/1>
65 0: GPIO pull-up or pull-down resistor is enabled, when pin is an input,
66 1: GPIO pull-up and pull-down resistor are disabled.
67
68Example board file extract:
69
70 pinctrl@80157000 {
71 compatible = "stericsson,nmk-pinctrl";
72 reg = <0x80157000 0x2000>;
73
74 pinctrl-names = "default";
75
76 slpm_in_wkup_pdis: slpm_in_wkup_pdis {
77 ste,sleep = <1>;
78 ste,sleep-input = <3>;
79 ste,sleep-wakeup = <1>;
80 ste,sleep-pull-disable = <0>;
81 };
82
83 slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
84 ste,sleep = <1>;
85 ste,sleep-output = <1>;
86 ste,sleep-wakeup = <1>;
87 ste,sleep-pull-disable = <0>;
88 };
89
90 slpm_out_wkup_pdis: slpm_out_wkup_pdis {
91 ste,sleep = <1>;
92 ste,sleep-output = <2>;
93 ste,sleep-wakeup = <1>;
94 ste,sleep-pull-disable = <0>;
95 };
96
97 uart0 {
98 uart0_default_mux: uart0_mux {
99 u0_default_mux {
100 ste,function = "u0";
101 ste,pins = "u0_a_1";
102 };
103 };
104 uart0_default_mode: uart0_default {
105 uart0_default_cfg1 {
106 ste,pins = "GPIO0", "GPIO2";
107 ste,input = <1>;
108 };
109
110 uart0_default_cfg2 {
111 ste,pins = "GPIO1", "GPIO3";
112 ste,output = <1>;
113 };
114 };
115 uart0_sleep_mode: uart0_sleep {
116 uart0_sleep_cfg1 {
117 ste,pins = "GPIO0", "GPIO2";
118 ste,config = <&slpm_in_wkup_pdis>;
119 };
120 uart0_sleep_cfg2 {
121 ste,pins = "GPIO1";
122 ste,config = <&slpm_out_hi_wkup_pdis>;
123 };
124 uart0_sleep_cfg3 {
125 ste,pins = "GPIO3";
126 ste,config = <&slpm_out_wkup_pdis>;
127 };
128 };
129 };
130 };
131
132 uart@80120000 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0x80120000 0x1000>;
135 interrupts = <0 11 0x4>;
136
137 pinctrl-names = "default","sleep";
138 pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
139 pinctrl-1 = <&uart0_sleep_mode>;
140 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 902b1b1f568e..15321373ec8d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -50,6 +50,7 @@ simtek
50sirf SiRF Technology, Inc. 50sirf SiRF Technology, Inc.
51snps Synopsys, Inc. 51snps Synopsys, Inc.
52st STMicroelectronics 52st STMicroelectronics
53ste ST-Ericsson
53stericsson ST-Ericsson 54stericsson ST-Ericsson
54ti Texas Instruments 55ti Texas Instruments
55via VIA Technologies, Inc. 56via VIA Technologies, Inc.
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index da40efbef6ec..a2b57e0a1db0 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -972,6 +972,18 @@ pinmux core.
972Pin control requests from drivers 972Pin control requests from drivers
973================================= 973=================================
974 974
975When a device driver is about to probe the device core will automatically
976attempt to issue pinctrl_get_select_default() on these devices.
977This way driver writers do not need to add any of the boilerplate code
978of the type found below. However when doing fine-grained state selection
979and not using the "default" state, you may have to do some device driver
980handling of the pinctrl handles and states.
981
982So if you just want to put the pins for a certain device into the default
983state and be done with it, there is nothing you need to do besides
984providing the proper mapping table. The device core will take care of
985the rest.
986
975Generally it is discouraged to let individual drivers get and enable pin 987Generally it is discouraged to let individual drivers get and enable pin
976control. So if possible, handle the pin control in platform code or some other 988control. So if possible, handle the pin control in platform code or some other
977place where you have access to all the affected struct device * pointers. In 989place where you have access to all the affected struct device * pointers. In
@@ -1097,9 +1109,9 @@ situations that can be electrically unpleasant, you will certainly want to
1097mux in and bias pins in a certain way before the GPIO subsystems starts to 1109mux in and bias pins in a certain way before the GPIO subsystems starts to
1098deal with them. 1110deal with them.
1099 1111
1100The above can be hidden: using pinctrl hogs, the pin control driver may be 1112The above can be hidden: using the device core, the pinctrl core may be
1101setting up the config and muxing for the pins when it is probing, 1113setting up the config and muxing for the pins right before the device is
1102nevertheless orthogonal to the GPIO subsystem. 1114probing, nevertheless orthogonal to the GPIO subsystem.
1103 1115
1104But there are also situations where it makes sense for the GPIO subsystem 1116But there are also situations where it makes sense for the GPIO subsystem
1105to communicate directly with with the pinctrl subsystem, using the latter 1117to communicate directly with with the pinctrl subsystem, using the latter
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9bbe760f2352..6c0900a9bf5c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1636,7 +1636,7 @@ config ARCH_NR_GPIO
1636 default 355 if ARCH_U8500 1636 default 355 if ARCH_U8500
1637 default 264 if MACH_H4700 1637 default 264 if MACH_H4700
1638 default 512 if SOC_OMAP5 1638 default 512 if SOC_OMAP5
1639 default 288 if ARCH_VT8500 1639 default 288 if ARCH_VT8500 || ARCH_SUNXI
1640 default 0 1640 default 0
1641 help 1641 help
1642 Maximum number of GPIOs in the system. 1642 Maximum number of GPIOs in the system.
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 63f2fbcfe819..69140ba99f46 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -170,10 +170,9 @@
170 gpio-bank = <8>; 170 gpio-bank = <8>;
171 }; 171 };
172 172
173 pinctrl@80157000 { 173 pinctrl {
174 // This is actually the PRCMU base address 174 compatible = "stericsson,nmk-pinctrl";
175 reg = <0x80157000 0x2000>; 175 prcm = <&prcmu>;
176 compatible = "stericsson,nmk_pinctrl";
177 }; 176 };
178 177
179 usb@a03e0000 { 178 usb@a03e0000 {
@@ -190,9 +189,10 @@
190 interrupts = <0 25 0x4>; 189 interrupts = <0 25 0x4>;
191 }; 190 };
192 191
193 prcmu@80157000 { 192 prcmu: prcmu@80157000 {
194 compatible = "stericsson,db8500-prcmu"; 193 compatible = "stericsson,db8500-prcmu";
195 reg = <0x80157000 0x1000>; 194 reg = <0x80157000 0x1000>;
195 reg-names = "prcmu";
196 interrupts = <0 47 0x4>; 196 interrupts = <0 47 0x4>;
197 #address-cells = <1>; 197 #address-cells = <1>;
198 #size-cells = <1>; 198 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e61fdd47bd01..f99f60dadf5d 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -16,4 +16,34 @@
16 memory { 16 memory {
17 reg = <0x40000000 0x80000000>; 17 reg = <0x40000000 0x80000000>;
18 }; 18 };
19
20 soc {
21 pinctrl@01c20800 {
22 compatible = "allwinner,sun4i-a10-pinctrl";
23 reg = <0x01c20800 0x400>;
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 uart0_pins_a: uart0@0 {
28 allwinner,pins = "PB22", "PB23";
29 allwinner,function = "uart0";
30 allwinner,drive = <0>;
31 allwinner,pull = <0>;
32 };
33
34 uart0_pins_b: uart0@1 {
35 allwinner,pins = "PF2", "PF4";
36 allwinner,function = "uart0";
37 allwinner,drive = <0>;
38 allwinner,pull = <0>;
39 };
40
41 uart1_pins_a: uart1@0 {
42 allwinner,pins = "PA10", "PA11";
43 allwinner,function = "uart1";
44 allwinner,drive = <0>;
45 allwinner,pull = <0>;
46 };
47 };
48 };
19}; 49};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 498a091a4ea2..4a1e45d4aace 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -24,6 +24,8 @@
24 24
25 soc { 25 soc {
26 uart1: uart@01c28400 { 26 uart1: uart@01c28400 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart1_pins_b>;
27 status = "okay"; 29 status = "okay";
28 }; 30 };
29 }; 31 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 59a2d265a98e..e1121890fb29 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -17,4 +17,27 @@
17 memory { 17 memory {
18 reg = <0x40000000 0x20000000>; 18 reg = <0x40000000 0x20000000>;
19 }; 19 };
20
21 soc {
22 pinctrl@01c20800 {
23 compatible = "allwinner,sun5i-a13-pinctrl";
24 reg = <0x01c20800 0x400>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 uart1_pins_a: uart1@0 {
29 allwinner,pins = "PE10", "PE11";
30 allwinner,function = "uart1";
31 allwinner,drive = <0>;
32 allwinner,pull = <0>;
33 };
34
35 uart1_pins_b: uart1@1 {
36 allwinner,pins = "PG3", "PG4";
37 allwinner,function = "uart1";
38 allwinner,drive = <0>;
39 allwinner,pull = <0>;
40 };
41 };
42 };
20}; 43};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3fdd0085e306..8709a39bd34c 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -7,3 +7,4 @@ config ARCH_SUNXI
7 select PINCTRL 7 select PINCTRL
8 select SPARSE_IRQ 8 select SPARSE_IRQ
9 select SUNXI_TIMER 9 select SUNXI_TIMER
10 select PINCTRL_SUNXI \ No newline at end of file
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 5dea90636d94..3e5bbd0e5b23 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
11 select COMMON_CLK 11 select COMMON_CLK
12 select PINCTRL 12 select PINCTRL
13 select PINCTRL_NOMADIK 13 select PINCTRL_NOMADIK
14 select PINCTRL_ABX500
14 select PL310_ERRATA_753970 if CACHE_PL310 15 select PL310_ERRATA_753970 if CACHE_PL310
15 16
16config UX500_SOC_DB8500 17config UX500_SOC_DB8500
@@ -18,6 +19,11 @@ config UX500_SOC_DB8500
18 select CPU_FREQ_TABLE if CPU_FREQ 19 select CPU_FREQ_TABLE if CPU_FREQ
19 select MFD_DB8500_PRCMU 20 select MFD_DB8500_PRCMU
20 select PINCTRL_DB8500 21 select PINCTRL_DB8500
22 select PINCTRL_DB8540
23 select PINCTRL_AB8500
24 select PINCTRL_AB8505
25 select PINCTRL_AB9540
26 select PINCTRL_AB8540
21 select REGULATOR 27 select REGULATOR
22 select REGULATOR_DB8500_PRCMU 28 select REGULATOR_DB8500_PRCMU
23 29
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index d453522edb0d..b8781caa54b8 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -90,26 +90,8 @@ static struct platform_device snowball_gpio_en_3v3_regulator_dev = {
90 }, 90 },
91}; 91};
92 92
93static struct ab8500_gpio_platform_data ab8500_gpio_pdata = { 93static struct abx500_gpio_platform_data ab8500_gpio_pdata = {
94 .gpio_base = MOP500_AB8500_PIN_GPIO(1), 94 .gpio_base = MOP500_AB8500_PIN_GPIO(1),
95 .irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
96 /* config_reg is the initial configuration of ab8500 pins.
97 * The pins can be configured as GPIO or alt functions based
98 * on value present in GpioSel1 to GpioSel6 and AlternatFunction
99 * register. This is the array of 7 configuration settings.
100 * One has to compile time decide these settings. Below is the
101 * explanation of these setting
102 * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
103 * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
104 * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
105 * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
106 * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
107 * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
108 * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
109 * as GPIO then this register selectes the alternate fucntions
110 */
111 .config_reg = {0x00, 0x1E, 0x80, 0x01,
112 0x7A, 0x00, 0x00},
113}; 95};
114 96
115/* ab8500-codec */ 97/* ab8500-codec */
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 5b286e06474c..b80ad9610e97 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -285,7 +285,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
285 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), 285 OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
286 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), 286 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
287 /* Requires device name bindings. */ 287 /* Requires device name bindings. */
288 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", U8500_PRCMU_BASE, 288 OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
289 "pinctrl-db8500", NULL), 289 "pinctrl-db8500", NULL),
290 /* Requires clock name and DMA bindings. */ 290 /* Requires clock name and DMA bindings. */
291 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000, 291 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 7d34c52798b5..d526dd8e87d3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -38,15 +38,7 @@
38#define MOP500_STMPE1601_IRQ_END \ 38#define MOP500_STMPE1601_IRQ_END \
39 MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS) 39 MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
40 40
41/* AB8500 virtual gpio IRQ */ 41#define MOP500_NR_IRQS MOP500_STMPE1601_IRQ_END
42#define AB8500_VIR_GPIO_NR_IRQS 16
43
44#define MOP500_AB8500_VIR_GPIO_IRQ_BASE \
45 MOP500_STMPE1601_IRQ_END
46#define MOP500_AB8500_VIR_GPIO_IRQ_END \
47 (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS)
48
49#define MOP500_NR_IRQS MOP500_AB8500_VIR_GPIO_IRQ_END
50 42
51#define MOP500_IRQ_END MOP500_NR_IRQS 43#define MOP500_IRQ_END MOP500_NR_IRQS
52 44
diff --git a/drivers/base/Makefile b/drivers/base/Makefile
index 5aa2d703d19f..4e22ce3ed73d 100644
--- a/drivers/base/Makefile
+++ b/drivers/base/Makefile
@@ -21,6 +21,7 @@ endif
21obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o 21obj-$(CONFIG_SYS_HYPERVISOR) += hypervisor.o
22obj-$(CONFIG_REGMAP) += regmap/ 22obj-$(CONFIG_REGMAP) += regmap/
23obj-$(CONFIG_SOC_BUS) += soc.o 23obj-$(CONFIG_SOC_BUS) += soc.o
24obj-$(CONFIG_PINCTRL) += pinctrl.o
24 25
25ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG 26ccflags-$(CONFIG_DEBUG_DRIVER) := -DDEBUG
26 27
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index e3bbed8a617c..656310156dde 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -24,6 +24,7 @@
24#include <linux/wait.h> 24#include <linux/wait.h>
25#include <linux/async.h> 25#include <linux/async.h>
26#include <linux/pm_runtime.h> 26#include <linux/pm_runtime.h>
27#include <linux/pinctrl/devinfo.h>
27 28
28#include "base.h" 29#include "base.h"
29#include "power/power.h" 30#include "power/power.h"
@@ -269,6 +270,12 @@ static int really_probe(struct device *dev, struct device_driver *drv)
269 WARN_ON(!list_empty(&dev->devres_head)); 270 WARN_ON(!list_empty(&dev->devres_head));
270 271
271 dev->driver = drv; 272 dev->driver = drv;
273
274 /* If using pinctrl, bind pins now before probing */
275 ret = pinctrl_bind_pins(dev);
276 if (ret)
277 goto probe_failed;
278
272 if (driver_sysfs_add(dev)) { 279 if (driver_sysfs_add(dev)) {
273 printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n", 280 printk(KERN_ERR "%s: driver_sysfs_add(%s) failed\n",
274 __func__, dev_name(dev)); 281 __func__, dev_name(dev));
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
new file mode 100644
index 000000000000..67a274e86727
--- /dev/null
+++ b/drivers/base/pinctrl.c
@@ -0,0 +1,69 @@
1/*
2 * Driver core interface to the pinctrl subsystem.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Written on behalf of Linaro for ST-Ericsson
6 * Based on bits of regulator core, gpio core and clk core
7 *
8 * Author: Linus Walleij <linus.walleij@linaro.org>
9 *
10 * License terms: GNU General Public License (GPL) version 2
11 */
12
13#include <linux/device.h>
14#include <linux/pinctrl/devinfo.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/slab.h>
17
18/**
19 * pinctrl_bind_pins() - called by the device core before probe
20 * @dev: the device that is just about to probe
21 */
22int pinctrl_bind_pins(struct device *dev)
23{
24 int ret;
25
26 dev->pins = devm_kzalloc(dev, sizeof(*(dev->pins)), GFP_KERNEL);
27 if (!dev->pins)
28 return -ENOMEM;
29
30 dev->pins->p = devm_pinctrl_get(dev);
31 if (IS_ERR(dev->pins->p)) {
32 dev_dbg(dev, "no pinctrl handle\n");
33 ret = PTR_ERR(dev->pins->p);
34 goto cleanup_alloc;
35 }
36
37 dev->pins->default_state = pinctrl_lookup_state(dev->pins->p,
38 PINCTRL_STATE_DEFAULT);
39 if (IS_ERR(dev->pins->default_state)) {
40 dev_dbg(dev, "no default pinctrl state\n");
41 ret = 0;
42 goto cleanup_get;
43 }
44
45 ret = pinctrl_select_state(dev->pins->p, dev->pins->default_state);
46 if (ret) {
47 dev_dbg(dev, "failed to activate default pinctrl state\n");
48 goto cleanup_get;
49 }
50
51 return 0;
52
53 /*
54 * If no pinctrl handle or default state was found for this device,
55 * let's explicitly free the pin container in the device, there is
56 * no point in keeping it around.
57 */
58cleanup_get:
59 devm_pinctrl_put(dev->pins->p);
60cleanup_alloc:
61 devm_kfree(dev, dev->pins);
62 dev->pins = NULL;
63
64 /* Only return deferrals */
65 if (ret != -EPROBE_DEFER)
66 ret = 0;
67
68 return ret;
69}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 682de754d63f..e5116fa85140 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -657,12 +657,6 @@ config GPIO_JANZ_TTL
657 This driver provides support for driving the pins in output 657 This driver provides support for driving the pins in output
658 mode only. Input mode is not supported. 658 mode only. Input mode is not supported.
659 659
660config GPIO_AB8500
661 bool "ST-Ericsson AB8500 Mixed Signal Circuit gpio functions"
662 depends on AB8500_CORE && BROKEN
663 help
664 Select this to enable the AB8500 IC GPIO driver
665
666config GPIO_TPS6586X 660config GPIO_TPS6586X
667 bool "TPS6586X GPIO" 661 bool "TPS6586X GPIO"
668 depends on MFD_TPS6586X 662 depends on MFD_TPS6586X
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c5aebd008dde..45a388c21d04 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_GPIO_ACPI) += gpiolib-acpi.o
10obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o 10obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
11 11
12obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o 12obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
13obj-$(CONFIG_GPIO_AB8500) += gpio-ab8500.o
14obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o 13obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
15obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o 14obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
16obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o 15obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o
diff --git a/drivers/gpio/gpio-ab8500.c b/drivers/gpio/gpio-ab8500.c
deleted file mode 100644
index 983ad425f0ac..000000000000
--- a/drivers/gpio/gpio-ab8500.c
+++ /dev/null
@@ -1,520 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2011
3 *
4 * Author: BIBEK BASU <bibek.basu@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/mfd/ab8500.h>
22#include <linux/mfd/abx500.h>
23#include <linux/mfd/ab8500/gpio.h>
24
25/*
26 * GPIO registers offset
27 * Bank: 0x10
28 */
29#define AB8500_GPIO_SEL1_REG 0x00
30#define AB8500_GPIO_SEL2_REG 0x01
31#define AB8500_GPIO_SEL3_REG 0x02
32#define AB8500_GPIO_SEL4_REG 0x03
33#define AB8500_GPIO_SEL5_REG 0x04
34#define AB8500_GPIO_SEL6_REG 0x05
35
36#define AB8500_GPIO_DIR1_REG 0x10
37#define AB8500_GPIO_DIR2_REG 0x11
38#define AB8500_GPIO_DIR3_REG 0x12
39#define AB8500_GPIO_DIR4_REG 0x13
40#define AB8500_GPIO_DIR5_REG 0x14
41#define AB8500_GPIO_DIR6_REG 0x15
42
43#define AB8500_GPIO_OUT1_REG 0x20
44#define AB8500_GPIO_OUT2_REG 0x21
45#define AB8500_GPIO_OUT3_REG 0x22
46#define AB8500_GPIO_OUT4_REG 0x23
47#define AB8500_GPIO_OUT5_REG 0x24
48#define AB8500_GPIO_OUT6_REG 0x25
49
50#define AB8500_GPIO_PUD1_REG 0x30
51#define AB8500_GPIO_PUD2_REG 0x31
52#define AB8500_GPIO_PUD3_REG 0x32
53#define AB8500_GPIO_PUD4_REG 0x33
54#define AB8500_GPIO_PUD5_REG 0x34
55#define AB8500_GPIO_PUD6_REG 0x35
56
57#define AB8500_GPIO_IN1_REG 0x40
58#define AB8500_GPIO_IN2_REG 0x41
59#define AB8500_GPIO_IN3_REG 0x42
60#define AB8500_GPIO_IN4_REG 0x43
61#define AB8500_GPIO_IN5_REG 0x44
62#define AB8500_GPIO_IN6_REG 0x45
63#define AB8500_GPIO_ALTFUN_REG 0x45
64#define ALTFUN_REG_INDEX 6
65#define AB8500_NUM_GPIO 42
66#define AB8500_NUM_VIR_GPIO_IRQ 16
67
68enum ab8500_gpio_action {
69 NONE,
70 STARTUP,
71 SHUTDOWN,
72 MASK,
73 UNMASK
74};
75
76struct ab8500_gpio {
77 struct gpio_chip chip;
78 struct ab8500 *parent;
79 struct device *dev;
80 struct mutex lock;
81 u32 irq_base;
82 enum ab8500_gpio_action irq_action;
83 u16 rising;
84 u16 falling;
85};
86/**
87 * to_ab8500_gpio() - get the pointer to ab8500_gpio
88 * @chip: Member of the structure ab8500_gpio
89 */
90static inline struct ab8500_gpio *to_ab8500_gpio(struct gpio_chip *chip)
91{
92 return container_of(chip, struct ab8500_gpio, chip);
93}
94
95static int ab8500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
96 unsigned offset, int val)
97{
98 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
99 u8 pos = offset % 8;
100 int ret;
101
102 reg = reg + (offset / 8);
103 ret = abx500_mask_and_set_register_interruptible(ab8500_gpio->dev,
104 AB8500_MISC, reg, 1 << pos, val << pos);
105 if (ret < 0)
106 dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
107 return ret;
108}
109/**
110 * ab8500_gpio_get() - Get the particular GPIO value
111 * @chip: Gpio device
112 * @offset: GPIO number to read
113 */
114static int ab8500_gpio_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
117 u8 mask = 1 << (offset % 8);
118 u8 reg = AB8500_GPIO_OUT1_REG + (offset / 8);
119 int ret;
120 u8 data;
121 ret = abx500_get_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
122 reg, &data);
123 if (ret < 0) {
124 dev_err(ab8500_gpio->dev, "%s read failed\n", __func__);
125 return ret;
126 }
127 return (data & mask) >> (offset % 8);
128}
129
130static void ab8500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
131{
132 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
133 int ret;
134 /* Write the data */
135 ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, 1);
136 if (ret < 0)
137 dev_err(ab8500_gpio->dev, "%s write failed\n", __func__);
138}
139
140static int ab8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
141 int val)
142{
143 int ret;
144 /* set direction as output */
145 ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
146 if (ret < 0)
147 return ret;
148 /* disable pull down */
149 ret = ab8500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
150 if (ret < 0)
151 return ret;
152 /* set the output as 1 or 0 */
153 return ab8500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
154
155}
156
157static int ab8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
158{
159 /* set the register as input */
160 return ab8500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
161}
162
163static int ab8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
164{
165 /*
166 * Only some GPIOs are interrupt capable, and they are
167 * organized in discontiguous clusters:
168 *
169 * GPIO6 to GPIO13
170 * GPIO24 and GPIO25
171 * GPIO36 to GPIO41
172 */
173 static struct ab8500_gpio_irq_cluster {
174 int start;
175 int end;
176 } clusters[] = {
177 {.start = 6, .end = 13},
178 {.start = 24, .end = 25},
179 {.start = 36, .end = 41},
180 };
181 struct ab8500_gpio *ab8500_gpio = to_ab8500_gpio(chip);
182 int base = ab8500_gpio->irq_base;
183 int i;
184
185 for (i = 0; i < ARRAY_SIZE(clusters); i++) {
186 struct ab8500_gpio_irq_cluster *cluster = &clusters[i];
187
188 if (offset >= cluster->start && offset <= cluster->end)
189 return base + offset - cluster->start;
190
191 /* Advance by the number of gpios in this cluster */
192 base += cluster->end - cluster->start + 1;
193 }
194
195 return -EINVAL;
196}
197
198static struct gpio_chip ab8500gpio_chip = {
199 .label = "ab8500_gpio",
200 .owner = THIS_MODULE,
201 .direction_input = ab8500_gpio_direction_input,
202 .get = ab8500_gpio_get,
203 .direction_output = ab8500_gpio_direction_output,
204 .set = ab8500_gpio_set,
205 .to_irq = ab8500_gpio_to_irq,
206};
207
208static unsigned int irq_to_rising(unsigned int irq)
209{
210 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
211 int offset = irq - ab8500_gpio->irq_base;
212 int new_irq = offset + AB8500_INT_GPIO6R
213 + ab8500_gpio->parent->irq_base;
214 return new_irq;
215}
216
217static unsigned int irq_to_falling(unsigned int irq)
218{
219 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
220 int offset = irq - ab8500_gpio->irq_base;
221 int new_irq = offset + AB8500_INT_GPIO6F
222 + ab8500_gpio->parent->irq_base;
223 return new_irq;
224
225}
226
227static unsigned int rising_to_irq(unsigned int irq, void *dev)
228{
229 struct ab8500_gpio *ab8500_gpio = dev;
230 int offset = irq - AB8500_INT_GPIO6R
231 - ab8500_gpio->parent->irq_base ;
232 int new_irq = offset + ab8500_gpio->irq_base;
233 return new_irq;
234}
235
236static unsigned int falling_to_irq(unsigned int irq, void *dev)
237{
238 struct ab8500_gpio *ab8500_gpio = dev;
239 int offset = irq - AB8500_INT_GPIO6F
240 - ab8500_gpio->parent->irq_base ;
241 int new_irq = offset + ab8500_gpio->irq_base;
242 return new_irq;
243
244}
245
246/*
247 * IRQ handler
248 */
249
250static irqreturn_t handle_rising(int irq, void *dev)
251{
252
253 handle_nested_irq(rising_to_irq(irq , dev));
254 return IRQ_HANDLED;
255}
256
257static irqreturn_t handle_falling(int irq, void *dev)
258{
259
260 handle_nested_irq(falling_to_irq(irq, dev));
261 return IRQ_HANDLED;
262}
263
264static void ab8500_gpio_irq_lock(unsigned int irq)
265{
266 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
267 mutex_lock(&ab8500_gpio->lock);
268}
269
270static void ab8500_gpio_irq_sync_unlock(unsigned int irq)
271{
272 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
273 int offset = irq - ab8500_gpio->irq_base;
274 bool rising = ab8500_gpio->rising & BIT(offset);
275 bool falling = ab8500_gpio->falling & BIT(offset);
276 int ret;
277
278 switch (ab8500_gpio->irq_action) {
279 case STARTUP:
280 if (rising)
281 ret = request_threaded_irq(irq_to_rising(irq),
282 NULL, handle_rising,
283 IRQF_TRIGGER_RISING,
284 "ab8500-gpio-r", ab8500_gpio);
285 if (falling)
286 ret = request_threaded_irq(irq_to_falling(irq),
287 NULL, handle_falling,
288 IRQF_TRIGGER_FALLING,
289 "ab8500-gpio-f", ab8500_gpio);
290 break;
291 case SHUTDOWN:
292 if (rising)
293 free_irq(irq_to_rising(irq), ab8500_gpio);
294 if (falling)
295 free_irq(irq_to_falling(irq), ab8500_gpio);
296 break;
297 case MASK:
298 if (rising)
299 disable_irq(irq_to_rising(irq));
300 if (falling)
301 disable_irq(irq_to_falling(irq));
302 break;
303 case UNMASK:
304 if (rising)
305 enable_irq(irq_to_rising(irq));
306 if (falling)
307 enable_irq(irq_to_falling(irq));
308 break;
309 case NONE:
310 break;
311 }
312 ab8500_gpio->irq_action = NONE;
313 ab8500_gpio->rising &= ~(BIT(offset));
314 ab8500_gpio->falling &= ~(BIT(offset));
315 mutex_unlock(&ab8500_gpio->lock);
316}
317
318
319static void ab8500_gpio_irq_mask(unsigned int irq)
320{
321 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
322 ab8500_gpio->irq_action = MASK;
323}
324
325static void ab8500_gpio_irq_unmask(unsigned int irq)
326{
327 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
328 ab8500_gpio->irq_action = UNMASK;
329}
330
331static int ab8500_gpio_irq_set_type(unsigned int irq, unsigned int type)
332{
333 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
334 int offset = irq - ab8500_gpio->irq_base;
335
336 if (type == IRQ_TYPE_EDGE_BOTH) {
337 ab8500_gpio->rising = BIT(offset);
338 ab8500_gpio->falling = BIT(offset);
339 } else if (type == IRQ_TYPE_EDGE_RISING) {
340 ab8500_gpio->rising = BIT(offset);
341 } else {
342 ab8500_gpio->falling = BIT(offset);
343 }
344 return 0;
345}
346
347unsigned int ab8500_gpio_irq_startup(unsigned int irq)
348{
349 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
350 ab8500_gpio->irq_action = STARTUP;
351 return 0;
352}
353
354void ab8500_gpio_irq_shutdown(unsigned int irq)
355{
356 struct ab8500_gpio *ab8500_gpio = get_irq_chip_data(irq);
357 ab8500_gpio->irq_action = SHUTDOWN;
358}
359
360static struct irq_chip ab8500_gpio_irq_chip = {
361 .name = "ab8500-gpio",
362 .startup = ab8500_gpio_irq_startup,
363 .shutdown = ab8500_gpio_irq_shutdown,
364 .bus_lock = ab8500_gpio_irq_lock,
365 .bus_sync_unlock = ab8500_gpio_irq_sync_unlock,
366 .mask = ab8500_gpio_irq_mask,
367 .unmask = ab8500_gpio_irq_unmask,
368 .set_type = ab8500_gpio_irq_set_type,
369};
370
371static int ab8500_gpio_irq_init(struct ab8500_gpio *ab8500_gpio)
372{
373 u32 base = ab8500_gpio->irq_base;
374 int irq;
375
376 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) {
377 set_irq_chip_data(irq, ab8500_gpio);
378 set_irq_chip_and_handler(irq, &ab8500_gpio_irq_chip,
379 handle_simple_irq);
380 set_irq_nested_thread(irq, 1);
381#ifdef CONFIG_ARM
382 set_irq_flags(irq, IRQF_VALID);
383#else
384 set_irq_noprobe(irq);
385#endif
386 }
387
388 return 0;
389}
390
391static void ab8500_gpio_irq_remove(struct ab8500_gpio *ab8500_gpio)
392{
393 int base = ab8500_gpio->irq_base;
394 int irq;
395
396 for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) {
397#ifdef CONFIG_ARM
398 set_irq_flags(irq, 0);
399#endif
400 set_irq_chip_and_handler(irq, NULL, NULL);
401 set_irq_chip_data(irq, NULL);
402 }
403}
404
405static int ab8500_gpio_probe(struct platform_device *pdev)
406{
407 struct ab8500_platform_data *ab8500_pdata =
408 dev_get_platdata(pdev->dev.parent);
409 struct ab8500_gpio_platform_data *pdata;
410 struct ab8500_gpio *ab8500_gpio;
411 int ret;
412 int i;
413
414 pdata = ab8500_pdata->gpio;
415 if (!pdata) {
416 dev_err(&pdev->dev, "gpio platform data missing\n");
417 return -ENODEV;
418 }
419
420 ab8500_gpio = kzalloc(sizeof(struct ab8500_gpio), GFP_KERNEL);
421 if (ab8500_gpio == NULL) {
422 dev_err(&pdev->dev, "failed to allocate memory\n");
423 return -ENOMEM;
424 }
425 ab8500_gpio->dev = &pdev->dev;
426 ab8500_gpio->parent = dev_get_drvdata(pdev->dev.parent);
427 ab8500_gpio->chip = ab8500gpio_chip;
428 ab8500_gpio->chip.ngpio = AB8500_NUM_GPIO;
429 ab8500_gpio->chip.dev = &pdev->dev;
430 ab8500_gpio->chip.base = pdata->gpio_base;
431 ab8500_gpio->irq_base = pdata->irq_base;
432 /* initialize the lock */
433 mutex_init(&ab8500_gpio->lock);
434 /*
435 * AB8500 core will handle and clear the IRQ
436 * configre GPIO based on config-reg value.
437 * These values are for selecting the PINs as
438 * GPIO or alternate function
439 */
440 for (i = AB8500_GPIO_SEL1_REG; i <= AB8500_GPIO_SEL6_REG; i++) {
441 ret = abx500_set_register_interruptible(ab8500_gpio->dev,
442 AB8500_MISC, i,
443 pdata->config_reg[i]);
444 if (ret < 0)
445 goto out_free;
446 }
447 ret = abx500_set_register_interruptible(ab8500_gpio->dev, AB8500_MISC,
448 AB8500_GPIO_ALTFUN_REG,
449 pdata->config_reg[ALTFUN_REG_INDEX]);
450 if (ret < 0)
451 goto out_free;
452
453 ret = ab8500_gpio_irq_init(ab8500_gpio);
454 if (ret)
455 goto out_free;
456 ret = gpiochip_add(&ab8500_gpio->chip);
457 if (ret) {
458 dev_err(&pdev->dev, "unable to add gpiochip: %d\n",
459 ret);
460 goto out_rem_irq;
461 }
462 platform_set_drvdata(pdev, ab8500_gpio);
463 return 0;
464
465out_rem_irq:
466 ab8500_gpio_irq_remove(ab8500_gpio);
467out_free:
468 mutex_destroy(&ab8500_gpio->lock);
469 kfree(ab8500_gpio);
470 return ret;
471}
472
473/*
474 * ab8500_gpio_remove() - remove Ab8500-gpio driver
475 * @pdev : Platform device registered
476 */
477static int ab8500_gpio_remove(struct platform_device *pdev)
478{
479 struct ab8500_gpio *ab8500_gpio = platform_get_drvdata(pdev);
480 int ret;
481
482 ret = gpiochip_remove(&ab8500_gpio->chip);
483 if (ret < 0) {
484 dev_err(ab8500_gpio->dev, "unable to remove gpiochip: %d\n",
485 ret);
486 return ret;
487 }
488
489 platform_set_drvdata(pdev, NULL);
490 mutex_destroy(&ab8500_gpio->lock);
491 kfree(ab8500_gpio);
492
493 return 0;
494}
495
496static struct platform_driver ab8500_gpio_driver = {
497 .driver = {
498 .name = "ab8500-gpio",
499 .owner = THIS_MODULE,
500 },
501 .probe = ab8500_gpio_probe,
502 .remove = ab8500_gpio_remove,
503};
504
505static int __init ab8500_gpio_init(void)
506{
507 return platform_driver_register(&ab8500_gpio_driver);
508}
509arch_initcall(ab8500_gpio_init);
510
511static void __exit ab8500_gpio_exit(void)
512{
513 platform_driver_unregister(&ab8500_gpio_driver);
514}
515module_exit(ab8500_gpio_exit);
516
517MODULE_AUTHOR("BIBEK BASU <bibek.basu@stericsson.com>");
518MODULE_DESCRIPTION("Driver allows to use AB8500 unused pins to be used as GPIO");
519MODULE_ALIAS("platform:ab8500-gpio");
520MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index d542a141811a..25b1dbe8921d 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -250,7 +250,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
250 * on the same GPIO chip. 250 * on the same GPIO chip.
251 */ 251 */
252 ret = gpiochip_add_pin_range(chip, 252 ret = gpiochip_add_pin_range(chip,
253 pinctrl_dev_get_name(pctldev), 253 pinctrl_dev_get_devname(pctldev),
254 0, /* offset in gpiochip */ 254 0, /* offset in gpiochip */
255 pinspec.args[0], 255 pinspec.args[0],
256 pinspec.args[1]); 256 pinspec.args[1]);
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a5f3c8ca480e..393b0ecf4ca4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -26,6 +26,29 @@ config DEBUG_PINCTRL
26 help 26 help
27 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
28 28
29config PINCTRL_ABX500
30 bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
31 depends on AB8500_CORE
32 select GENERIC_PINCONF
33 help
34 Select this to enable the ABx500 family IC GPIO driver
35
36config PINCTRL_AB8500
37 bool "AB8500 pin controller driver"
38 depends on PINCTRL_ABX500 && ARCH_U8500
39
40config PINCTRL_AB8540
41 bool "AB8540 pin controller driver"
42 depends on PINCTRL_ABX500 && ARCH_U8500
43
44config PINCTRL_AB9540
45 bool "AB9540 pin controller driver"
46 depends on PINCTRL_ABX500 && ARCH_U8500
47
48config PINCTRL_AB8505
49 bool "AB8505 pin controller driver"
50 depends on PINCTRL_ABX500 && ARCH_U8500
51
29config PINCTRL_AT91 52config PINCTRL_AT91
30 bool "AT91 pinctrl driver" 53 bool "AT91 pinctrl driver"
31 depends on OF 54 depends on OF
@@ -151,6 +174,11 @@ config PINCTRL_SIRF
151 depends on ARCH_SIRF 174 depends on ARCH_SIRF
152 select PINMUX 175 select PINMUX
153 176
177config PINCTRL_SUNXI
178 bool
179 select PINMUX
180 select GENERIC_PINCONF
181
154config PINCTRL_TEGRA 182config PINCTRL_TEGRA
155 bool 183 bool
156 select PINMUX 184 select PINMUX
@@ -164,6 +192,10 @@ config PINCTRL_TEGRA30
164 bool 192 bool
165 select PINCTRL_TEGRA 193 select PINCTRL_TEGRA
166 194
195config PINCTRL_TEGRA114
196 bool
197 select PINCTRL_TEGRA
198
167config PINCTRL_U300 199config PINCTRL_U300
168 bool "U300 pin controller driver" 200 bool "U300 pin controller driver"
169 depends on ARCH_U300 201 depends on ARCH_U300
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6e87e52eab5d..0fd5f57fcb57 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -9,6 +9,11 @@ ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o 9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif 10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_ABX500) += pinctrl-abx500.o
13obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
12obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 17obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
13obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 18obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
14obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 19obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
@@ -30,9 +35,11 @@ obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
30obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 35obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
31obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 36obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
32obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 37obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
38obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
33obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 39obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
34obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 40obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
35obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 41obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
42obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
36obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 43obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
37obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 44obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
38obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o 45obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 59f5a965bdc4..b0de6e7f1fdb 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -14,6 +14,7 @@
14#define pr_fmt(fmt) "pinctrl core: " fmt 14#define pr_fmt(fmt) "pinctrl core: " fmt
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/kref.h>
17#include <linux/export.h> 18#include <linux/export.h>
18#include <linux/init.h> 19#include <linux/init.h>
19#include <linux/device.h> 20#include <linux/device.h>
@@ -31,17 +32,6 @@
31#include "pinmux.h" 32#include "pinmux.h"
32#include "pinconf.h" 33#include "pinconf.h"
33 34
34/**
35 * struct pinctrl_maps - a list item containing part of the mapping table
36 * @node: mapping table list node
37 * @maps: array of mapping table entries
38 * @num_maps: the number of entries in @maps
39 */
40struct pinctrl_maps {
41 struct list_head node;
42 struct pinctrl_map const *maps;
43 unsigned num_maps;
44};
45 35
46static bool pinctrl_dummy_state; 36static bool pinctrl_dummy_state;
47 37
@@ -55,13 +45,8 @@ LIST_HEAD(pinctrldev_list);
55static LIST_HEAD(pinctrl_list); 45static LIST_HEAD(pinctrl_list);
56 46
57/* List of pinctrl maps (struct pinctrl_maps) */ 47/* List of pinctrl maps (struct pinctrl_maps) */
58static LIST_HEAD(pinctrl_maps); 48LIST_HEAD(pinctrl_maps);
59 49
60#define for_each_maps(_maps_node_, _i_, _map_) \
61 list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
62 for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
63 _i_ < _maps_node_->num_maps; \
64 _i_++, _map_ = &_maps_node_->maps[_i_])
65 50
66/** 51/**
67 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support 52 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
@@ -83,6 +68,12 @@ const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
83} 68}
84EXPORT_SYMBOL_GPL(pinctrl_dev_get_name); 69EXPORT_SYMBOL_GPL(pinctrl_dev_get_name);
85 70
71const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev)
72{
73 return dev_name(pctldev->dev);
74}
75EXPORT_SYMBOL_GPL(pinctrl_dev_get_devname);
76
86void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev) 77void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev)
87{ 78{
88 return pctldev->driver_data; 79 return pctldev->driver_data;
@@ -609,13 +600,16 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
609 600
610 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); 601 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
611 if (setting->pctldev == NULL) { 602 if (setting->pctldev == NULL) {
612 dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
613 map->ctrl_dev_name);
614 kfree(setting); 603 kfree(setting);
604 /* Do not defer probing of hogs (circular loop) */
605 if (!strcmp(map->ctrl_dev_name, map->dev_name))
606 return -ENODEV;
615 /* 607 /*
616 * OK let us guess that the driver is not there yet, and 608 * OK let us guess that the driver is not there yet, and
617 * let's defer obtaining this pinctrl handle to later... 609 * let's defer obtaining this pinctrl handle to later...
618 */ 610 */
611 dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
612 map->ctrl_dev_name);
619 return -EPROBE_DEFER; 613 return -EPROBE_DEFER;
620 } 614 }
621 615
@@ -694,11 +688,31 @@ static struct pinctrl *create_pinctrl(struct device *dev)
694 continue; 688 continue;
695 689
696 ret = add_setting(p, map); 690 ret = add_setting(p, map);
697 if (ret < 0) { 691 /*
692 * At this point the adding of a setting may:
693 *
694 * - Defer, if the pinctrl device is not yet available
695 * - Fail, if the pinctrl device is not yet available,
696 * AND the setting is a hog. We cannot defer that, since
697 * the hog will kick in immediately after the device
698 * is registered.
699 *
700 * If the error returned was not -EPROBE_DEFER then we
701 * accumulate the errors to see if we end up with
702 * an -EPROBE_DEFER later, as that is the worst case.
703 */
704 if (ret == -EPROBE_DEFER) {
698 pinctrl_put_locked(p, false); 705 pinctrl_put_locked(p, false);
699 return ERR_PTR(ret); 706 return ERR_PTR(ret);
700 } 707 }
701 } 708 }
709 if (ret < 0) {
710 /* If some other error than deferral occured, return here */
711 pinctrl_put_locked(p, false);
712 return ERR_PTR(ret);
713 }
714
715 kref_init(&p->users);
702 716
703 /* Add the pinctrl handle to the global list */ 717 /* Add the pinctrl handle to the global list */
704 list_add_tail(&p->node, &pinctrl_list); 718 list_add_tail(&p->node, &pinctrl_list);
@@ -713,9 +727,17 @@ static struct pinctrl *pinctrl_get_locked(struct device *dev)
713 if (WARN_ON(!dev)) 727 if (WARN_ON(!dev))
714 return ERR_PTR(-EINVAL); 728 return ERR_PTR(-EINVAL);
715 729
730 /*
731 * See if somebody else (such as the device core) has already
732 * obtained a handle to the pinctrl for this device. In that case,
733 * return another pointer to it.
734 */
716 p = find_pinctrl(dev); 735 p = find_pinctrl(dev);
717 if (p != NULL) 736 if (p != NULL) {
718 return ERR_PTR(-EBUSY); 737 dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
738 kref_get(&p->users);
739 return p;
740 }
719 741
720 return create_pinctrl(dev); 742 return create_pinctrl(dev);
721} 743}
@@ -771,13 +793,24 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
771} 793}
772 794
773/** 795/**
774 * pinctrl_put() - release a previously claimed pinctrl handle 796 * pinctrl_release() - release the pinctrl handle
797 * @kref: the kref in the pinctrl being released
798 */
799static void pinctrl_release(struct kref *kref)
800{
801 struct pinctrl *p = container_of(kref, struct pinctrl, users);
802
803 pinctrl_put_locked(p, true);
804}
805
806/**
807 * pinctrl_put() - decrease use count on a previously claimed pinctrl handle
775 * @p: the pinctrl handle to release 808 * @p: the pinctrl handle to release
776 */ 809 */
777void pinctrl_put(struct pinctrl *p) 810void pinctrl_put(struct pinctrl *p)
778{ 811{
779 mutex_lock(&pinctrl_mutex); 812 mutex_lock(&pinctrl_mutex);
780 pinctrl_put_locked(p, true); 813 kref_put(&p->users, pinctrl_release);
781 mutex_unlock(&pinctrl_mutex); 814 mutex_unlock(&pinctrl_mutex);
782} 815}
783EXPORT_SYMBOL_GPL(pinctrl_put); 816EXPORT_SYMBOL_GPL(pinctrl_put);
@@ -1055,6 +1088,30 @@ void pinctrl_unregister_map(struct pinctrl_map const *map)
1055 } 1088 }
1056} 1089}
1057 1090
1091/**
1092 * pinctrl_force_sleep() - turn a given controller device into sleep state
1093 * @pctldev: pin controller device
1094 */
1095int pinctrl_force_sleep(struct pinctrl_dev *pctldev)
1096{
1097 if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_sleep))
1098 return pinctrl_select_state(pctldev->p, pctldev->hog_sleep);
1099 return 0;
1100}
1101EXPORT_SYMBOL_GPL(pinctrl_force_sleep);
1102
1103/**
1104 * pinctrl_force_default() - turn a given controller device into default state
1105 * @pctldev: pin controller device
1106 */
1107int pinctrl_force_default(struct pinctrl_dev *pctldev)
1108{
1109 if (!IS_ERR(pctldev->p) && !IS_ERR(pctldev->hog_default))
1110 return pinctrl_select_state(pctldev->p, pctldev->hog_default);
1111 return 0;
1112}
1113EXPORT_SYMBOL_GPL(pinctrl_force_default);
1114
1058#ifdef CONFIG_DEBUG_FS 1115#ifdef CONFIG_DEBUG_FS
1059 1116
1060static int pinctrl_pins_show(struct seq_file *s, void *what) 1117static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -1500,16 +1557,23 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1500 1557
1501 pctldev->p = pinctrl_get_locked(pctldev->dev); 1558 pctldev->p = pinctrl_get_locked(pctldev->dev);
1502 if (!IS_ERR(pctldev->p)) { 1559 if (!IS_ERR(pctldev->p)) {
1503 struct pinctrl_state *s = 1560 pctldev->hog_default =
1504 pinctrl_lookup_state_locked(pctldev->p, 1561 pinctrl_lookup_state_locked(pctldev->p,
1505 PINCTRL_STATE_DEFAULT); 1562 PINCTRL_STATE_DEFAULT);
1506 if (IS_ERR(s)) { 1563 if (IS_ERR(pctldev->hog_default)) {
1507 dev_dbg(dev, "failed to lookup the default state\n"); 1564 dev_dbg(dev, "failed to lookup the default state\n");
1508 } else { 1565 } else {
1509 if (pinctrl_select_state_locked(pctldev->p, s)) 1566 if (pinctrl_select_state_locked(pctldev->p,
1567 pctldev->hog_default))
1510 dev_err(dev, 1568 dev_err(dev,
1511 "failed to select default state\n"); 1569 "failed to select default state\n");
1512 } 1570 }
1571
1572 pctldev->hog_sleep =
1573 pinctrl_lookup_state_locked(pctldev->p,
1574 PINCTRL_STATE_SLEEP);
1575 if (IS_ERR(pctldev->hog_sleep))
1576 dev_dbg(dev, "failed to lookup the sleep state\n");
1513 } 1577 }
1514 1578
1515 mutex_unlock(&pinctrl_mutex); 1579 mutex_unlock(&pinctrl_mutex);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 12f5694f3d5d..ee72f1f6d862 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -9,6 +9,7 @@
9 * License terms: GNU General Public License (GPL) version 2 9 * License terms: GNU General Public License (GPL) version 2
10 */ 10 */
11 11
12#include <linux/kref.h>
12#include <linux/mutex.h> 13#include <linux/mutex.h>
13#include <linux/radix-tree.h> 14#include <linux/radix-tree.h>
14#include <linux/pinctrl/pinconf.h> 15#include <linux/pinctrl/pinconf.h>
@@ -30,6 +31,8 @@ struct pinctrl_gpio_range;
30 * @driver_data: driver data for drivers registering to the pin controller 31 * @driver_data: driver data for drivers registering to the pin controller
31 * subsystem 32 * subsystem
32 * @p: result of pinctrl_get() for this device 33 * @p: result of pinctrl_get() for this device
34 * @hog_default: default state for pins hogged by this device
35 * @hog_sleep: sleep state for pins hogged by this device
33 * @device_root: debugfs root for this device 36 * @device_root: debugfs root for this device
34 */ 37 */
35struct pinctrl_dev { 38struct pinctrl_dev {
@@ -41,6 +44,8 @@ struct pinctrl_dev {
41 struct module *owner; 44 struct module *owner;
42 void *driver_data; 45 void *driver_data;
43 struct pinctrl *p; 46 struct pinctrl *p;
47 struct pinctrl_state *hog_default;
48 struct pinctrl_state *hog_sleep;
44#ifdef CONFIG_DEBUG_FS 49#ifdef CONFIG_DEBUG_FS
45 struct dentry *device_root; 50 struct dentry *device_root;
46#endif 51#endif
@@ -54,6 +59,7 @@ struct pinctrl_dev {
54 * @state: the current state 59 * @state: the current state
55 * @dt_maps: the mapping table chunks dynamically parsed from device tree for 60 * @dt_maps: the mapping table chunks dynamically parsed from device tree for
56 * this device, if any 61 * this device, if any
62 * @users: reference count
57 */ 63 */
58struct pinctrl { 64struct pinctrl {
59 struct list_head node; 65 struct list_head node;
@@ -61,6 +67,7 @@ struct pinctrl {
61 struct list_head states; 67 struct list_head states;
62 struct pinctrl_state *state; 68 struct pinctrl_state *state;
63 struct list_head dt_maps; 69 struct list_head dt_maps;
70 struct kref users;
64}; 71};
65 72
66/** 73/**
@@ -148,6 +155,18 @@ struct pin_desc {
148#endif 155#endif
149}; 156};
150 157
158/**
159 * struct pinctrl_maps - a list item containing part of the mapping table
160 * @node: mapping table list node
161 * @maps: array of mapping table entries
162 * @num_maps: the number of entries in @maps
163 */
164struct pinctrl_maps {
165 struct list_head node;
166 struct pinctrl_map const *maps;
167 unsigned num_maps;
168};
169
151struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); 170struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
152int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); 171int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
153const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin); 172const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
@@ -164,5 +183,15 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
164 bool dup, bool locked); 183 bool dup, bool locked);
165void pinctrl_unregister_map(struct pinctrl_map const *map); 184void pinctrl_unregister_map(struct pinctrl_map const *map);
166 185
186extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
187extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
188
167extern struct mutex pinctrl_mutex; 189extern struct mutex pinctrl_mutex;
168extern struct list_head pinctrldev_list; 190extern struct list_head pinctrldev_list;
191extern struct list_head pinctrl_maps;
192
193#define for_each_maps(_maps_node_, _i_, _map_) \
194 list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
195 for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
196 _i_ < _maps_node_->num_maps; \
197 _i_++, _map_ = &_maps_node_->maps[_i_])
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index fe2d1af7cfa0..fd40a11ad645 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -141,6 +141,11 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
141 pctldev = find_pinctrl_by_of_node(np_pctldev); 141 pctldev = find_pinctrl_by_of_node(np_pctldev);
142 if (pctldev) 142 if (pctldev)
143 break; 143 break;
144 /* Do not defer probing of hogs (circular loop) */
145 if (np_pctldev == p->dev->of_node) {
146 of_node_put(np_pctldev);
147 return -ENODEV;
148 }
144 } 149 }
145 of_node_put(np_pctldev); 150 of_node_put(np_pctldev);
146 151
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 833a36458157..06c304ac6f7d 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -41,11 +41,13 @@ struct pin_config_item conf_items[] = {
41 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL), 41 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL),
42 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), 42 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
43 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), 43 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
44 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_DISABLE, "input schmitt disabled", NULL), 44 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL),
45 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL), 45 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
46 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"), 46 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "time units"),
47 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"), 47 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector"),
48 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL),
48 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"), 49 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode"),
50 PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level"),
49}; 51};
50 52
51void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, 53void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index baee2cc46a17..ac8d382a79bb 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -574,6 +574,207 @@ static const struct file_operations pinconf_groups_ops = {
574 .release = single_release, 574 .release = single_release,
575}; 575};
576 576
577/* 32bit read/write ressources */
578#define MAX_NAME_LEN 16
579char dbg_pinname[MAX_NAME_LEN]; /* shared: name of the state of the pin*/
580char dbg_state_name[MAX_NAME_LEN]; /* shared: state of the pin*/
581static u32 dbg_config; /* shared: config to be read/set for the pin & state*/
582
583static int pinconf_dbg_pinname_print(struct seq_file *s, void *d)
584{
585 if (strlen(dbg_pinname))
586 seq_printf(s, "%s\n", dbg_pinname);
587 else
588 seq_printf(s, "No pin name set\n");
589 return 0;
590}
591
592static int pinconf_dbg_pinname_open(struct inode *inode, struct file *file)
593{
594 return single_open(file, pinconf_dbg_pinname_print, inode->i_private);
595}
596
597static int pinconf_dbg_pinname_write(struct file *file,
598 const char __user *user_buf, size_t count, loff_t *ppos)
599{
600 int err;
601
602 if (count > MAX_NAME_LEN)
603 return -EINVAL;
604
605 err = sscanf(user_buf, "%15s", dbg_pinname);
606
607 if (err != 1)
608 return -EINVAL;
609
610 return count;
611}
612
613static const struct file_operations pinconf_dbg_pinname_fops = {
614 .open = pinconf_dbg_pinname_open,
615 .write = pinconf_dbg_pinname_write,
616 .read = seq_read,
617 .llseek = seq_lseek,
618 .release = single_release,
619 .owner = THIS_MODULE,
620};
621
622static int pinconf_dbg_state_print(struct seq_file *s, void *d)
623{
624 if (strlen(dbg_state_name))
625 seq_printf(s, "%s\n", dbg_pinname);
626 else
627 seq_printf(s, "No pin state set\n");
628 return 0;
629}
630
631static int pinconf_dbg_state_open(struct inode *inode, struct file *file)
632{
633 return single_open(file, pinconf_dbg_state_print, inode->i_private);
634}
635
636static int pinconf_dbg_state_write(struct file *file,
637 const char __user *user_buf, size_t count, loff_t *ppos)
638{
639 int err;
640
641 if (count > MAX_NAME_LEN)
642 return -EINVAL;
643
644 err = sscanf(user_buf, "%15s", dbg_state_name);
645
646 if (err != 1)
647 return -EINVAL;
648
649 return count;
650}
651
652static const struct file_operations pinconf_dbg_pinstate_fops = {
653 .open = pinconf_dbg_state_open,
654 .write = pinconf_dbg_state_write,
655 .read = seq_read,
656 .llseek = seq_lseek,
657 .release = single_release,
658 .owner = THIS_MODULE,
659};
660
661/**
662 * pinconf_dbg_config_print() - display the pinctrl config from the pinctrl
663 * map, of a pin/state pair based on pinname and state that have been
664 * selected with the debugfs entries pinconf-name and pinconf-state
665 * @s: contains the 32bits config to be written
666 * @d: not used
667 */
668static int pinconf_dbg_config_print(struct seq_file *s, void *d)
669{
670 struct pinctrl_maps *maps_node;
671 struct pinctrl_map const *map;
672 struct pinctrl_dev *pctldev = NULL;
673 struct pinconf_ops *confops = NULL;
674 int i, j;
675 bool found = false;
676
677 mutex_lock(&pinctrl_mutex);
678
679 /* Parse the pinctrl map and look for the elected pin/state */
680 for_each_maps(maps_node, i, map) {
681 if (map->type != PIN_MAP_TYPE_CONFIGS_PIN)
682 continue;
683
684 if (strncmp(map->name, dbg_state_name, MAX_NAME_LEN) > 0)
685 continue;
686
687 for (j = 0; j < map->data.configs.num_configs; j++) {
688 if (0 == strncmp(map->data.configs.group_or_pin,
689 dbg_pinname, MAX_NAME_LEN)) {
690 /* We found the right pin / state, read the
691 * config and store the pctldev */
692 dbg_config = map->data.configs.configs[j];
693 pctldev = get_pinctrl_dev_from_devname
694 (map->ctrl_dev_name);
695 found = true;
696 break;
697 }
698 }
699 }
700
701 mutex_unlock(&pinctrl_mutex);
702
703 if (found) {
704 seq_printf(s, "Config of %s in state %s: 0x%08X\n", dbg_pinname,
705 dbg_state_name, dbg_config);
706
707 if (pctldev)
708 confops = pctldev->desc->confops;
709
710 if (confops && confops->pin_config_config_dbg_show)
711 confops->pin_config_config_dbg_show(pctldev,
712 s, dbg_config);
713 } else {
714 seq_printf(s, "No pin found for defined name/state\n");
715 }
716
717 return 0;
718}
719
720static int pinconf_dbg_config_open(struct inode *inode, struct file *file)
721{
722 return single_open(file, pinconf_dbg_config_print, inode->i_private);
723}
724
725/**
726 * pinconf_dbg_config_write() - overwrite the pinctrl config in thepinctrl
727 * map, of a pin/state pair based on pinname and state that have been
728 * selected with the debugfs entries pinconf-name and pinconf-state
729 */
730static int pinconf_dbg_config_write(struct file *file,
731 const char __user *user_buf, size_t count, loff_t *ppos)
732{
733 int err;
734 unsigned long config;
735 struct pinctrl_maps *maps_node;
736 struct pinctrl_map const *map;
737 int i, j;
738
739 err = kstrtoul_from_user(user_buf, count, 0, &config);
740
741 if (err)
742 return err;
743
744 dbg_config = config;
745
746 mutex_lock(&pinctrl_mutex);
747
748 /* Parse the pinctrl map and look for the selected pin/state */
749 for_each_maps(maps_node, i, map) {
750 if (map->type != PIN_MAP_TYPE_CONFIGS_PIN)
751 continue;
752
753 if (strncmp(map->name, dbg_state_name, MAX_NAME_LEN) > 0)
754 continue;
755
756 /* we found the right pin / state, so overwrite config */
757 for (j = 0; j < map->data.configs.num_configs; j++) {
758 if (strncmp(map->data.configs.group_or_pin, dbg_pinname,
759 MAX_NAME_LEN) == 0)
760 map->data.configs.configs[j] = dbg_config;
761 }
762 }
763
764 mutex_unlock(&pinctrl_mutex);
765
766 return count;
767}
768
769static const struct file_operations pinconf_dbg_pinconfig_fops = {
770 .open = pinconf_dbg_config_open,
771 .write = pinconf_dbg_config_write,
772 .read = seq_read,
773 .llseek = seq_lseek,
774 .release = single_release,
775 .owner = THIS_MODULE,
776};
777
577void pinconf_init_device_debugfs(struct dentry *devroot, 778void pinconf_init_device_debugfs(struct dentry *devroot,
578 struct pinctrl_dev *pctldev) 779 struct pinctrl_dev *pctldev)
579{ 780{
@@ -581,6 +782,12 @@ void pinconf_init_device_debugfs(struct dentry *devroot,
581 devroot, pctldev, &pinconf_pins_ops); 782 devroot, pctldev, &pinconf_pins_ops);
582 debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO, 783 debugfs_create_file("pinconf-groups", S_IFREG | S_IRUGO,
583 devroot, pctldev, &pinconf_groups_ops); 784 devroot, pctldev, &pinconf_groups_ops);
785 debugfs_create_file("pinconf-name", (S_IRUGO | S_IWUSR | S_IWGRP),
786 devroot, pctldev, &pinconf_dbg_pinname_fops);
787 debugfs_create_file("pinconf-state", (S_IRUGO | S_IWUSR | S_IWGRP),
788 devroot, pctldev, &pinconf_dbg_pinstate_fops);
789 debugfs_create_file("pinconf-config", (S_IRUGO | S_IWUSR | S_IWGRP),
790 devroot, pctldev, &pinconf_dbg_pinconfig_fops);
584} 791}
585 792
586#endif 793#endif
diff --git a/drivers/pinctrl/pinctrl-ab8500.c b/drivers/pinctrl/pinctrl-ab8500.c
new file mode 100644
index 000000000000..3b471d87c211
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-ab8500.c
@@ -0,0 +1,484 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/mfd/abx500/ab8500.h>
15#include "pinctrl-abx500.h"
16
17/* All the pins that can be used for GPIO and some other functions */
18#define ABX500_GPIO(offset) (offset)
19
20#define AB8500_PIN_T10 ABX500_GPIO(1)
21#define AB8500_PIN_T9 ABX500_GPIO(2)
22#define AB8500_PIN_U9 ABX500_GPIO(3)
23#define AB8500_PIN_W2 ABX500_GPIO(4)
24/* hole */
25#define AB8500_PIN_Y18 ABX500_GPIO(6)
26#define AB8500_PIN_AA20 ABX500_GPIO(7)
27#define AB8500_PIN_W18 ABX500_GPIO(8)
28#define AB8500_PIN_AA19 ABX500_GPIO(9)
29#define AB8500_PIN_U17 ABX500_GPIO(10)
30#define AB8500_PIN_AA18 ABX500_GPIO(11)
31#define AB8500_PIN_U16 ABX500_GPIO(12)
32#define AB8500_PIN_W17 ABX500_GPIO(13)
33#define AB8500_PIN_F14 ABX500_GPIO(14)
34#define AB8500_PIN_B17 ABX500_GPIO(15)
35#define AB8500_PIN_F15 ABX500_GPIO(16)
36#define AB8500_PIN_P5 ABX500_GPIO(17)
37#define AB8500_PIN_R5 ABX500_GPIO(18)
38#define AB8500_PIN_U5 ABX500_GPIO(19)
39#define AB8500_PIN_T5 ABX500_GPIO(20)
40#define AB8500_PIN_H19 ABX500_GPIO(21)
41#define AB8500_PIN_G20 ABX500_GPIO(22)
42#define AB8500_PIN_G19 ABX500_GPIO(23)
43#define AB8500_PIN_T14 ABX500_GPIO(24)
44#define AB8500_PIN_R16 ABX500_GPIO(25)
45#define AB8500_PIN_M16 ABX500_GPIO(26)
46#define AB8500_PIN_J6 ABX500_GPIO(27)
47#define AB8500_PIN_K6 ABX500_GPIO(28)
48#define AB8500_PIN_G6 ABX500_GPIO(29)
49#define AB8500_PIN_H6 ABX500_GPIO(30)
50#define AB8500_PIN_F5 ABX500_GPIO(31)
51#define AB8500_PIN_G5 ABX500_GPIO(32)
52/* hole */
53#define AB8500_PIN_R17 ABX500_GPIO(34)
54#define AB8500_PIN_W15 ABX500_GPIO(35)
55#define AB8500_PIN_A17 ABX500_GPIO(36)
56#define AB8500_PIN_E15 ABX500_GPIO(37)
57#define AB8500_PIN_C17 ABX500_GPIO(38)
58#define AB8500_PIN_E16 ABX500_GPIO(39)
59#define AB8500_PIN_T19 ABX500_GPIO(40)
60#define AB8500_PIN_U19 ABX500_GPIO(41)
61#define AB8500_PIN_U2 ABX500_GPIO(42)
62
63/* indicates the highest GPIO number */
64#define AB8500_GPIO_MAX_NUMBER 42
65
66/*
67 * The names of the pins are denoted by GPIO number and ball name, even
68 * though they can be used for other things than GPIO, this is the first
69 * column in the table of the data sheet and often used on schematics and
70 * such.
71 */
72static const struct pinctrl_pin_desc ab8500_pins[] = {
73 PINCTRL_PIN(AB8500_PIN_T10, "GPIO1_T10"),
74 PINCTRL_PIN(AB8500_PIN_T9, "GPIO2_T9"),
75 PINCTRL_PIN(AB8500_PIN_U9, "GPIO3_U9"),
76 PINCTRL_PIN(AB8500_PIN_W2, "GPIO4_W2"),
77 /* hole */
78 PINCTRL_PIN(AB8500_PIN_Y18, "GPIO6_Y18"),
79 PINCTRL_PIN(AB8500_PIN_AA20, "GPIO7_AA20"),
80 PINCTRL_PIN(AB8500_PIN_W18, "GPIO8_W18"),
81 PINCTRL_PIN(AB8500_PIN_AA19, "GPIO9_AA19"),
82 PINCTRL_PIN(AB8500_PIN_U17, "GPIO10_U17"),
83 PINCTRL_PIN(AB8500_PIN_AA18, "GPIO11_AA18"),
84 PINCTRL_PIN(AB8500_PIN_U16, "GPIO12_U16"),
85 PINCTRL_PIN(AB8500_PIN_W17, "GPIO13_W17"),
86 PINCTRL_PIN(AB8500_PIN_F14, "GPIO14_F14"),
87 PINCTRL_PIN(AB8500_PIN_B17, "GPIO15_B17"),
88 PINCTRL_PIN(AB8500_PIN_F15, "GPIO16_F15"),
89 PINCTRL_PIN(AB8500_PIN_P5, "GPIO17_P5"),
90 PINCTRL_PIN(AB8500_PIN_R5, "GPIO18_R5"),
91 PINCTRL_PIN(AB8500_PIN_U5, "GPIO19_U5"),
92 PINCTRL_PIN(AB8500_PIN_T5, "GPIO20_T5"),
93 PINCTRL_PIN(AB8500_PIN_H19, "GPIO21_H19"),
94 PINCTRL_PIN(AB8500_PIN_G20, "GPIO22_G20"),
95 PINCTRL_PIN(AB8500_PIN_G19, "GPIO23_G19"),
96 PINCTRL_PIN(AB8500_PIN_T14, "GPIO24_T14"),
97 PINCTRL_PIN(AB8500_PIN_R16, "GPIO25_R16"),
98 PINCTRL_PIN(AB8500_PIN_M16, "GPIO26_M16"),
99 PINCTRL_PIN(AB8500_PIN_J6, "GPIO27_J6"),
100 PINCTRL_PIN(AB8500_PIN_K6, "GPIO28_K6"),
101 PINCTRL_PIN(AB8500_PIN_G6, "GPIO29_G6"),
102 PINCTRL_PIN(AB8500_PIN_H6, "GPIO30_H6"),
103 PINCTRL_PIN(AB8500_PIN_F5, "GPIO31_F5"),
104 PINCTRL_PIN(AB8500_PIN_G5, "GPIO32_G5"),
105 /* hole */
106 PINCTRL_PIN(AB8500_PIN_R17, "GPIO34_R17"),
107 PINCTRL_PIN(AB8500_PIN_W15, "GPIO35_W15"),
108 PINCTRL_PIN(AB8500_PIN_A17, "GPIO36_A17"),
109 PINCTRL_PIN(AB8500_PIN_E15, "GPIO37_E15"),
110 PINCTRL_PIN(AB8500_PIN_C17, "GPIO38_C17"),
111 PINCTRL_PIN(AB8500_PIN_E16, "GPIO39_E16"),
112 PINCTRL_PIN(AB8500_PIN_T19, "GPIO40_T19"),
113 PINCTRL_PIN(AB8500_PIN_U19, "GPIO41_U19"),
114 PINCTRL_PIN(AB8500_PIN_U2, "GPIO42_U2"),
115};
116
117/*
118 * Maps local GPIO offsets to local pin numbers
119 */
120static const struct abx500_pinrange ab8500_pinranges[] = {
121 ABX500_PINRANGE(1, 4, ABX500_ALT_A),
122 ABX500_PINRANGE(6, 4, ABX500_ALT_A),
123 ABX500_PINRANGE(10, 4, ABX500_DEFAULT),
124 ABX500_PINRANGE(14, 12, ABX500_ALT_A),
125 ABX500_PINRANGE(26, 1, ABX500_DEFAULT),
126 ABX500_PINRANGE(27, 6, ABX500_ALT_A),
127 ABX500_PINRANGE(34, 1, ABX500_ALT_A),
128 ABX500_PINRANGE(35, 1, ABX500_DEFAULT),
129 ABX500_PINRANGE(36, 7, ABX500_ALT_A),
130};
131
132/*
133 * Read the pin group names like this:
134 * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
135 *
136 * The groups are arranged as sets per altfunction column, so we can
137 * mux in one group at a time by selecting the same altfunction for them
138 * all. When functions require pins on different altfunctions, you need
139 * to combine several groups.
140 */
141
142/* default column */
143static const unsigned sysclkreq2_d_1_pins[] = { AB8500_PIN_T10 };
144static const unsigned sysclkreq3_d_1_pins[] = { AB8500_PIN_T9 };
145static const unsigned sysclkreq4_d_1_pins[] = { AB8500_PIN_U9 };
146static const unsigned sysclkreq6_d_1_pins[] = { AB8500_PIN_W2 };
147static const unsigned ycbcr0123_d_1_pins[] = { AB8500_PIN_Y18, AB8500_PIN_AA20,
148 AB8500_PIN_W18, AB8500_PIN_AA19};
149static const unsigned gpio10_d_1_pins[] = { AB8500_PIN_U17 };
150static const unsigned gpio11_d_1_pins[] = { AB8500_PIN_AA18 };
151static const unsigned gpio12_d_1_pins[] = { AB8500_PIN_U16 };
152static const unsigned gpio13_d_1_pins[] = { AB8500_PIN_W17 };
153static const unsigned pwmout1_d_1_pins[] = { AB8500_PIN_F14 };
154static const unsigned pwmout2_d_1_pins[] = { AB8500_PIN_B17 };
155static const unsigned pwmout3_d_1_pins[] = { AB8500_PIN_F15 };
156
157/* audio data interface 1*/
158static const unsigned adi1_d_1_pins[] = { AB8500_PIN_P5, AB8500_PIN_R5,
159 AB8500_PIN_U5, AB8500_PIN_T5 };
160/* USBUICC */
161static const unsigned usbuicc_d_1_pins[] = { AB8500_PIN_H19, AB8500_PIN_G20,
162 AB8500_PIN_G19 };
163static const unsigned sysclkreq7_d_1_pins[] = { AB8500_PIN_T14 };
164static const unsigned sysclkreq8_d_1_pins[] = { AB8500_PIN_R16 };
165static const unsigned gpio26_d_1_pins[] = { AB8500_PIN_M16 };
166/* Digital microphone 1 and 2 */
167static const unsigned dmic12_d_1_pins[] = { AB8500_PIN_J6, AB8500_PIN_K6 };
168/* Digital microphone 3 and 4 */
169static const unsigned dmic34_d_1_pins[] = { AB8500_PIN_G6, AB8500_PIN_H6 };
170/* Digital microphone 5 and 6 */
171static const unsigned dmic56_d_1_pins[] = { AB8500_PIN_F5, AB8500_PIN_G5 };
172static const unsigned extcpena_d_1_pins[] = { AB8500_PIN_R17 };
173static const unsigned gpio35_d_1_pins[] = { AB8500_PIN_W15 };
174/* APE SPI */
175static const unsigned apespi_d_1_pins[] = { AB8500_PIN_A17, AB8500_PIN_E15,
176 AB8500_PIN_C17, AB8500_PIN_E16};
177/* modem SDA/SCL */
178static const unsigned modsclsda_d_1_pins[] = { AB8500_PIN_T19, AB8500_PIN_U19 };
179static const unsigned sysclkreq5_d_1_pins[] = { AB8500_PIN_U2 };
180
181/* Altfunction A column */
182static const unsigned gpio1_a_1_pins[] = { AB8500_PIN_T10 };
183static const unsigned gpio2_a_1_pins[] = { AB8500_PIN_T9 };
184static const unsigned gpio3_a_1_pins[] = { AB8500_PIN_U9 };
185static const unsigned gpio4_a_1_pins[] = { AB8500_PIN_W2 };
186static const unsigned gpio6_a_1_pins[] = { AB8500_PIN_Y18 };
187static const unsigned gpio7_a_1_pins[] = { AB8500_PIN_AA20 };
188static const unsigned gpio8_a_1_pins[] = { AB8500_PIN_W18 };
189static const unsigned gpio9_a_1_pins[] = { AB8500_PIN_AA19 };
190/* YCbCr4 YCbCr5 YCbCr6 YCbCr7*/
191static const unsigned ycbcr4567_a_1_pins[] = { AB8500_PIN_U17, AB8500_PIN_AA18,
192 AB8500_PIN_U16, AB8500_PIN_W17};
193static const unsigned gpio14_a_1_pins[] = { AB8500_PIN_F14 };
194static const unsigned gpio15_a_1_pins[] = { AB8500_PIN_B17 };
195static const unsigned gpio16_a_1_pins[] = { AB8500_PIN_F15 };
196static const unsigned gpio17_a_1_pins[] = { AB8500_PIN_P5 };
197static const unsigned gpio18_a_1_pins[] = { AB8500_PIN_R5 };
198static const unsigned gpio19_a_1_pins[] = { AB8500_PIN_U5 };
199static const unsigned gpio20_a_1_pins[] = { AB8500_PIN_T5 };
200static const unsigned gpio21_a_1_pins[] = { AB8500_PIN_H19 };
201static const unsigned gpio22_a_1_pins[] = { AB8500_PIN_G20 };
202static const unsigned gpio23_a_1_pins[] = { AB8500_PIN_G19 };
203static const unsigned gpio24_a_1_pins[] = { AB8500_PIN_T14 };
204static const unsigned gpio25_a_1_pins[] = { AB8500_PIN_R16 };
205static const unsigned gpio27_a_1_pins[] = { AB8500_PIN_J6 };
206static const unsigned gpio28_a_1_pins[] = { AB8500_PIN_K6 };
207static const unsigned gpio29_a_1_pins[] = { AB8500_PIN_G6 };
208static const unsigned gpio30_a_1_pins[] = { AB8500_PIN_H6 };
209static const unsigned gpio31_a_1_pins[] = { AB8500_PIN_F5 };
210static const unsigned gpio32_a_1_pins[] = { AB8500_PIN_G5 };
211static const unsigned gpio34_a_1_pins[] = { AB8500_PIN_R17 };
212static const unsigned gpio36_a_1_pins[] = { AB8500_PIN_A17 };
213static const unsigned gpio37_a_1_pins[] = { AB8500_PIN_E15 };
214static const unsigned gpio38_a_1_pins[] = { AB8500_PIN_C17 };
215static const unsigned gpio39_a_1_pins[] = { AB8500_PIN_E16 };
216static const unsigned gpio40_a_1_pins[] = { AB8500_PIN_T19 };
217static const unsigned gpio41_a_1_pins[] = { AB8500_PIN_U19 };
218static const unsigned gpio42_a_1_pins[] = { AB8500_PIN_U2 };
219
220/* Altfunction B colum */
221static const unsigned hiqclkena_b_1_pins[] = { AB8500_PIN_U17 };
222static const unsigned usbuiccpd_b_1_pins[] = { AB8500_PIN_AA18 };
223static const unsigned i2ctrig1_b_1_pins[] = { AB8500_PIN_U16 };
224static const unsigned i2ctrig2_b_1_pins[] = { AB8500_PIN_W17 };
225
226/* Altfunction C column */
227static const unsigned usbvdat_c_1_pins[] = { AB8500_PIN_W17 };
228
229
230#define AB8500_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
231 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
232
233static const struct abx500_pingroup ab8500_groups[] = {
234 /* default column */
235 AB8500_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
236 AB8500_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
237 AB8500_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
238 AB8500_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
239 AB8500_PIN_GROUP(ycbcr0123_d_1, ABX500_DEFAULT),
240 AB8500_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
241 AB8500_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
242 AB8500_PIN_GROUP(gpio12_d_1, ABX500_DEFAULT),
243 AB8500_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
244 AB8500_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
245 AB8500_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
246 AB8500_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
247 AB8500_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
248 AB8500_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
249 AB8500_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
250 AB8500_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
251 AB8500_PIN_GROUP(gpio26_d_1, ABX500_DEFAULT),
252 AB8500_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
253 AB8500_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
254 AB8500_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
255 AB8500_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
256 AB8500_PIN_GROUP(gpio35_d_1, ABX500_DEFAULT),
257 AB8500_PIN_GROUP(apespi_d_1, ABX500_DEFAULT),
258 AB8500_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
259 AB8500_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
260 /* Altfunction A column */
261 AB8500_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
262 AB8500_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
263 AB8500_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
264 AB8500_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
265 AB8500_PIN_GROUP(gpio6_a_1, ABX500_ALT_A),
266 AB8500_PIN_GROUP(gpio7_a_1, ABX500_ALT_A),
267 AB8500_PIN_GROUP(gpio8_a_1, ABX500_ALT_A),
268 AB8500_PIN_GROUP(gpio9_a_1, ABX500_ALT_A),
269 AB8500_PIN_GROUP(ycbcr4567_a_1, ABX500_ALT_A),
270 AB8500_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
271 AB8500_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
272 AB8500_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
273 AB8500_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
274 AB8500_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
275 AB8500_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
276 AB8500_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
277 AB8500_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
278 AB8500_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
279 AB8500_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
280 AB8500_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
281 AB8500_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
282 AB8500_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
283 AB8500_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
284 AB8500_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
285 AB8500_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
286 AB8500_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
287 AB8500_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
288 AB8500_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
289 AB8500_PIN_GROUP(gpio36_a_1, ABX500_ALT_A),
290 AB8500_PIN_GROUP(gpio37_a_1, ABX500_ALT_A),
291 AB8500_PIN_GROUP(gpio38_a_1, ABX500_ALT_A),
292 AB8500_PIN_GROUP(gpio39_a_1, ABX500_ALT_A),
293 AB8500_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
294 AB8500_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
295 AB8500_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
296 /* Altfunction B column */
297 AB8500_PIN_GROUP(hiqclkena_b_1, ABX500_ALT_B),
298 AB8500_PIN_GROUP(usbuiccpd_b_1, ABX500_ALT_B),
299 AB8500_PIN_GROUP(i2ctrig1_b_1, ABX500_ALT_B),
300 AB8500_PIN_GROUP(i2ctrig2_b_1, ABX500_ALT_B),
301 /* Altfunction C column */
302 AB8500_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
303};
304
305/* We use this macro to define the groups applicable to a function */
306#define AB8500_FUNC_GROUPS(a, b...) \
307static const char * const a##_groups[] = { b };
308
309AB8500_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
310 "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
311 "sysclkreq7_d_1", "sysclkreq8_d_1");
312AB8500_FUNC_GROUPS(ycbcr, "ycbcr0123_d_1", "ycbcr4567_a_1");
313AB8500_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
314 "gpio6_a_1", "gpio7_a_1", "gpio8_a_1", "gpio9_a_1",
315 "gpio10_d_1", "gpio11_d_1", "gpio12_d_1", "gpio13_d_1",
316 "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
317 "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio21_a_1",
318 "gpio22_a_1", "gpio23_a_1", "gpio24_a_1", "gpio25_a_1",
319 "gpio26_d_1", "gpio27_a_1", "gpio28_a_1", "gpio29_a_1",
320 "gpio30_a_1", "gpio31_a_1", "gpio32_a_1", "gpio34_a_1",
321 "gpio35_d_1", "gpio36_a_1", "gpio37_a_1", "gpio38_a_1",
322 "gpio39_a_1", "gpio40_a_1", "gpio41_a_1", "gpio42_a_1");
323AB8500_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
324AB8500_FUNC_GROUPS(adi1, "adi1_d_1");
325AB8500_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_b_1");
326AB8500_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
327AB8500_FUNC_GROUPS(extcpena, "extcpena_d_1");
328AB8500_FUNC_GROUPS(apespi, "apespi_d_1");
329AB8500_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
330AB8500_FUNC_GROUPS(hiqclkena, "hiqclkena_b_1");
331AB8500_FUNC_GROUPS(i2ctrig, "i2ctrig1_b_1", "i2ctrig2_b_1");
332AB8500_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
333
334#define FUNCTION(fname) \
335 { \
336 .name = #fname, \
337 .groups = fname##_groups, \
338 .ngroups = ARRAY_SIZE(fname##_groups), \
339 }
340
341static const struct abx500_function ab8500_functions[] = {
342 FUNCTION(sysclkreq),
343 FUNCTION(ycbcr),
344 FUNCTION(gpio),
345 FUNCTION(pwmout),
346 FUNCTION(adi1),
347 FUNCTION(usbuicc),
348 FUNCTION(dmic),
349 FUNCTION(extcpena),
350 FUNCTION(apespi),
351 FUNCTION(modsclsda),
352 FUNCTION(hiqclkena),
353 FUNCTION(i2ctrig),
354 FUNCTION(usbvdat),
355};
356
357/*
358 * this table translates what's is in the AB8500 specification regarding the
359 * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
360 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
361 * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
362 *
363 * example :
364 *
365 * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1 ,2),
366 * means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A,
367 * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
368 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
369 * ALTERNATFUNC register. We need to specifies these values as SOC
370 * designers didn't apply the same logic on how to select mux in the
371 * ABx500 family.
372 *
373 * As this pins supports at least ALT_B mux, default mux is
374 * selected by writing 1 in GPIOSEL bit :
375 *
376 * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
377 * default | 1 | 0 | 0
378 * alt_A | 0 | 0 | 0
379 * alt_B | 0 | 0 | 1
380 * alt_C | 0 | 1 | 0
381 *
382 * ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED),
383 * means that pin AB8500_PIN_W18 (pin 8) supports 2 mux, so only GPIOSEL
384 * register is used to select the mux. As this pins doesn't support at
385 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
386 *
387 * | GPIOSEL bit=7 | alternatfunc bit2= | alternatfunc bit1=
388 * default | 0 | 0 | 0
389 * alt_A | 1 | 0 | 0
390 */
391
392struct alternate_functions ab8500_alternate_functions[AB8500_GPIO_MAX_NUMBER + 1] = {
393 ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
394 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
395 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
396 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
397 ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
398 /* bit 4 reserved */
399 ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
400 ALTERNATE_FUNCTIONS(6, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO6, altA controlled by bit 5*/
401 ALTERNATE_FUNCTIONS(7, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO7, altA controlled by bit 6*/
402 ALTERNATE_FUNCTIONS(8, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO8, altA controlled by bit 7*/
403
404 ALTERNATE_FUNCTIONS(9, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO9, altA controlled by bit 0*/
405 ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 0, 1, 0), /* GPIO10, altA and altB controlled by bit 0 */
406 ALTERNATE_FUNCTIONS(11, 2, 1, UNUSED, 0, 1, 0), /* GPIO11, altA and altB controlled by bit 1 */
407 ALTERNATE_FUNCTIONS(12, 3, 2, UNUSED, 0, 1, 0), /* GPIO12, altA and altB controlled by bit 2 */
408 ALTERNATE_FUNCTIONS(13, 4, 3, 4, 0, 1, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
409 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
410 ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
411 ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
412 /*
413 * pins 17 to 20 are special case, only bit 0 is used to select
414 * alternate function for these 4 pins.
415 * bits 1 to 3 are reserved
416 */
417 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
418 ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
419 ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
420 ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
421 ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
422 ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
423 ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
424 ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
425
426 ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
427 /* pin 26 special case, no alternate function, bit 1 reserved */
428 ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO26 */
429 ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
430 ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
431 ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
432 ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
433 ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
434 ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
435
436 ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
437 ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
438 /* pin 35 special case, no alternate function, bit 2 reserved */
439 ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* GPIO35 */
440 ALTERNATE_FUNCTIONS(36, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO36, altA controlled by bit 3 */
441 ALTERNATE_FUNCTIONS(37, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO37, altA controlled by bit 4 */
442 ALTERNATE_FUNCTIONS(38, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO38, altA controlled by bit 5 */
443 ALTERNATE_FUNCTIONS(39, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO39, altA controlled by bit 6 */
444 ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
445
446 ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
447 ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
448};
449
450/*
451 * Only some GPIOs are interrupt capable, and they are
452 * organized in discontiguous clusters:
453 *
454 * GPIO6 to GPIO13
455 * GPIO24 and GPIO25
456 * GPIO36 to GPIO41
457 */
458struct abx500_gpio_irq_cluster ab8500_gpio_irq_cluster[] = {
459 GPIO_IRQ_CLUSTER(6, 13, AB8500_INT_GPIO6R),
460 GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
461 GPIO_IRQ_CLUSTER(36, 41, AB8500_INT_GPIO36R),
462};
463
464static struct abx500_pinctrl_soc_data ab8500_soc = {
465 .gpio_ranges = ab8500_pinranges,
466 .gpio_num_ranges = ARRAY_SIZE(ab8500_pinranges),
467 .pins = ab8500_pins,
468 .npins = ARRAY_SIZE(ab8500_pins),
469 .functions = ab8500_functions,
470 .nfunctions = ARRAY_SIZE(ab8500_functions),
471 .groups = ab8500_groups,
472 .ngroups = ARRAY_SIZE(ab8500_groups),
473 .alternate_functions = ab8500_alternate_functions,
474 .gpio_irq_cluster = ab8500_gpio_irq_cluster,
475 .ngpio_irq_cluster = ARRAY_SIZE(ab8500_gpio_irq_cluster),
476 .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
477 .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
478 .irq_gpio_factor = 1,
479};
480
481void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
482{
483 *soc = &ab8500_soc;
484}
diff --git a/drivers/pinctrl/pinctrl-ab8505.c b/drivers/pinctrl/pinctrl-ab8505.c
new file mode 100644
index 000000000000..3a4238e879e3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-ab8505.c
@@ -0,0 +1,380 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/mfd/abx500/ab8500.h>
15#include "pinctrl-abx500.h"
16
17/* All the pins that can be used for GPIO and some other functions */
18#define ABX500_GPIO(offset) (offset)
19
20#define AB8505_PIN_N4 ABX500_GPIO(1)
21#define AB8505_PIN_R5 ABX500_GPIO(2)
22#define AB8505_PIN_P5 ABX500_GPIO(3)
23/* hole */
24#define AB8505_PIN_B16 ABX500_GPIO(10)
25#define AB8505_PIN_B17 ABX500_GPIO(11)
26/* hole */
27#define AB8505_PIN_D17 ABX500_GPIO(13)
28#define AB8505_PIN_C16 ABX500_GPIO(14)
29/* hole */
30#define AB8505_PIN_P2 ABX500_GPIO(17)
31#define AB8505_PIN_N3 ABX500_GPIO(18)
32#define AB8505_PIN_T1 ABX500_GPIO(19)
33#define AB8505_PIN_P3 ABX500_GPIO(20)
34/* hole */
35#define AB8505_PIN_H14 ABX500_GPIO(34)
36/* hole */
37#define AB8505_PIN_J15 ABX500_GPIO(40)
38#define AB8505_PIN_J14 ABX500_GPIO(41)
39/* hole */
40#define AB8505_PIN_L4 ABX500_GPIO(50)
41/* hole */
42#define AB8505_PIN_D16 ABX500_GPIO(52)
43#define AB8505_PIN_D15 ABX500_GPIO(53)
44
45/* indicates the higher GPIO number */
46#define AB8505_GPIO_MAX_NUMBER 53
47
48/*
49 * The names of the pins are denoted by GPIO number and ball name, even
50 * though they can be used for other things than GPIO, this is the first
51 * column in the table of the data sheet and often used on schematics and
52 * such.
53 */
54static const struct pinctrl_pin_desc ab8505_pins[] = {
55 PINCTRL_PIN(AB8505_PIN_N4, "GPIO1_N4"),
56 PINCTRL_PIN(AB8505_PIN_R5, "GPIO2_R5"),
57 PINCTRL_PIN(AB8505_PIN_P5, "GPIO3_P5"),
58/* hole */
59 PINCTRL_PIN(AB8505_PIN_B16, "GPIO10_B16"),
60 PINCTRL_PIN(AB8505_PIN_B17, "GPIO11_B17"),
61/* hole */
62 PINCTRL_PIN(AB8505_PIN_D17, "GPIO13_D17"),
63 PINCTRL_PIN(AB8505_PIN_C16, "GPIO14_C16"),
64/* hole */
65 PINCTRL_PIN(AB8505_PIN_P2, "GPIO17_P2"),
66 PINCTRL_PIN(AB8505_PIN_N3, "GPIO18_N3"),
67 PINCTRL_PIN(AB8505_PIN_T1, "GPIO19_T1"),
68 PINCTRL_PIN(AB8505_PIN_P3, "GPIO20_P3"),
69/* hole */
70 PINCTRL_PIN(AB8505_PIN_H14, "GPIO34_H14"),
71/* hole */
72 PINCTRL_PIN(AB8505_PIN_J15, "GPIO40_J15"),
73 PINCTRL_PIN(AB8505_PIN_J14, "GPIO41_J14"),
74/* hole */
75 PINCTRL_PIN(AB8505_PIN_L4, "GPIO50_L4"),
76/* hole */
77 PINCTRL_PIN(AB8505_PIN_D16, "GPIO52_D16"),
78 PINCTRL_PIN(AB8505_PIN_D15, "GPIO53_D15"),
79};
80
81/*
82 * Maps local GPIO offsets to local pin numbers
83 */
84static const struct abx500_pinrange ab8505_pinranges[] = {
85 ABX500_PINRANGE(1, 3, ABX500_ALT_A),
86 ABX500_PINRANGE(10, 2, ABX500_DEFAULT),
87 ABX500_PINRANGE(13, 1, ABX500_DEFAULT),
88 ABX500_PINRANGE(14, 1, ABX500_ALT_A),
89 ABX500_PINRANGE(17, 4, ABX500_ALT_A),
90 ABX500_PINRANGE(34, 1, ABX500_ALT_A),
91 ABX500_PINRANGE(40, 2, ABX500_ALT_A),
92 ABX500_PINRANGE(50, 1, ABX500_DEFAULT),
93 ABX500_PINRANGE(52, 2, ABX500_ALT_A),
94};
95
96/*
97 * Read the pin group names like this:
98 * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
99 *
100 * The groups are arranged as sets per altfunction column, so we can
101 * mux in one group at a time by selecting the same altfunction for them
102 * all. When functions require pins on different altfunctions, you need
103 * to combine several groups.
104 */
105
106/* default column */
107static const unsigned sysclkreq2_d_1_pins[] = { AB8505_PIN_N4 };
108static const unsigned sysclkreq3_d_1_pins[] = { AB8505_PIN_R5 };
109static const unsigned sysclkreq4_d_1_pins[] = { AB8505_PIN_P5 };
110static const unsigned gpio10_d_1_pins[] = { AB8505_PIN_B16 };
111static const unsigned gpio11_d_1_pins[] = { AB8505_PIN_B17 };
112static const unsigned gpio13_d_1_pins[] = { AB8505_PIN_D17 };
113static const unsigned pwmout1_d_1_pins[] = { AB8505_PIN_C16 };
114/* audio data interface 2*/
115static const unsigned adi2_d_1_pins[] = { AB8505_PIN_P2, AB8505_PIN_N3,
116 AB8505_PIN_T1, AB8505_PIN_P3 };
117static const unsigned extcpena_d_1_pins[] = { AB8505_PIN_H14 };
118/* modem SDA/SCL */
119static const unsigned modsclsda_d_1_pins[] = { AB8505_PIN_J15, AB8505_PIN_J14 };
120static const unsigned gpio50_d_1_pins[] = { AB8505_PIN_L4 };
121static const unsigned resethw_d_1_pins[] = { AB8505_PIN_D16 };
122static const unsigned service_d_1_pins[] = { AB8505_PIN_D15 };
123
124/* Altfunction A column */
125static const unsigned gpio1_a_1_pins[] = { AB8505_PIN_N4 };
126static const unsigned gpio2_a_1_pins[] = { AB8505_PIN_R5 };
127static const unsigned gpio3_a_1_pins[] = { AB8505_PIN_P5 };
128static const unsigned hiqclkena_a_1_pins[] = { AB8505_PIN_B16 };
129static const unsigned pdmclk_a_1_pins[] = { AB8505_PIN_B17 };
130static const unsigned uarttxdata_a_1_pins[] = { AB8505_PIN_D17 };
131static const unsigned gpio14_a_1_pins[] = { AB8505_PIN_C16 };
132static const unsigned gpio17_a_1_pins[] = { AB8505_PIN_P2 };
133static const unsigned gpio18_a_1_pins[] = { AB8505_PIN_N3 };
134static const unsigned gpio19_a_1_pins[] = { AB8505_PIN_T1 };
135static const unsigned gpio20_a_1_pins[] = { AB8505_PIN_P3 };
136static const unsigned gpio34_a_1_pins[] = { AB8505_PIN_H14 };
137static const unsigned gpio40_a_1_pins[] = { AB8505_PIN_J15 };
138static const unsigned gpio41_a_1_pins[] = { AB8505_PIN_J14 };
139static const unsigned uartrxdata_a_1_pins[] = { AB8505_PIN_J14 };
140static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 };
141static const unsigned gpio52_a_1_pins[] = { AB8505_PIN_D16 };
142static const unsigned gpio53_a_1_pins[] = { AB8505_PIN_D15 };
143
144/* Altfunction B colum */
145static const unsigned pdmdata_b_1_pins[] = { AB8505_PIN_B16 };
146static const unsigned extvibrapwm1_b_1_pins[] = { AB8505_PIN_D17 };
147static const unsigned extvibrapwm2_b_1_pins[] = { AB8505_PIN_L4 };
148
149/* Altfunction C column */
150static const unsigned usbvdat_c_1_pins[] = { AB8505_PIN_D17 };
151
152#define AB8505_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
153 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
154
155static const struct abx500_pingroup ab8505_groups[] = {
156 AB8505_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
157 AB8505_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
158 AB8505_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
159 AB8505_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
160 AB8505_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
161 AB8505_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
162 AB8505_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
163 AB8505_PIN_GROUP(adi2_d_1, ABX500_DEFAULT),
164 AB8505_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
165 AB8505_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
166 AB8505_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT),
167 AB8505_PIN_GROUP(resethw_d_1, ABX500_DEFAULT),
168 AB8505_PIN_GROUP(service_d_1, ABX500_DEFAULT),
169 AB8505_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
170 AB8505_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
171 AB8505_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
172 AB8505_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A),
173 AB8505_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A),
174 AB8505_PIN_GROUP(uarttxdata_a_1, ABX500_ALT_A),
175 AB8505_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
176 AB8505_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
177 AB8505_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
178 AB8505_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
179 AB8505_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
180 AB8505_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
181 AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
182 AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
183 AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A),
184 AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
185 AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
186 AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B),
187 AB8505_PIN_GROUP(extvibrapwm1_b_1, ABX500_ALT_B),
188 AB8505_PIN_GROUP(extvibrapwm2_b_1, ABX500_ALT_B),
189 AB8505_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
190};
191
192/* We use this macro to define the groups applicable to a function */
193#define AB8505_FUNC_GROUPS(a, b...) \
194static const char * const a##_groups[] = { b };
195
196AB8505_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
197 "sysclkreq4_d_1");
198AB8505_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1",
199 "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1",
200 "gpio17_a_1", "gpio18_a_1", "gpio19_a_1", "gpio20_a_1",
201 "gpio34_a_1", "gpio40_a_1", "gpio41_a_1", "gpio50_d_1",
202 "gpio52_a_1", "gpio53_a_1");
203AB8505_FUNC_GROUPS(pwmout, "pwmout1_d_1");
204AB8505_FUNC_GROUPS(adi2, "adi2_d_1");
205AB8505_FUNC_GROUPS(extcpena, "extcpena_d_1");
206AB8505_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
207AB8505_FUNC_GROUPS(resethw, "resethw_d_1");
208AB8505_FUNC_GROUPS(service, "service_d_1");
209AB8505_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1");
210AB8505_FUNC_GROUPS(pdm, "pdmclk_a_1", "pdmdata_b_1");
211AB8505_FUNC_GROUPS(uartdata, "uarttxdata_a_1", "uartrxdata_a_1");
212AB8505_FUNC_GROUPS(extvibra, "extvibrapwm1_b_1", "extvibrapwm2_b_1");
213AB8505_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
214
215#define FUNCTION(fname) \
216 { \
217 .name = #fname, \
218 .groups = fname##_groups, \
219 .ngroups = ARRAY_SIZE(fname##_groups), \
220 }
221
222static const struct abx500_function ab8505_functions[] = {
223 FUNCTION(sysclkreq),
224 FUNCTION(gpio),
225 FUNCTION(pwmout),
226 FUNCTION(adi2),
227 FUNCTION(extcpena),
228 FUNCTION(modsclsda),
229 FUNCTION(resethw),
230 FUNCTION(service),
231 FUNCTION(hiqclkena),
232 FUNCTION(pdm),
233 FUNCTION(uartdata),
234 FUNCTION(extvibra),
235 FUNCTION(extvibra),
236 FUNCTION(usbvdat),
237};
238
239/*
240 * this table translates what's is in the AB8505 specification regarding the
241 * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
242 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
243 * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
244 *
245 * example :
246 *
247 * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2),
248 * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
249 * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
250 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
251 * ALTERNATFUNC register. We need to specifies these values as SOC
252 * designers didn't apply the same logic on how to select mux in the
253 * ABx500 family.
254 *
255 * As this pins supports at least ALT_B mux, default mux is
256 * selected by writing 1 in GPIOSEL bit :
257 *
258 * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
259 * default | 1 | 0 | 0
260 * alt_A | 0 | 0 | 1
261 * alt_B | 0 | 0 | 0
262 * alt_C | 0 | 1 | 0
263 *
264 * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED),
265 * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
266 * register is used to select the mux. As this pins doesn't support at
267 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
268 *
269 * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1=
270 * default | 0 | 0 | 0
271 * alt_A | 1 | 0 | 0
272 */
273
274struct alternate_functions ab8505_alternate_functions[AB8505_GPIO_MAX_NUMBER + 1] = {
275 ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
276 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
277 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
278 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
279 ALTERNATE_FUNCTIONS(4, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO4, bit 3 reserved */
280 ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5, bit 4 reserved */
281 ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6, bit 5 reserved */
282 ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7, bit 6 reserved */
283 ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8, bit 7 reserved */
284
285 ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9, bit 0 reserved */
286 ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
287 ALTERNATE_FUNCTIONS(11, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 2 */
288 ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12, bit3 reseved */
289 ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
290 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
291 ALTERNATE_FUNCTIONS(15, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 6 reserved */
292 ALTERNATE_FUNCTIONS(16, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO15, bit 7 reserved */
293 /*
294 * pins 17 to 20 are special case, only bit 0 is used to select
295 * alternate function for these 4 pins.
296 * bits 1 to 3 are reserved
297 */
298 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
299 ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
300 ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
301 ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
302 ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21, bit 4 reserved */
303 ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22, bit 5 reserved */
304 ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23, bit 6 reserved */
305 ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24, bit 7 reserved */
306
307 ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25, bit 0 reserved */
308 ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26, bit 1 reserved */
309 ALTERNATE_FUNCTIONS(27, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO27, bit 2 reserved */
310 ALTERNATE_FUNCTIONS(28, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO28, bit 3 reserved */
311 ALTERNATE_FUNCTIONS(29, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO29, bit 4 reserved */
312 ALTERNATE_FUNCTIONS(30, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO30, bit 5 reserved */
313 ALTERNATE_FUNCTIONS(31, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO31, bit 6 reserved */
314 ALTERNATE_FUNCTIONS(32, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO32, bit 7 reserved */
315
316 ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33, bit 0 reserved */
317 ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
318 ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35, bit 2 reserved */
319 ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36, bit 2 reserved */
320 ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37, bit 2 reserved */
321 ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38, bit 2 reserved */
322 ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39, bit 2 reserved */
323 ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7*/
324
325 ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
326 ALTERNATE_FUNCTIONS(42, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO42, bit 1 reserved */
327 ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43, bit 2 reserved */
328 ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44, bit 3 reserved */
329 ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45, bit 4 reserved */
330 ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46, bit 5 reserved */
331 ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47, bit 6 reserved */
332 ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48, bit 7 reserved */
333
334 ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */
335 ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA controlled by bit 1 */
336 ALTERNATE_FUNCTIONS(51, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49, bit 0 reserved */
337 ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
338 ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
339};
340
341/*
342 * For AB8505 Only some GPIOs are interrupt capable, and they are
343 * organized in discontiguous clusters:
344 *
345 * GPIO10 to GPIO11
346 * GPIO13
347 * GPIO40 and GPIO41
348 * GPIO50
349 * GPIO52 to GPIO53
350 */
351struct abx500_gpio_irq_cluster ab8505_gpio_irq_cluster[] = {
352 GPIO_IRQ_CLUSTER(10, 11, AB8500_INT_GPIO10R),
353 GPIO_IRQ_CLUSTER(13, 13, AB8500_INT_GPIO13R),
354 GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R),
355 GPIO_IRQ_CLUSTER(50, 50, AB9540_INT_GPIO50R),
356 GPIO_IRQ_CLUSTER(52, 53, AB9540_INT_GPIO52R),
357};
358
359static struct abx500_pinctrl_soc_data ab8505_soc = {
360 .gpio_ranges = ab8505_pinranges,
361 .gpio_num_ranges = ARRAY_SIZE(ab8505_pinranges),
362 .pins = ab8505_pins,
363 .npins = ARRAY_SIZE(ab8505_pins),
364 .functions = ab8505_functions,
365 .nfunctions = ARRAY_SIZE(ab8505_functions),
366 .groups = ab8505_groups,
367 .ngroups = ARRAY_SIZE(ab8505_groups),
368 .alternate_functions = ab8505_alternate_functions,
369 .gpio_irq_cluster = ab8505_gpio_irq_cluster,
370 .ngpio_irq_cluster = ARRAY_SIZE(ab8505_gpio_irq_cluster),
371 .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
372 .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
373 .irq_gpio_factor = 1,
374};
375
376void
377abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
378{
379 *soc = &ab8505_soc;
380}
diff --git a/drivers/pinctrl/pinctrl-ab8540.c b/drivers/pinctrl/pinctrl-ab8540.c
new file mode 100644
index 000000000000..8ee1e8d95f65
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-ab8540.c
@@ -0,0 +1,407 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/mfd/abx500/ab8500.h>
15#include "pinctrl-abx500.h"
16
17/* All the pins that can be used for GPIO and some other functions */
18#define ABX500_GPIO(offset) (offset)
19
20#define AB8540_PIN_J16 ABX500_GPIO(1)
21#define AB8540_PIN_D17 ABX500_GPIO(2)
22#define AB8540_PIN_C12 ABX500_GPIO(3)
23#define AB8540_PIN_G12 ABX500_GPIO(4)
24/* hole */
25#define AB8540_PIN_D16 ABX500_GPIO(14)
26#define AB8540_PIN_F15 ABX500_GPIO(15)
27#define AB8540_PIN_J8 ABX500_GPIO(16)
28#define AB8540_PIN_K16 ABX500_GPIO(17)
29#define AB8540_PIN_G15 ABX500_GPIO(18)
30#define AB8540_PIN_F17 ABX500_GPIO(19)
31#define AB8540_PIN_E17 ABX500_GPIO(20)
32/* hole */
33#define AB8540_PIN_AA16 ABX500_GPIO(27)
34#define AB8540_PIN_W18 ABX500_GPIO(28)
35#define AB8540_PIN_Y15 ABX500_GPIO(29)
36#define AB8540_PIN_W16 ABX500_GPIO(30)
37#define AB8540_PIN_V15 ABX500_GPIO(31)
38#define AB8540_PIN_W17 ABX500_GPIO(32)
39/* hole */
40#define AB8540_PIN_D12 ABX500_GPIO(42)
41#define AB8540_PIN_P4 ABX500_GPIO(43)
42#define AB8540_PIN_AB1 ABX500_GPIO(44)
43#define AB8540_PIN_K7 ABX500_GPIO(45)
44#define AB8540_PIN_L7 ABX500_GPIO(46)
45#define AB8540_PIN_G10 ABX500_GPIO(47)
46#define AB8540_PIN_K12 ABX500_GPIO(48)
47/* hole */
48#define AB8540_PIN_N8 ABX500_GPIO(51)
49#define AB8540_PIN_P12 ABX500_GPIO(52)
50#define AB8540_PIN_K8 ABX500_GPIO(53)
51#define AB8540_PIN_J11 ABX500_GPIO(54)
52#define AB8540_PIN_AC2 ABX500_GPIO(55)
53#define AB8540_PIN_AB2 ABX500_GPIO(56)
54
55/* indicates the highest GPIO number */
56#define AB8540_GPIO_MAX_NUMBER 56
57
58/*
59 * The names of the pins are denoted by GPIO number and ball name, even
60 * though they can be used for other things than GPIO, this is the first
61 * column in the table of the data sheet and often used on schematics and
62 * such.
63 */
64static const struct pinctrl_pin_desc ab8540_pins[] = {
65 PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"),
66 PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"),
67 PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"),
68 PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"),
69 /* hole */
70 PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"),
71 PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"),
72 PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"),
73 PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"),
74 PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"),
75 PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"),
76 PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"),
77 /* hole */
78 PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"),
79 PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"),
80 PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"),
81 PINCTRL_PIN(AB8540_PIN_W16, "GPIO30_W16"),
82 PINCTRL_PIN(AB8540_PIN_V15, "GPIO31_V15"),
83 PINCTRL_PIN(AB8540_PIN_W17, "GPIO32_W17"),
84 /* hole */
85 PINCTRL_PIN(AB8540_PIN_D12, "GPIO42_D12"),
86 PINCTRL_PIN(AB8540_PIN_P4, "GPIO43_P4"),
87 PINCTRL_PIN(AB8540_PIN_AB1, "GPIO44_AB1"),
88 PINCTRL_PIN(AB8540_PIN_K7, "GPIO45_K7"),
89 PINCTRL_PIN(AB8540_PIN_L7, "GPIO46_L7"),
90 PINCTRL_PIN(AB8540_PIN_G10, "GPIO47_G10"),
91 PINCTRL_PIN(AB8540_PIN_K12, "GPIO48_K12"),
92 /* hole */
93 PINCTRL_PIN(AB8540_PIN_N8, "GPIO51_N8"),
94 PINCTRL_PIN(AB8540_PIN_P12, "GPIO52_P12"),
95 PINCTRL_PIN(AB8540_PIN_K8, "GPIO53_K8"),
96 PINCTRL_PIN(AB8540_PIN_J11, "GPIO54_J11"),
97 PINCTRL_PIN(AB8540_PIN_AC2, "GPIO55_AC2"),
98 PINCTRL_PIN(AB8540_PIN_AB2, "GPIO56_AB2"),
99};
100
101/*
102 * Maps local GPIO offsets to local pin numbers
103 */
104static const struct abx500_pinrange ab8540_pinranges[] = {
105 ABX500_PINRANGE(1, 4, ABX500_ALT_A),
106 ABX500_PINRANGE(14, 7, ABX500_ALT_A),
107 ABX500_PINRANGE(27, 6, ABX500_ALT_A),
108 ABX500_PINRANGE(42, 7, ABX500_ALT_A),
109 ABX500_PINRANGE(51, 6, ABX500_ALT_A),
110};
111
112/*
113 * Read the pin group names like this:
114 * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
115 *
116 * The groups are arranged as sets per altfunction column, so we can
117 * mux in one group at a time by selecting the same altfunction for them
118 * all. When functions require pins on different altfunctions, you need
119 * to combine several groups.
120 */
121
122/* default column */
123static const unsigned sysclkreq2_d_1_pins[] = { AB8540_PIN_J16 };
124static const unsigned sysclkreq3_d_1_pins[] = { AB8540_PIN_D17 };
125static const unsigned sysclkreq4_d_1_pins[] = { AB8540_PIN_C12 };
126static const unsigned sysclkreq6_d_1_pins[] = { AB8540_PIN_G12 };
127static const unsigned pwmout1_d_1_pins[] = { AB8540_PIN_D16 };
128static const unsigned pwmout2_d_1_pins[] = { AB8540_PIN_F15 };
129static const unsigned pwmout3_d_1_pins[] = { AB8540_PIN_J8 };
130
131/* audio data interface 1*/
132static const unsigned adi1_d_1_pins[] = { AB8540_PIN_K16, AB8540_PIN_G15,
133 AB8540_PIN_F17, AB8540_PIN_E17 };
134/* Digital microphone 1 and 2 */
135static const unsigned dmic12_d_1_pins[] = { AB8540_PIN_AA16, AB8540_PIN_W18 };
136/* Digital microphone 3 and 4 */
137static const unsigned dmic34_d_1_pins[] = { AB8540_PIN_Y15, AB8540_PIN_W16 };
138/* Digital microphone 5 and 6 */
139static const unsigned dmic56_d_1_pins[] = { AB8540_PIN_V15, AB8540_PIN_W17 };
140static const unsigned sysclkreq5_d_1_pins[] = { AB8540_PIN_D12 };
141static const unsigned batremn_d_1_pins[] = { AB8540_PIN_P4 };
142static const unsigned service_d_1_pins[] = { AB8540_PIN_AB1 };
143static const unsigned pwrctrl0_d_1_pins[] = { AB8540_PIN_K7 };
144static const unsigned pwrctrl1_d_1_pins[] = { AB8540_PIN_L7 };
145static const unsigned pwmextvibra1_d_1_pins[] = { AB8540_PIN_G10 };
146static const unsigned pwmextvibra2_d_1_pins[] = { AB8540_PIN_K12 };
147static const unsigned gpio1_vbat_d_1_pins[] = { AB8540_PIN_N8 };
148static const unsigned gpio2_vbat_d_1_pins[] = { AB8540_PIN_P12 };
149static const unsigned gpio3_vbat_d_1_pins[] = { AB8540_PIN_K8 };
150static const unsigned gpio4_vbat_d_1_pins[] = { AB8540_PIN_J11 };
151static const unsigned pdmclkdat_d_1_pins[] = { AB8540_PIN_AC2, AB8540_PIN_AB2 };
152
153/* Altfunction A column */
154static const unsigned gpio1_a_1_pins[] = { AB8540_PIN_J16 };
155static const unsigned gpio2_a_1_pins[] = { AB8540_PIN_D17 };
156static const unsigned gpio3_a_1_pins[] = { AB8540_PIN_C12 };
157static const unsigned gpio4_a_1_pins[] = { AB8540_PIN_G12 };
158static const unsigned gpio14_a_1_pins[] = { AB8540_PIN_D16 };
159static const unsigned gpio15_a_1_pins[] = { AB8540_PIN_F15 };
160static const unsigned gpio16_a_1_pins[] = { AB8540_PIN_J8 };
161static const unsigned gpio17_a_1_pins[] = { AB8540_PIN_K16 };
162static const unsigned gpio18_a_1_pins[] = { AB8540_PIN_G15 };
163static const unsigned gpio19_a_1_pins[] = { AB8540_PIN_F17 };
164static const unsigned gpio20_a_1_pins[] = { AB8540_PIN_E17 };
165static const unsigned gpio27_a_1_pins[] = { AB8540_PIN_AA16 };
166static const unsigned gpio28_a_1_pins[] = { AB8540_PIN_W18 };
167static const unsigned gpio29_a_1_pins[] = { AB8540_PIN_Y15 };
168static const unsigned gpio30_a_1_pins[] = { AB8540_PIN_W16 };
169static const unsigned gpio31_a_1_pins[] = { AB8540_PIN_V15 };
170static const unsigned gpio32_a_1_pins[] = { AB8540_PIN_W17 };
171static const unsigned gpio42_a_1_pins[] = { AB8540_PIN_D12 };
172static const unsigned gpio43_a_1_pins[] = { AB8540_PIN_P4 };
173static const unsigned gpio44_a_1_pins[] = { AB8540_PIN_AB1 };
174static const unsigned gpio45_a_1_pins[] = { AB8540_PIN_K7 };
175static const unsigned gpio46_a_1_pins[] = { AB8540_PIN_L7 };
176static const unsigned gpio47_a_1_pins[] = { AB8540_PIN_G10 };
177static const unsigned gpio48_a_1_pins[] = { AB8540_PIN_K12 };
178static const unsigned gpio51_a_1_pins[] = { AB8540_PIN_N8 };
179static const unsigned gpio52_a_1_pins[] = { AB8540_PIN_P12 };
180static const unsigned gpio53_a_1_pins[] = { AB8540_PIN_K8 };
181static const unsigned gpio54_a_1_pins[] = { AB8540_PIN_J11 };
182static const unsigned gpio55_a_1_pins[] = { AB8540_PIN_AC2 };
183static const unsigned gpio56_a_1_pins[] = { AB8540_PIN_AB2 };
184
185#define AB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
186 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
187
188static const struct abx500_pingroup ab8540_groups[] = {
189 /* default column */
190 AB8540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
191 AB8540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
192 AB8540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
193 AB8540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
194 AB8540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
195 AB8540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
196 AB8540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
197 AB8540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
198 AB8540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
199 AB8540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
200 AB8540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
201 AB8540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
202 AB8540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
203 AB8540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
204 AB8540_PIN_GROUP(pwrctrl0_d_1, ABX500_DEFAULT),
205 AB8540_PIN_GROUP(pwrctrl1_d_1, ABX500_DEFAULT),
206 AB8540_PIN_GROUP(pwmextvibra1_d_1, ABX500_DEFAULT),
207 AB8540_PIN_GROUP(pwmextvibra2_d_1, ABX500_DEFAULT),
208 AB8540_PIN_GROUP(gpio1_vbat_d_1, ABX500_DEFAULT),
209 AB8540_PIN_GROUP(gpio2_vbat_d_1, ABX500_DEFAULT),
210 AB8540_PIN_GROUP(gpio3_vbat_d_1, ABX500_DEFAULT),
211 AB8540_PIN_GROUP(gpio4_vbat_d_1, ABX500_DEFAULT),
212 AB8540_PIN_GROUP(pdmclkdat_d_1, ABX500_DEFAULT),
213 /* Altfunction A column */
214 AB8540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
215 AB8540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
216 AB8540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
217 AB8540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
218 AB8540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
219 AB8540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
220 AB8540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
221 AB8540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
222 AB8540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
223 AB8540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
224 AB8540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
225 AB8540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
226 AB8540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
227 AB8540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
228 AB8540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
229 AB8540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
230 AB8540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
231 AB8540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
232 AB8540_PIN_GROUP(gpio43_a_1, ABX500_ALT_A),
233 AB8540_PIN_GROUP(gpio44_a_1, ABX500_ALT_A),
234 AB8540_PIN_GROUP(gpio45_a_1, ABX500_ALT_A),
235 AB8540_PIN_GROUP(gpio46_a_1, ABX500_ALT_A),
236 AB8540_PIN_GROUP(gpio47_a_1, ABX500_ALT_A),
237 AB8540_PIN_GROUP(gpio48_a_1, ABX500_ALT_A),
238 AB8540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
239 AB8540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
240 AB8540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
241 AB8540_PIN_GROUP(gpio54_a_1, ABX500_ALT_A),
242 AB8540_PIN_GROUP(gpio55_a_1, ABX500_ALT_A),
243 AB8540_PIN_GROUP(gpio56_a_1, ABX500_ALT_A),
244};
245
246/* We use this macro to define the groups applicable to a function */
247#define AB8540_FUNC_GROUPS(a, b...) \
248static const char * const a##_groups[] = { b };
249
250AB8540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
251 "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1");
252AB8540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
253 "gpio14_a_1", "gpio15_a_1", "gpio16_a_1", "gpio17_a_1",
254 "gpio18_a_1", "gpio19_a_1", "gpio20_a_1", "gpio27_a_1",
255 "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
256 "gpio32_a_1", "gpio42_a_1", "gpio43_a_1", "gpio44_a_1",
257 "gpio45_a_1", "gpio46_a_1", "gpio47_a_1", "gpio48_a_1",
258 "gpio51_a_1", "gpio52_a_1", "gpio53_a_1", "gpio54_a_1",
259 "gpio55_a_1", "gpio56_a_1");
260AB8540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
261AB8540_FUNC_GROUPS(adi1, "adi1_d_1");
262AB8540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
263AB8540_FUNC_GROUPS(batremn, "batremn_d_1");
264AB8540_FUNC_GROUPS(service, "service_d_1");
265AB8540_FUNC_GROUPS(pwrctrl, "pwrctrl0_d_1", "pwrctrl1_d_1");
266AB8540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_d_1", "pwmextvibra2_d_1");
267AB8540_FUNC_GROUPS(gpio_vbat, "gpio1_vbat_d_1", "gpio2_vbat_d_1",
268 "gpio3_vbat_d_1", "gpio4_vbat_d_1");
269AB8540_FUNC_GROUPS(pdm, "pdmclkdat_d_1");
270
271#define FUNCTION(fname) \
272 { \
273 .name = #fname, \
274 .groups = fname##_groups, \
275 .ngroups = ARRAY_SIZE(fname##_groups), \
276 }
277
278static const struct abx500_function ab8540_functions[] = {
279 FUNCTION(sysclkreq),
280 FUNCTION(gpio),
281 FUNCTION(pwmout),
282 FUNCTION(adi1),
283 FUNCTION(dmic),
284 FUNCTION(batremn),
285 FUNCTION(service),
286 FUNCTION(pwrctrl),
287 FUNCTION(pwmextvibra),
288 FUNCTION(gpio_vbat),
289 FUNCTION(pdm),
290};
291
292/*
293 * this table translates what's is in the AB8540 specification regarding the
294 * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
295 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
296 * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
297 * AB8540 only supports DEFAULT and ALTA functions, so ALTERNATFUNC
298 * registers is not used
299 *
300 */
301
302struct alternate_functions ab8540_alternate_functions[AB8540_GPIO_MAX_NUMBER + 1] = {
303 /* GPIOSEL1 - bit 4-7 reserved */
304 ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
305 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
306 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
307 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
308 ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
309 ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
310 ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
311 ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
312 ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
313 /* GPIOSEL2 - bit 0-4 reserved */
314 ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
315 ALTERNATE_FUNCTIONS(10, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO10 */
316 ALTERNATE_FUNCTIONS(11, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO11 */
317 ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
318 ALTERNATE_FUNCTIONS(13, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO13 */
319 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
320 ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
321 ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
322 /* GPIOSEL3 - bit 4-7 reserved */
323 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
324 ALTERNATE_FUNCTIONS(18, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 1 */
325 ALTERNATE_FUNCTIONS(19, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 2 */
326 ALTERNATE_FUNCTIONS(20, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 3 */
327 ALTERNATE_FUNCTIONS(21, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO21 */
328 ALTERNATE_FUNCTIONS(22, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO22 */
329 ALTERNATE_FUNCTIONS(23, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO23 */
330 ALTERNATE_FUNCTIONS(24, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO24 */
331 /* GPIOSEL4 - bit 0-1 reserved */
332 ALTERNATE_FUNCTIONS(25, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO25 */
333 ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
334 ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
335 ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
336 ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
337 ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
338 ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
339 ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
340 /* GPIOSEL5 - bit 0-7 reserved */
341 ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
342 ALTERNATE_FUNCTIONS(34, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO34 */
343 ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
344 ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
345 ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
346 ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
347 ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
348 ALTERNATE_FUNCTIONS(40, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO40 */
349 /* GPIOSEL6 - bit 0 reserved */
350 ALTERNATE_FUNCTIONS(41, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO41 */
351 ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
352 ALTERNATE_FUNCTIONS(43, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO43, altA controlled by bit 2 */
353 ALTERNATE_FUNCTIONS(44, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO44, altA controlled by bit 3 */
354 ALTERNATE_FUNCTIONS(45, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO45, altA controlled by bit 4 */
355 ALTERNATE_FUNCTIONS(46, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO46, altA controlled by bit 5 */
356 ALTERNATE_FUNCTIONS(47, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO47, altA controlled by bit 6 */
357 ALTERNATE_FUNCTIONS(48, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO48, altA controlled by bit 7 */
358 /* GPIOSEL7 - bit 0-1 reserved */
359 ALTERNATE_FUNCTIONS(49, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
360 ALTERNATE_FUNCTIONS(50, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO50 */
361 ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
362 ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
363 ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
364 ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54, altA controlled by bit 5 */
365 ALTERNATE_FUNCTIONS(55, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO55, altA controlled by bit 6 */
366 ALTERNATE_FUNCTIONS(56, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO56, altA controlled by bit 7 */
367};
368
369static struct pullud ab8540_pullud = {
370 .first_pin = 51, /* GPIO1_VBAT */
371 .last_pin = 54, /* GPIO4_VBAT */
372};
373
374/*
375 * For AB8540 Only some GPIOs are interrupt capable:
376 * GPIO43 to GPIO44
377 * GPIO51 to GPIO54
378 */
379struct abx500_gpio_irq_cluster ab8540_gpio_irq_cluster[] = {
380 GPIO_IRQ_CLUSTER(43, 43, AB8540_INT_GPIO43F),
381 GPIO_IRQ_CLUSTER(44, 44, AB8540_INT_GPIO44F),
382 GPIO_IRQ_CLUSTER(51, 54, AB9540_INT_GPIO51R),
383};
384
385static struct abx500_pinctrl_soc_data ab8540_soc = {
386 .gpio_ranges = ab8540_pinranges,
387 .gpio_num_ranges = ARRAY_SIZE(ab8540_pinranges),
388 .pins = ab8540_pins,
389 .npins = ARRAY_SIZE(ab8540_pins),
390 .functions = ab8540_functions,
391 .nfunctions = ARRAY_SIZE(ab8540_functions),
392 .groups = ab8540_groups,
393 .ngroups = ARRAY_SIZE(ab8540_groups),
394 .alternate_functions = ab8540_alternate_functions,
395 .pullud = &ab8540_pullud,
396 .gpio_irq_cluster = ab8540_gpio_irq_cluster,
397 .ngpio_irq_cluster = ARRAY_SIZE(ab8540_gpio_irq_cluster),
398 .irq_gpio_rising_offset = AB8540_INT_GPIO43R,
399 .irq_gpio_falling_offset = AB8540_INT_GPIO43F,
400 .irq_gpio_factor = 2,
401};
402
403void
404abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
405{
406 *soc = &ab8540_soc;
407}
diff --git a/drivers/pinctrl/pinctrl-ab9540.c b/drivers/pinctrl/pinctrl-ab9540.c
new file mode 100644
index 000000000000..7610bd012b98
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-ab9540.c
@@ -0,0 +1,485 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/pinctrl/pinctrl.h>
14#include <linux/mfd/abx500/ab8500.h>
15#include "pinctrl-abx500.h"
16
17/* All the pins that can be used for GPIO and some other functions */
18#define ABX500_GPIO(offset) (offset)
19
20#define AB9540_PIN_R4 ABX500_GPIO(1)
21#define AB9540_PIN_V3 ABX500_GPIO(2)
22#define AB9540_PIN_T4 ABX500_GPIO(3)
23#define AB9540_PIN_T5 ABX500_GPIO(4)
24/* hole */
25#define AB9540_PIN_B18 ABX500_GPIO(10)
26#define AB9540_PIN_C18 ABX500_GPIO(11)
27/* hole */
28#define AB9540_PIN_D18 ABX500_GPIO(13)
29#define AB9540_PIN_B19 ABX500_GPIO(14)
30#define AB9540_PIN_C19 ABX500_GPIO(15)
31#define AB9540_PIN_D19 ABX500_GPIO(16)
32#define AB9540_PIN_R3 ABX500_GPIO(17)
33#define AB9540_PIN_T2 ABX500_GPIO(18)
34#define AB9540_PIN_U2 ABX500_GPIO(19)
35#define AB9540_PIN_V2 ABX500_GPIO(20)
36#define AB9540_PIN_N17 ABX500_GPIO(21)
37#define AB9540_PIN_N16 ABX500_GPIO(22)
38#define AB9540_PIN_M19 ABX500_GPIO(23)
39#define AB9540_PIN_T3 ABX500_GPIO(24)
40#define AB9540_PIN_W2 ABX500_GPIO(25)
41/* hole */
42#define AB9540_PIN_H4 ABX500_GPIO(27)
43#define AB9540_PIN_F1 ABX500_GPIO(28)
44#define AB9540_PIN_F4 ABX500_GPIO(29)
45#define AB9540_PIN_F2 ABX500_GPIO(30)
46#define AB9540_PIN_E4 ABX500_GPIO(31)
47#define AB9540_PIN_F3 ABX500_GPIO(32)
48/* hole */
49#define AB9540_PIN_J13 ABX500_GPIO(34)
50/* hole */
51#define AB9540_PIN_L17 ABX500_GPIO(40)
52#define AB9540_PIN_L16 ABX500_GPIO(41)
53#define AB9540_PIN_W3 ABX500_GPIO(42)
54#define AB9540_PIN_N4 ABX500_GPIO(50)
55#define AB9540_PIN_G12 ABX500_GPIO(51)
56#define AB9540_PIN_E17 ABX500_GPIO(52)
57#define AB9540_PIN_D11 ABX500_GPIO(53)
58#define AB9540_PIN_M18 ABX500_GPIO(54)
59
60/* indicates the highest GPIO number */
61#define AB9540_GPIO_MAX_NUMBER 54
62
63/*
64 * The names of the pins are denoted by GPIO number and ball name, even
65 * though they can be used for other things than GPIO, this is the first
66 * column in the table of the data sheet and often used on schematics and
67 * such.
68 */
69static const struct pinctrl_pin_desc ab9540_pins[] = {
70 PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"),
71 PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"),
72 PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"),
73 PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"),
74 /* hole */
75 PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"),
76 PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"),
77 /* hole */
78 PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"),
79 PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"),
80 PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"),
81 PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"),
82 PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"),
83 PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"),
84 PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"),
85 PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"),
86 PINCTRL_PIN(AB9540_PIN_N17, "GPIO21_N17"),
87 PINCTRL_PIN(AB9540_PIN_N16, "GPIO22_N16"),
88 PINCTRL_PIN(AB9540_PIN_M19, "GPIO23_M19"),
89 PINCTRL_PIN(AB9540_PIN_T3, "GPIO24_T3"),
90 PINCTRL_PIN(AB9540_PIN_W2, "GPIO25_W2"),
91 /* hole */
92 PINCTRL_PIN(AB9540_PIN_H4, "GPIO27_H4"),
93 PINCTRL_PIN(AB9540_PIN_F1, "GPIO28_F1"),
94 PINCTRL_PIN(AB9540_PIN_F4, "GPIO29_F4"),
95 PINCTRL_PIN(AB9540_PIN_F2, "GPIO30_F2"),
96 PINCTRL_PIN(AB9540_PIN_E4, "GPIO31_E4"),
97 PINCTRL_PIN(AB9540_PIN_F3, "GPIO32_F3"),
98 /* hole */
99 PINCTRL_PIN(AB9540_PIN_J13, "GPIO34_J13"),
100 /* hole */
101 PINCTRL_PIN(AB9540_PIN_L17, "GPIO40_L17"),
102 PINCTRL_PIN(AB9540_PIN_L16, "GPIO41_L16"),
103 PINCTRL_PIN(AB9540_PIN_W3, "GPIO42_W3"),
104 PINCTRL_PIN(AB9540_PIN_N4, "GPIO50_N4"),
105 PINCTRL_PIN(AB9540_PIN_G12, "GPIO51_G12"),
106 PINCTRL_PIN(AB9540_PIN_E17, "GPIO52_E17"),
107 PINCTRL_PIN(AB9540_PIN_D11, "GPIO53_D11"),
108 PINCTRL_PIN(AB9540_PIN_M18, "GPIO60_M18"),
109};
110
111/*
112 * Maps local GPIO offsets to local pin numbers
113 */
114static const struct abx500_pinrange ab9540_pinranges[] = {
115 ABX500_PINRANGE(1, 4, ABX500_ALT_A),
116 ABX500_PINRANGE(10, 2, ABX500_DEFAULT),
117 ABX500_PINRANGE(13, 1, ABX500_DEFAULT),
118 ABX500_PINRANGE(14, 12, ABX500_ALT_A),
119 ABX500_PINRANGE(27, 6, ABX500_ALT_A),
120 ABX500_PINRANGE(34, 1, ABX500_ALT_A),
121 ABX500_PINRANGE(40, 3, ABX500_ALT_A),
122 ABX500_PINRANGE(50, 1, ABX500_DEFAULT),
123 ABX500_PINRANGE(51, 3, ABX500_ALT_A),
124 ABX500_PINRANGE(54, 1, ABX500_DEFAULT),
125};
126
127/*
128 * Read the pin group names like this:
129 * sysclkreq2_d_1 = first groups of pins for sysclkreq2 on default function
130 *
131 * The groups are arranged as sets per altfunction column, so we can
132 * mux in one group at a time by selecting the same altfunction for them
133 * all. When functions require pins on different altfunctions, you need
134 * to combine several groups.
135 */
136
137/* default column */
138static const unsigned sysclkreq2_d_1_pins[] = { AB9540_PIN_R4 };
139static const unsigned sysclkreq3_d_1_pins[] = { AB9540_PIN_V3 };
140static const unsigned sysclkreq4_d_1_pins[] = { AB9540_PIN_T4 };
141static const unsigned sysclkreq6_d_1_pins[] = { AB9540_PIN_T5 };
142static const unsigned gpio10_d_1_pins[] = { AB9540_PIN_B18 };
143static const unsigned gpio11_d_1_pins[] = { AB9540_PIN_C18 };
144static const unsigned gpio13_d_1_pins[] = { AB9540_PIN_D18 };
145static const unsigned pwmout1_d_1_pins[] = { AB9540_PIN_B19 };
146static const unsigned pwmout2_d_1_pins[] = { AB9540_PIN_C19 };
147static const unsigned pwmout3_d_1_pins[] = { AB9540_PIN_D19 };
148/* audio data interface 1*/
149static const unsigned adi1_d_1_pins[] = { AB9540_PIN_R3, AB9540_PIN_T2,
150 AB9540_PIN_U2, AB9540_PIN_V2 };
151/* USBUICC */
152static const unsigned usbuicc_d_1_pins[] = { AB9540_PIN_N17, AB9540_PIN_N16,
153 AB9540_PIN_M19 };
154static const unsigned sysclkreq7_d_1_pins[] = { AB9540_PIN_T3 };
155static const unsigned sysclkreq8_d_1_pins[] = { AB9540_PIN_W2 };
156/* Digital microphone 1 and 2 */
157static const unsigned dmic12_d_1_pins[] = { AB9540_PIN_H4, AB9540_PIN_F1 };
158/* Digital microphone 3 and 4 */
159static const unsigned dmic34_d_1_pins[] = { AB9540_PIN_F4, AB9540_PIN_F2 };
160/* Digital microphone 5 and 6 */
161static const unsigned dmic56_d_1_pins[] = { AB9540_PIN_E4, AB9540_PIN_F3 };
162static const unsigned extcpena_d_1_pins[] = { AB9540_PIN_J13 };
163/* modem SDA/SCL */
164static const unsigned modsclsda_d_1_pins[] = { AB9540_PIN_L17, AB9540_PIN_L16 };
165static const unsigned sysclkreq5_d_1_pins[] = { AB9540_PIN_W3 };
166static const unsigned gpio50_d_1_pins[] = { AB9540_PIN_N4 };
167static const unsigned batremn_d_1_pins[] = { AB9540_PIN_G12 };
168static const unsigned resethw_d_1_pins[] = { AB9540_PIN_E17 };
169static const unsigned service_d_1_pins[] = { AB9540_PIN_D11 };
170static const unsigned gpio60_d_1_pins[] = { AB9540_PIN_M18 };
171
172/* Altfunction A column */
173static const unsigned gpio1_a_1_pins[] = { AB9540_PIN_R4 };
174static const unsigned gpio2_a_1_pins[] = { AB9540_PIN_V3 };
175static const unsigned gpio3_a_1_pins[] = { AB9540_PIN_T4 };
176static const unsigned gpio4_a_1_pins[] = { AB9540_PIN_T5 };
177static const unsigned hiqclkena_a_1_pins[] = { AB9540_PIN_B18 };
178static const unsigned pdmclk_a_1_pins[] = { AB9540_PIN_C18 };
179static const unsigned uartdata_a_1_pins[] = { AB9540_PIN_D18, AB9540_PIN_N4 };
180static const unsigned gpio14_a_1_pins[] = { AB9540_PIN_B19 };
181static const unsigned gpio15_a_1_pins[] = { AB9540_PIN_C19 };
182static const unsigned gpio16_a_1_pins[] = { AB9540_PIN_D19 };
183static const unsigned gpio17_a_1_pins[] = { AB9540_PIN_R3 };
184static const unsigned gpio18_a_1_pins[] = { AB9540_PIN_T2 };
185static const unsigned gpio19_a_1_pins[] = { AB9540_PIN_U2 };
186static const unsigned gpio20_a_1_pins[] = { AB9540_PIN_V2 };
187static const unsigned gpio21_a_1_pins[] = { AB9540_PIN_N17 };
188static const unsigned gpio22_a_1_pins[] = { AB9540_PIN_N16 };
189static const unsigned gpio23_a_1_pins[] = { AB9540_PIN_M19 };
190static const unsigned gpio24_a_1_pins[] = { AB9540_PIN_T3 };
191static const unsigned gpio25_a_1_pins[] = { AB9540_PIN_W2 };
192static const unsigned gpio27_a_1_pins[] = { AB9540_PIN_H4 };
193static const unsigned gpio28_a_1_pins[] = { AB9540_PIN_F1 };
194static const unsigned gpio29_a_1_pins[] = { AB9540_PIN_F4 };
195static const unsigned gpio30_a_1_pins[] = { AB9540_PIN_F2 };
196static const unsigned gpio31_a_1_pins[] = { AB9540_PIN_E4 };
197static const unsigned gpio32_a_1_pins[] = { AB9540_PIN_F3 };
198static const unsigned gpio34_a_1_pins[] = { AB9540_PIN_J13 };
199static const unsigned gpio40_a_1_pins[] = { AB9540_PIN_L17 };
200static const unsigned gpio41_a_1_pins[] = { AB9540_PIN_L16 };
201static const unsigned gpio42_a_1_pins[] = { AB9540_PIN_W3 };
202static const unsigned gpio51_a_1_pins[] = { AB9540_PIN_G12 };
203static const unsigned gpio52_a_1_pins[] = { AB9540_PIN_E17 };
204static const unsigned gpio53_a_1_pins[] = { AB9540_PIN_D11 };
205static const unsigned usbuiccpd_a_1_pins[] = { AB9540_PIN_M18 };
206
207/* Altfunction B colum */
208static const unsigned pdmdata_b_1_pins[] = { AB9540_PIN_B18 };
209static const unsigned pwmextvibra1_b_1_pins[] = { AB9540_PIN_D18 };
210static const unsigned pwmextvibra2_b_1_pins[] = { AB9540_PIN_N4 };
211
212/* Altfunction C column */
213static const unsigned usbvdat_c_1_pins[] = { AB9540_PIN_D18 };
214
215#define AB9540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
216 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
217
218static const struct abx500_pingroup ab9540_groups[] = {
219 /* default column */
220 AB9540_PIN_GROUP(sysclkreq2_d_1, ABX500_DEFAULT),
221 AB9540_PIN_GROUP(sysclkreq3_d_1, ABX500_DEFAULT),
222 AB9540_PIN_GROUP(sysclkreq4_d_1, ABX500_DEFAULT),
223 AB9540_PIN_GROUP(sysclkreq6_d_1, ABX500_DEFAULT),
224 AB9540_PIN_GROUP(gpio10_d_1, ABX500_DEFAULT),
225 AB9540_PIN_GROUP(gpio11_d_1, ABX500_DEFAULT),
226 AB9540_PIN_GROUP(gpio13_d_1, ABX500_DEFAULT),
227 AB9540_PIN_GROUP(pwmout1_d_1, ABX500_DEFAULT),
228 AB9540_PIN_GROUP(pwmout2_d_1, ABX500_DEFAULT),
229 AB9540_PIN_GROUP(pwmout3_d_1, ABX500_DEFAULT),
230 AB9540_PIN_GROUP(adi1_d_1, ABX500_DEFAULT),
231 AB9540_PIN_GROUP(usbuicc_d_1, ABX500_DEFAULT),
232 AB9540_PIN_GROUP(sysclkreq7_d_1, ABX500_DEFAULT),
233 AB9540_PIN_GROUP(sysclkreq8_d_1, ABX500_DEFAULT),
234 AB9540_PIN_GROUP(dmic12_d_1, ABX500_DEFAULT),
235 AB9540_PIN_GROUP(dmic34_d_1, ABX500_DEFAULT),
236 AB9540_PIN_GROUP(dmic56_d_1, ABX500_DEFAULT),
237 AB9540_PIN_GROUP(extcpena_d_1, ABX500_DEFAULT),
238 AB9540_PIN_GROUP(modsclsda_d_1, ABX500_DEFAULT),
239 AB9540_PIN_GROUP(sysclkreq5_d_1, ABX500_DEFAULT),
240 AB9540_PIN_GROUP(gpio50_d_1, ABX500_DEFAULT),
241 AB9540_PIN_GROUP(batremn_d_1, ABX500_DEFAULT),
242 AB9540_PIN_GROUP(resethw_d_1, ABX500_DEFAULT),
243 AB9540_PIN_GROUP(service_d_1, ABX500_DEFAULT),
244 AB9540_PIN_GROUP(gpio60_d_1, ABX500_DEFAULT),
245
246 /* Altfunction A column */
247 AB9540_PIN_GROUP(gpio1_a_1, ABX500_ALT_A),
248 AB9540_PIN_GROUP(gpio2_a_1, ABX500_ALT_A),
249 AB9540_PIN_GROUP(gpio3_a_1, ABX500_ALT_A),
250 AB9540_PIN_GROUP(gpio4_a_1, ABX500_ALT_A),
251 AB9540_PIN_GROUP(hiqclkena_a_1, ABX500_ALT_A),
252 AB9540_PIN_GROUP(pdmclk_a_1, ABX500_ALT_A),
253 AB9540_PIN_GROUP(uartdata_a_1, ABX500_ALT_A),
254 AB9540_PIN_GROUP(gpio14_a_1, ABX500_ALT_A),
255 AB9540_PIN_GROUP(gpio15_a_1, ABX500_ALT_A),
256 AB9540_PIN_GROUP(gpio16_a_1, ABX500_ALT_A),
257 AB9540_PIN_GROUP(gpio17_a_1, ABX500_ALT_A),
258 AB9540_PIN_GROUP(gpio18_a_1, ABX500_ALT_A),
259 AB9540_PIN_GROUP(gpio19_a_1, ABX500_ALT_A),
260 AB9540_PIN_GROUP(gpio20_a_1, ABX500_ALT_A),
261 AB9540_PIN_GROUP(gpio21_a_1, ABX500_ALT_A),
262 AB9540_PIN_GROUP(gpio22_a_1, ABX500_ALT_A),
263 AB9540_PIN_GROUP(gpio23_a_1, ABX500_ALT_A),
264 AB9540_PIN_GROUP(gpio24_a_1, ABX500_ALT_A),
265 AB9540_PIN_GROUP(gpio25_a_1, ABX500_ALT_A),
266 AB9540_PIN_GROUP(gpio27_a_1, ABX500_ALT_A),
267 AB9540_PIN_GROUP(gpio28_a_1, ABX500_ALT_A),
268 AB9540_PIN_GROUP(gpio29_a_1, ABX500_ALT_A),
269 AB9540_PIN_GROUP(gpio30_a_1, ABX500_ALT_A),
270 AB9540_PIN_GROUP(gpio31_a_1, ABX500_ALT_A),
271 AB9540_PIN_GROUP(gpio32_a_1, ABX500_ALT_A),
272 AB9540_PIN_GROUP(gpio34_a_1, ABX500_ALT_A),
273 AB9540_PIN_GROUP(gpio40_a_1, ABX500_ALT_A),
274 AB9540_PIN_GROUP(gpio41_a_1, ABX500_ALT_A),
275 AB9540_PIN_GROUP(gpio42_a_1, ABX500_ALT_A),
276 AB9540_PIN_GROUP(gpio51_a_1, ABX500_ALT_A),
277 AB9540_PIN_GROUP(gpio52_a_1, ABX500_ALT_A),
278 AB9540_PIN_GROUP(gpio53_a_1, ABX500_ALT_A),
279 AB9540_PIN_GROUP(usbuiccpd_a_1, ABX500_ALT_A),
280
281 /* Altfunction B column */
282 AB9540_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B),
283 AB9540_PIN_GROUP(pwmextvibra1_b_1, ABX500_ALT_B),
284 AB9540_PIN_GROUP(pwmextvibra2_b_1, ABX500_ALT_B),
285
286 /* Altfunction C column */
287 AB9540_PIN_GROUP(usbvdat_c_1, ABX500_ALT_C),
288};
289
290/* We use this macro to define the groups applicable to a function */
291#define AB9540_FUNC_GROUPS(a, b...) \
292static const char * const a##_groups[] = { b };
293
294AB9540_FUNC_GROUPS(sysclkreq, "sysclkreq2_d_1", "sysclkreq3_d_1",
295 "sysclkreq4_d_1", "sysclkreq5_d_1", "sysclkreq6_d_1",
296 "sysclkreq7_d_1", "sysclkreq8_d_1");
297AB9540_FUNC_GROUPS(gpio, "gpio1_a_1", "gpio2_a_1", "gpio3_a_1", "gpio4_a_1",
298 "gpio10_d_1", "gpio11_d_1", "gpio13_d_1", "gpio14_a_1",
299 "gpio15_a_1", "gpio16_a_1", "gpio17_a_1", "gpio18_a_1",
300 "gpio19_a_1", "gpio20_a_1", "gpio21_a_1", "gpio22_a_1",
301 "gpio23_a_1", "gpio24_a_1", "gpio25_a_1", "gpio27_a_1",
302 "gpio28_a_1", "gpio29_a_1", "gpio30_a_1", "gpio31_a_1",
303 "gpio32_a_1", "gpio34_a_1", "gpio40_a_1", "gpio41_a_1",
304 "gpio42_a_1", "gpio50_d_1", "gpio51_a_1", "gpio52_a_1",
305 "gpio53_a_1", "gpio60_d_1");
306AB9540_FUNC_GROUPS(pwmout, "pwmout1_d_1", "pwmout2_d_1", "pwmout3_d_1");
307AB9540_FUNC_GROUPS(adi1, "adi1_d_1");
308AB9540_FUNC_GROUPS(usbuicc, "usbuicc_d_1", "usbuiccpd_a_1");
309AB9540_FUNC_GROUPS(dmic, "dmic12_d_1", "dmic34_d_1", "dmic56_d_1");
310AB9540_FUNC_GROUPS(extcpena, "extcpena_d_1");
311AB9540_FUNC_GROUPS(modsclsda, "modsclsda_d_1");
312AB9540_FUNC_GROUPS(batremn, "batremn_d_1");
313AB9540_FUNC_GROUPS(resethw, "resethw_d_1");
314AB9540_FUNC_GROUPS(service, "service_d_1");
315AB9540_FUNC_GROUPS(hiqclkena, "hiqclkena_a_1");
316AB9540_FUNC_GROUPS(pdm, "pdmdata_b_1", "pdmclk_a_1");
317AB9540_FUNC_GROUPS(uartdata, "uartdata_a_1");
318AB9540_FUNC_GROUPS(pwmextvibra, "pwmextvibra1_b_1", "pwmextvibra2_b_1");
319AB9540_FUNC_GROUPS(usbvdat, "usbvdat_c_1");
320
321#define FUNCTION(fname) \
322 { \
323 .name = #fname, \
324 .groups = fname##_groups, \
325 .ngroups = ARRAY_SIZE(fname##_groups), \
326 }
327
328static const struct abx500_function ab9540_functions[] = {
329 FUNCTION(sysclkreq),
330 FUNCTION(gpio),
331 FUNCTION(pwmout),
332 FUNCTION(adi1),
333 FUNCTION(usbuicc),
334 FUNCTION(dmic),
335 FUNCTION(extcpena),
336 FUNCTION(modsclsda),
337 FUNCTION(batremn),
338 FUNCTION(resethw),
339 FUNCTION(service),
340 FUNCTION(hiqclkena),
341 FUNCTION(pdm),
342 FUNCTION(uartdata),
343 FUNCTION(pwmextvibra),
344 FUNCTION(usbvdat),
345};
346
347/*
348 * this table translates what's is in the AB9540 specification regarding the
349 * balls alternate functions (as for DB, default, ALT_A, ALT_B and ALT_C).
350 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
351 * ALTERNATEFUNC bit2, ALTA val, ALTB val, ALTC val),
352 *
353 * example :
354 *
355 * ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2),
356 * means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
357 * ALT_B and ALT_C), so GPIOSEL and ALTERNATFUNC registers are used to
358 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
359 * ALTERNATFUNC register. We need to specifies these values as SOC
360 * designers didn't apply the same logic on how to select mux in the
361 * ABx500 family.
362 *
363 * As this pins supports at least ALT_B mux, default mux is
364 * selected by writing 1 in GPIOSEL bit :
365 *
366 * | GPIOSEL bit=4 | alternatfunc bit2=4 | alternatfunc bit1=3
367 * default | 1 | 0 | 0
368 * alt_A | 0 | 0 | 1
369 * alt_B | 0 | 0 | 0
370 * alt_C | 0 | 1 | 0
371 *
372 * ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED),
373 * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
374 * register is used to select the mux. As this pins doesn't support at
375 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
376 *
377 * | GPIOSEL bit=0 | alternatfunc bit2= | alternatfunc bit1=
378 * default | 0 | 0 | 0
379 * alt_A | 1 | 0 | 0
380 */
381
382struct alternate_functions ab9540alternate_functions[AB9540_GPIO_MAX_NUMBER + 1] = {
383 /* GPIOSEL1 - bits 4-7 are reserved */
384 ALTERNATE_FUNCTIONS(0, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO0 */
385 ALTERNATE_FUNCTIONS(1, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO1, altA controlled by bit 0 */
386 ALTERNATE_FUNCTIONS(2, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO2, altA controlled by bit 1 */
387 ALTERNATE_FUNCTIONS(3, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO3, altA controlled by bit 2*/
388 ALTERNATE_FUNCTIONS(4, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO4, altA controlled by bit 3*/
389 ALTERNATE_FUNCTIONS(5, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO5 */
390 ALTERNATE_FUNCTIONS(6, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO6 */
391 ALTERNATE_FUNCTIONS(7, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO7 */
392 ALTERNATE_FUNCTIONS(8, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO8 */
393 /* GPIOSEL2 - bits 0 and 3 are reserved */
394 ALTERNATE_FUNCTIONS(9, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO9 */
395 ALTERNATE_FUNCTIONS(10, 1, 0, UNUSED, 1, 0, 0), /* GPIO10, altA and altB controlled by bit 0 */
396 ALTERNATE_FUNCTIONS(11, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO11, altA controlled by bit 1 */
397 ALTERNATE_FUNCTIONS(12, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO12 */
398 ALTERNATE_FUNCTIONS(13, 4, 3, 4, 1, 0, 2), /* GPIO13, altA altB and altC controlled by bit 3 and 4 */
399 ALTERNATE_FUNCTIONS(14, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO14, altA controlled by bit 5 */
400 ALTERNATE_FUNCTIONS(15, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO15, altA controlled by bit 6 */
401 ALTERNATE_FUNCTIONS(16, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO16, altA controlled by bit 7 */
402 /* GPIOSEL3 - bit 1-3 reserved
403 * pins 17 to 20 are special case, only bit 0 is used to select
404 * alternate function for these 4 pins.
405 * bits 1 to 3 are reserved
406 */
407 ALTERNATE_FUNCTIONS(17, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO17, altA controlled by bit 0 */
408 ALTERNATE_FUNCTIONS(18, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO18, altA controlled by bit 0 */
409 ALTERNATE_FUNCTIONS(19, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO19, altA controlled by bit 0 */
410 ALTERNATE_FUNCTIONS(20, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO20, altA controlled by bit 0 */
411 ALTERNATE_FUNCTIONS(21, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO21, altA controlled by bit 4 */
412 ALTERNATE_FUNCTIONS(22, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO22, altA controlled by bit 5 */
413 ALTERNATE_FUNCTIONS(23, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO23, altA controlled by bit 6 */
414 ALTERNATE_FUNCTIONS(24, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO24, altA controlled by bit 7 */
415 /* GPIOSEL4 - bit 1 reserved */
416 ALTERNATE_FUNCTIONS(25, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO25, altA controlled by bit 0 */
417 ALTERNATE_FUNCTIONS(26, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO26 */
418 ALTERNATE_FUNCTIONS(27, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO27, altA controlled by bit 2 */
419 ALTERNATE_FUNCTIONS(28, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO28, altA controlled by bit 3 */
420 ALTERNATE_FUNCTIONS(29, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO29, altA controlled by bit 4 */
421 ALTERNATE_FUNCTIONS(30, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO30, altA controlled by bit 5 */
422 ALTERNATE_FUNCTIONS(31, 6, UNUSED, UNUSED, 0, 0, 0), /* GPIO31, altA controlled by bit 6 */
423 ALTERNATE_FUNCTIONS(32, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO32, altA controlled by bit 7 */
424 /* GPIOSEL5 - bit 0, 2-6 are reserved */
425 ALTERNATE_FUNCTIONS(33, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO33 */
426 ALTERNATE_FUNCTIONS(34, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO34, altA controlled by bit 1 */
427 ALTERNATE_FUNCTIONS(35, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO35 */
428 ALTERNATE_FUNCTIONS(36, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO36 */
429 ALTERNATE_FUNCTIONS(37, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO37 */
430 ALTERNATE_FUNCTIONS(38, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO38 */
431 ALTERNATE_FUNCTIONS(39, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO39 */
432 ALTERNATE_FUNCTIONS(40, 7, UNUSED, UNUSED, 0, 0, 0), /* GPIO40, altA controlled by bit 7 */
433 /* GPIOSEL6 - bit 2-7 are reserved */
434 ALTERNATE_FUNCTIONS(41, 0, UNUSED, UNUSED, 0, 0, 0), /* GPIO41, altA controlled by bit 0 */
435 ALTERNATE_FUNCTIONS(42, 1, UNUSED, UNUSED, 0, 0, 0), /* GPIO42, altA controlled by bit 1 */
436 ALTERNATE_FUNCTIONS(43, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO43 */
437 ALTERNATE_FUNCTIONS(44, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO44 */
438 ALTERNATE_FUNCTIONS(45, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO45 */
439 ALTERNATE_FUNCTIONS(46, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO46 */
440 ALTERNATE_FUNCTIONS(47, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO47 */
441 ALTERNATE_FUNCTIONS(48, UNUSED, UNUSED, UNUSED, 0, 0, 0), /* no GPIO48 */
442 /*
443 * GPIOSEL7 - bit 0 and 6-7 are reserved
444 * special case with GPIO60, wich is located at offset 5 of gpiosel7
445 * don't know why it has been called GPIO60 in AB9540 datasheet,
446 * GPIO54 would be logical..., so at SOC point of view we consider
447 * GPIO60 = GPIO54
448 */
449 ALTERNATE_FUNCTIONS(49, 0, UNUSED, UNUSED, 0, 0, 0), /* no GPIO49 */
450 ALTERNATE_FUNCTIONS(50, 1, 2, UNUSED, 1, 0, 0), /* GPIO50, altA and altB controlled by bit 1 */
451 ALTERNATE_FUNCTIONS(51, 2, UNUSED, UNUSED, 0, 0, 0), /* GPIO51, altA controlled by bit 2 */
452 ALTERNATE_FUNCTIONS(52, 3, UNUSED, UNUSED, 0, 0, 0), /* GPIO52, altA controlled by bit 3 */
453 ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
454 ALTERNATE_FUNCTIONS(54, 5, UNUSED, UNUSED, 0, 0, 0), /* GPIO54 = GPIO60, altA controlled by bit 5 */
455};
456
457struct abx500_gpio_irq_cluster ab9540_gpio_irq_cluster[] = {
458 GPIO_IRQ_CLUSTER(10, 13, AB8500_INT_GPIO10R),
459 GPIO_IRQ_CLUSTER(24, 25, AB8500_INT_GPIO24R),
460 GPIO_IRQ_CLUSTER(40, 41, AB8500_INT_GPIO40R),
461 GPIO_IRQ_CLUSTER(50, 54, AB9540_INT_GPIO50R),
462};
463
464static struct abx500_pinctrl_soc_data ab9540_soc = {
465 .gpio_ranges = ab9540_pinranges,
466 .gpio_num_ranges = ARRAY_SIZE(ab9540_pinranges),
467 .pins = ab9540_pins,
468 .npins = ARRAY_SIZE(ab9540_pins),
469 .functions = ab9540_functions,
470 .nfunctions = ARRAY_SIZE(ab9540_functions),
471 .groups = ab9540_groups,
472 .ngroups = ARRAY_SIZE(ab9540_groups),
473 .alternate_functions = ab9540alternate_functions,
474 .gpio_irq_cluster = ab9540_gpio_irq_cluster,
475 .ngpio_irq_cluster = ARRAY_SIZE(ab9540_gpio_irq_cluster),
476 .irq_gpio_rising_offset = AB8500_INT_GPIO6R,
477 .irq_gpio_falling_offset = AB8500_INT_GPIO6F,
478 .irq_gpio_factor = 1,
479};
480
481void
482abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
483{
484 *soc = &ab9540_soc;
485}
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
new file mode 100644
index 000000000000..caecdd373061
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -0,0 +1,1012 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/mfd/abx500.h>
26#include <linux/mfd/abx500/ab8500.h>
27#include <linux/mfd/abx500/ab8500-gpio.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/consumer.h>
30#include <linux/pinctrl/pinmux.h>
31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinconf-generic.h>
33
34#include "pinctrl-abx500.h"
35
36/*
37 * The AB9540 and AB8540 GPIO support are extended versions
38 * of the AB8500 GPIO support.
39 * The AB9540 supports an additional (7th) register so that
40 * more GPIO may be configured and used.
41 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
42 * internal pull-up and pull-down capabilities.
43 */
44
45/*
46 * GPIO registers offset
47 * Bank: 0x10
48 */
49#define AB8500_GPIO_SEL1_REG 0x00
50#define AB8500_GPIO_SEL2_REG 0x01
51#define AB8500_GPIO_SEL3_REG 0x02
52#define AB8500_GPIO_SEL4_REG 0x03
53#define AB8500_GPIO_SEL5_REG 0x04
54#define AB8500_GPIO_SEL6_REG 0x05
55#define AB9540_GPIO_SEL7_REG 0x06
56
57#define AB8500_GPIO_DIR1_REG 0x10
58#define AB8500_GPIO_DIR2_REG 0x11
59#define AB8500_GPIO_DIR3_REG 0x12
60#define AB8500_GPIO_DIR4_REG 0x13
61#define AB8500_GPIO_DIR5_REG 0x14
62#define AB8500_GPIO_DIR6_REG 0x15
63#define AB9540_GPIO_DIR7_REG 0x16
64
65#define AB8500_GPIO_OUT1_REG 0x20
66#define AB8500_GPIO_OUT2_REG 0x21
67#define AB8500_GPIO_OUT3_REG 0x22
68#define AB8500_GPIO_OUT4_REG 0x23
69#define AB8500_GPIO_OUT5_REG 0x24
70#define AB8500_GPIO_OUT6_REG 0x25
71#define AB9540_GPIO_OUT7_REG 0x26
72
73#define AB8500_GPIO_PUD1_REG 0x30
74#define AB8500_GPIO_PUD2_REG 0x31
75#define AB8500_GPIO_PUD3_REG 0x32
76#define AB8500_GPIO_PUD4_REG 0x33
77#define AB8500_GPIO_PUD5_REG 0x34
78#define AB8500_GPIO_PUD6_REG 0x35
79#define AB9540_GPIO_PUD7_REG 0x36
80
81#define AB8500_GPIO_IN1_REG 0x40
82#define AB8500_GPIO_IN2_REG 0x41
83#define AB8500_GPIO_IN3_REG 0x42
84#define AB8500_GPIO_IN4_REG 0x43
85#define AB8500_GPIO_IN5_REG 0x44
86#define AB8500_GPIO_IN6_REG 0x45
87#define AB9540_GPIO_IN7_REG 0x46
88#define AB8540_GPIO_VINSEL_REG 0x47
89#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
90#define AB8500_GPIO_ALTFUN_REG 0x50
91#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
92#define AB8540_GPIO_VINSEL_MASK 0x03
93#define AB8540_GPIOX_VBAT_START 51
94#define AB8540_GPIOX_VBAT_END 54
95
96struct abx500_pinctrl {
97 struct device *dev;
98 struct pinctrl_dev *pctldev;
99 struct abx500_pinctrl_soc_data *soc;
100 struct gpio_chip chip;
101 struct ab8500 *parent;
102 struct mutex lock;
103 struct abx500_gpio_irq_cluster *irq_cluster;
104 int irq_cluster_size;
105};
106
107/**
108 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
109 * @chip: Member of the structure abx500_pinctrl
110 */
111static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
112{
113 return container_of(chip, struct abx500_pinctrl, chip);
114}
115
116static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
117 unsigned offset, bool *bit)
118{
119 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
120 u8 pos = offset % 8;
121 u8 val;
122 int ret;
123
124 reg += offset / 8;
125 ret = abx500_get_register_interruptible(pct->dev,
126 AB8500_MISC, reg, &val);
127
128 *bit = !!(val & BIT(pos));
129
130 if (ret < 0)
131 dev_err(pct->dev,
132 "%s read reg =%x, offset=%x failed\n",
133 __func__, reg, offset);
134
135 return ret;
136}
137
138static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
139 unsigned offset, int val)
140{
141 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
142 u8 pos = offset % 8;
143 int ret;
144
145 reg += offset / 8;
146 ret = abx500_mask_and_set_register_interruptible(pct->dev,
147 AB8500_MISC, reg, BIT(pos), val << pos);
148 if (ret < 0)
149 dev_err(pct->dev, "%s write failed\n", __func__);
150
151 return ret;
152}
153
154/**
155 * abx500_gpio_get() - Get the particular GPIO value
156 * @chip: Gpio device
157 * @offset: GPIO number to read
158 */
159static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
160{
161 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
162 bool bit;
163 int ret;
164
165 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
166 offset, &bit);
167 if (ret < 0) {
168 dev_err(pct->dev, "%s failed\n", __func__);
169 return ret;
170 }
171
172 return bit;
173}
174
175static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
176{
177 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
178 int ret;
179
180 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
181 if (ret < 0)
182 dev_err(pct->dev, "%s write failed\n", __func__);
183}
184
185static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
186 int offset, enum abx500_gpio_pull_updown val)
187{
188 u8 pos;
189 int ret;
190 struct pullud *pullud;
191
192 if (!pct->soc->pullud) {
193 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
194 __func__);
195 ret = -EPERM;
196 goto out;
197 }
198
199 pullud = pct->soc->pullud;
200
201 if ((offset < pullud->first_pin)
202 || (offset > pullud->last_pin)) {
203 ret = -EINVAL;
204 goto out;
205 }
206
207 pos = offset << 1;
208
209 ret = abx500_mask_and_set_register_interruptible(pct->dev,
210 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
211 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
212
213out:
214 if (ret < 0)
215 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
216
217 return ret;
218}
219
220static int abx500_gpio_direction_output(struct gpio_chip *chip,
221 unsigned offset,
222 int val)
223{
224 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
225 struct pullud *pullud = pct->soc->pullud;
226 unsigned gpio;
227 int ret;
228
229 /* set direction as output */
230 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
231 if (ret < 0)
232 return ret;
233
234 /* disable pull down */
235 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
236 if (ret < 0)
237 return ret;
238
239 /* if supported, disable both pull down and pull up */
240 gpio = offset + 1;
241 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
242 ret = abx500_config_pull_updown(pct,
243 gpio,
244 ABX500_GPIO_PULL_NONE);
245 if (ret < 0)
246 return ret;
247 }
248
249 /* set the output as 1 or 0 */
250 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
251}
252
253static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
254{
255 /* set the register as input */
256 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
257}
258
259static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
260{
261 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
262 /* The AB8500 GPIO numbers are off by one */
263 int gpio = offset + 1;
264 int hwirq;
265 int i;
266
267 for (i = 0; i < pct->irq_cluster_size; i++) {
268 struct abx500_gpio_irq_cluster *cluster =
269 &pct->irq_cluster[i];
270
271 if (gpio >= cluster->start && gpio <= cluster->end) {
272 /*
273 * The ABx500 GPIO's associated IRQs are clustered together
274 * throughout the interrupt numbers at irregular intervals.
275 * To solve this quandry, we have placed the read-in values
276 * into the cluster information table.
277 */
278 hwirq = gpio - cluster->start + cluster->to_irq;
279 return irq_create_mapping(pct->parent->domain, hwirq);
280 }
281 }
282
283 return -EINVAL;
284}
285
286static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
287 unsigned gpio, int alt_setting)
288{
289 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
290 struct alternate_functions af = pct->soc->alternate_functions[gpio];
291 int ret;
292 int val;
293 unsigned offset;
294
295 const char *modes[] = {
296 [ABX500_DEFAULT] = "default",
297 [ABX500_ALT_A] = "altA",
298 [ABX500_ALT_B] = "altB",
299 [ABX500_ALT_C] = "altC",
300 };
301
302 /* sanity check */
303 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
304 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
305 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
306 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
307 modes[alt_setting]);
308 return -EINVAL;
309 }
310
311 /* on ABx5xx, there is no GPIO0, so adjust the offset */
312 offset = gpio - 1;
313
314 switch (alt_setting) {
315 case ABX500_DEFAULT:
316 /*
317 * for ABx5xx family, default mode is always selected by
318 * writing 0 to GPIOSELx register, except for pins which
319 * support at least ALT_B mode, default mode is selected
320 * by writing 1 to GPIOSELx register
321 */
322 val = 0;
323 if (af.alt_bit1 != UNUSED)
324 val++;
325
326 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
327 offset, val);
328 break;
329
330 case ABX500_ALT_A:
331 /*
332 * for ABx5xx family, alt_a mode is always selected by
333 * writing 1 to GPIOSELx register, except for pins which
334 * support at least ALT_B mode, alt_a mode is selected
335 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
336 * register
337 */
338 if (af.alt_bit1 != UNUSED) {
339 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
340 offset, 0);
341 ret = abx500_gpio_set_bits(chip,
342 AB8500_GPIO_ALTFUN_REG,
343 af.alt_bit1,
344 !!(af.alta_val && BIT(0)));
345 if (af.alt_bit2 != UNUSED)
346 ret = abx500_gpio_set_bits(chip,
347 AB8500_GPIO_ALTFUN_REG,
348 af.alt_bit2,
349 !!(af.alta_val && BIT(1)));
350 } else
351 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
352 offset, 1);
353 break;
354
355 case ABX500_ALT_B:
356 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
357 offset, 0);
358 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
359 af.alt_bit1, !!(af.altb_val && BIT(0)));
360 if (af.alt_bit2 != UNUSED)
361 ret = abx500_gpio_set_bits(chip,
362 AB8500_GPIO_ALTFUN_REG,
363 af.alt_bit2,
364 !!(af.altb_val && BIT(1)));
365 break;
366
367 case ABX500_ALT_C:
368 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
369 offset, 0);
370 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
371 af.alt_bit2, !!(af.altc_val && BIT(0)));
372 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
373 af.alt_bit2, !!(af.altc_val && BIT(1)));
374 break;
375
376 default:
377 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
378
379 return -EINVAL;
380 }
381
382 return ret;
383}
384
385static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
386 unsigned gpio)
387{
388 u8 mode;
389 bool bit_mode;
390 bool alt_bit1;
391 bool alt_bit2;
392 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
393 struct alternate_functions af = pct->soc->alternate_functions[gpio];
394 /* on ABx5xx, there is no GPIO0, so adjust the offset */
395 unsigned offset = gpio - 1;
396
397 /*
398 * if gpiosel_bit is set to unused,
399 * it means no GPIO or special case
400 */
401 if (af.gpiosel_bit == UNUSED)
402 return ABX500_DEFAULT;
403
404 /* read GpioSelx register */
405 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
406 af.gpiosel_bit, &bit_mode);
407 mode = bit_mode;
408
409 /* sanity check */
410 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
411 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
412 dev_err(pct->dev,
413 "alt_bitX value not in correct range (-1 to 7)\n");
414 return -EINVAL;
415 }
416
417 /* if alt_bit2 is used, alt_bit1 must be used too */
418 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
419 dev_err(pct->dev,
420 "if alt_bit2 is used, alt_bit1 can't be unused\n");
421 return -EINVAL;
422 }
423
424 /* check if pin use AlternateFunction register */
425 if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
426 return mode;
427 /*
428 * if pin GPIOSEL bit is set and pin supports alternate function,
429 * it means DEFAULT mode
430 */
431 if (mode)
432 return ABX500_DEFAULT;
433
434 /*
435 * pin use the AlternatFunction register
436 * read alt_bit1 value
437 */
438 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
439 af.alt_bit1, &alt_bit1);
440
441 if (af.alt_bit2 != UNUSED)
442 /* read alt_bit2 value */
443 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
444 &alt_bit2);
445 else
446 alt_bit2 = 0;
447
448 mode = (alt_bit2 << 1) + alt_bit1;
449 if (mode == af.alta_val)
450 return ABX500_ALT_A;
451 else if (mode == af.altb_val)
452 return ABX500_ALT_B;
453 else
454 return ABX500_ALT_C;
455}
456
457#ifdef CONFIG_DEBUG_FS
458
459#include <linux/seq_file.h>
460
461static void abx500_gpio_dbg_show_one(struct seq_file *s,
462 struct pinctrl_dev *pctldev,
463 struct gpio_chip *chip,
464 unsigned offset, unsigned gpio)
465{
466 const char *label = gpiochip_is_requested(chip, offset - 1);
467 u8 gpio_offset = offset - 1;
468 int mode = -1;
469 bool is_out;
470 bool pull;
471
472 const char *modes[] = {
473 [ABX500_DEFAULT] = "default",
474 [ABX500_ALT_A] = "altA",
475 [ABX500_ALT_B] = "altB",
476 [ABX500_ALT_C] = "altC",
477 };
478
479 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
480 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
481
482 if (pctldev)
483 mode = abx500_get_mode(pctldev, chip, offset);
484
485 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
486 gpio, label ?: "(none)",
487 is_out ? "out" : "in ",
488 is_out ?
489 (chip->get
490 ? (chip->get(chip, offset) ? "hi" : "lo")
491 : "? ")
492 : (pull ? "pull up" : "pull down"),
493 (mode < 0) ? "unknown" : modes[mode]);
494}
495
496static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
497{
498 unsigned i;
499 unsigned gpio = chip->base;
500 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
501 struct pinctrl_dev *pctldev = pct->pctldev;
502
503 for (i = 0; i < chip->ngpio; i++, gpio++) {
504 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
505 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
506 seq_printf(s, "\n");
507 }
508}
509
510#else
511static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
512 struct pinctrl_dev *pctldev,
513 struct gpio_chip *chip,
514 unsigned offset, unsigned gpio)
515{
516}
517#define abx500_gpio_dbg_show NULL
518#endif
519
520int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
521{
522 int gpio = chip->base + offset;
523
524 return pinctrl_request_gpio(gpio);
525}
526
527void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
528{
529 int gpio = chip->base + offset;
530
531 pinctrl_free_gpio(gpio);
532}
533
534static struct gpio_chip abx500gpio_chip = {
535 .label = "abx500-gpio",
536 .owner = THIS_MODULE,
537 .request = abx500_gpio_request,
538 .free = abx500_gpio_free,
539 .direction_input = abx500_gpio_direction_input,
540 .get = abx500_gpio_get,
541 .direction_output = abx500_gpio_direction_output,
542 .set = abx500_gpio_set,
543 .to_irq = abx500_gpio_to_irq,
544 .dbg_show = abx500_gpio_dbg_show,
545};
546
547static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
548{
549 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
550
551 return pct->soc->nfunctions;
552}
553
554static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
555 unsigned function)
556{
557 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
558
559 return pct->soc->functions[function].name;
560}
561
562static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
563 unsigned function,
564 const char * const **groups,
565 unsigned * const num_groups)
566{
567 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
568
569 *groups = pct->soc->functions[function].groups;
570 *num_groups = pct->soc->functions[function].ngroups;
571
572 return 0;
573}
574
575static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
576 unsigned group)
577{
578 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
579 struct gpio_chip *chip = &pct->chip;
580 const struct abx500_pingroup *g;
581 int i;
582 int ret = 0;
583
584 g = &pct->soc->groups[group];
585 if (g->altsetting < 0)
586 return -EINVAL;
587
588 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
589
590 for (i = 0; i < g->npins; i++) {
591 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
592 g->pins[i], g->altsetting);
593
594 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
595 }
596
597 return ret;
598}
599
600static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
601 unsigned function, unsigned group)
602{
603 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
604 const struct abx500_pingroup *g;
605
606 g = &pct->soc->groups[group];
607 if (g->altsetting < 0)
608 return;
609
610 /* FIXME: poke out the mux, set the pin to some default state? */
611 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
612}
613
614int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
615 struct pinctrl_gpio_range *range,
616 unsigned offset)
617{
618 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
619 const struct abx500_pinrange *p;
620 int ret;
621 int i;
622
623 /*
624 * Different ranges have different ways to enable GPIO function on a
625 * pin, so refer back to our local range type, where we handily define
626 * what altfunc enables GPIO for a certain pin.
627 */
628 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
629 p = &pct->soc->gpio_ranges[i];
630 if ((offset >= p->offset) &&
631 (offset < (p->offset + p->npins)))
632 break;
633 }
634
635 if (i == pct->soc->gpio_num_ranges) {
636 dev_err(pct->dev, "%s failed to locate range\n", __func__);
637 return -ENODEV;
638 }
639
640 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
641 p->altfunc, offset);
642
643 ret = abx500_set_mode(pct->pctldev, &pct->chip,
644 offset, p->altfunc);
645 if (ret < 0) {
646 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
647 return ret;
648 }
649
650 return ret;
651}
652
653static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
654 struct pinctrl_gpio_range *range,
655 unsigned offset)
656{
657}
658
659static struct pinmux_ops abx500_pinmux_ops = {
660 .get_functions_count = abx500_pmx_get_funcs_cnt,
661 .get_function_name = abx500_pmx_get_func_name,
662 .get_function_groups = abx500_pmx_get_func_groups,
663 .enable = abx500_pmx_enable,
664 .disable = abx500_pmx_disable,
665 .gpio_request_enable = abx500_gpio_request_enable,
666 .gpio_disable_free = abx500_gpio_disable_free,
667};
668
669static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
670{
671 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
672
673 return pct->soc->ngroups;
674}
675
676static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
677 unsigned selector)
678{
679 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
680
681 return pct->soc->groups[selector].name;
682}
683
684static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
685 unsigned selector,
686 const unsigned **pins,
687 unsigned *num_pins)
688{
689 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
690
691 *pins = pct->soc->groups[selector].pins;
692 *num_pins = pct->soc->groups[selector].npins;
693
694 return 0;
695}
696
697static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
698 struct seq_file *s, unsigned offset)
699{
700 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
701 struct gpio_chip *chip = &pct->chip;
702
703 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
704 chip->base + offset - 1);
705}
706
707static struct pinctrl_ops abx500_pinctrl_ops = {
708 .get_groups_count = abx500_get_groups_cnt,
709 .get_group_name = abx500_get_group_name,
710 .get_group_pins = abx500_get_group_pins,
711 .pin_dbg_show = abx500_pin_dbg_show,
712};
713
714int abx500_pin_config_get(struct pinctrl_dev *pctldev,
715 unsigned pin,
716 unsigned long *config)
717{
718 return -ENOSYS;
719}
720
721int abx500_pin_config_set(struct pinctrl_dev *pctldev,
722 unsigned pin,
723 unsigned long config)
724{
725 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
726 struct pullud *pullud = pct->soc->pullud;
727 struct gpio_chip *chip = &pct->chip;
728 unsigned offset;
729 int ret;
730 enum pin_config_param param = pinconf_to_config_param(config);
731 enum pin_config_param argument = pinconf_to_config_argument(config);
732
733 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
734 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
735 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
736 (argument ? "pull up" : "pull down"));
737
738 /* on ABx500, there is no GPIO0, so adjust the offset */
739 offset = pin - 1;
740
741 switch (param) {
742 case PIN_CONFIG_BIAS_PULL_DOWN:
743 /*
744 * if argument = 1 set the pull down
745 * else clear the pull down
746 */
747 ret = abx500_gpio_direction_input(chip, offset);
748 /*
749 * Some chips only support pull down, while some actually
750 * support both pull up and pull down. Such chips have
751 * a "pullud" range specified for the pins that support
752 * both features. If the pin is not within that range, we
753 * fall back to the old bit set that only support pull down.
754 */
755 if (pullud &&
756 pin >= pullud->first_pin &&
757 pin <= pullud->last_pin)
758 ret = abx500_config_pull_updown(pct,
759 pin,
760 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
761 else
762 /* Chip only supports pull down */
763 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
764 offset, argument ? 0 : 1);
765 break;
766
767 case PIN_CONFIG_OUTPUT:
768 ret = abx500_gpio_direction_output(chip, offset, argument);
769
770 break;
771
772 default:
773 dev_err(chip->dev, "illegal configuration requested\n");
774
775 return -EINVAL;
776 }
777
778 return ret;
779}
780
781static struct pinconf_ops abx500_pinconf_ops = {
782 .pin_config_get = abx500_pin_config_get,
783 .pin_config_set = abx500_pin_config_set,
784};
785
786static struct pinctrl_desc abx500_pinctrl_desc = {
787 .name = "pinctrl-abx500",
788 .pctlops = &abx500_pinctrl_ops,
789 .pmxops = &abx500_pinmux_ops,
790 .confops = &abx500_pinconf_ops,
791 .owner = THIS_MODULE,
792};
793
794static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
795{
796 unsigned int lowest = 0;
797 unsigned int highest = 0;
798 unsigned int npins = 0;
799 int i;
800
801 /*
802 * Compute number of GPIOs from the last SoC gpio range descriptors
803 * These ranges may include "holes" but the GPIO number space shall
804 * still be homogeneous, so we need to detect and account for any
805 * such holes so that these are included in the number of GPIO pins.
806 */
807 for (i = 0; i < soc->gpio_num_ranges; i++) {
808 unsigned gstart;
809 unsigned gend;
810 const struct abx500_pinrange *p;
811
812 p = &soc->gpio_ranges[i];
813 gstart = p->offset;
814 gend = p->offset + p->npins - 1;
815
816 if (i == 0) {
817 /* First iteration, set start values */
818 lowest = gstart;
819 highest = gend;
820 } else {
821 if (gstart < lowest)
822 lowest = gstart;
823 if (gend > highest)
824 highest = gend;
825 }
826 }
827 /* this gives the absolute number of pins */
828 npins = highest - lowest + 1;
829 return npins;
830}
831
832static const struct of_device_id abx500_gpio_match[] = {
833 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
834 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
835 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
836 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
837};
838
839static int abx500_gpio_probe(struct platform_device *pdev)
840{
841 struct ab8500_platform_data *abx500_pdata =
842 dev_get_platdata(pdev->dev.parent);
843 struct abx500_gpio_platform_data *pdata = NULL;
844 struct device_node *np = pdev->dev.of_node;
845 struct abx500_pinctrl *pct;
846 const struct platform_device_id *platid = platform_get_device_id(pdev);
847 unsigned int id = -1;
848 int ret, err;
849 int i;
850
851 if (abx500_pdata)
852 pdata = abx500_pdata->gpio;
853 if (!pdata) {
854 if (np) {
855 const struct of_device_id *match;
856
857 match = of_match_device(abx500_gpio_match, &pdev->dev);
858 if (!match)
859 return -ENODEV;
860 id = (unsigned long)match->data;
861 } else {
862 dev_err(&pdev->dev, "gpio dt and platform data missing\n");
863 return -ENODEV;
864 }
865 }
866
867 if (platid)
868 id = platid->driver_data;
869
870 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
871 GFP_KERNEL);
872 if (pct == NULL) {
873 dev_err(&pdev->dev,
874 "failed to allocate memory for pct\n");
875 return -ENOMEM;
876 }
877
878 pct->dev = &pdev->dev;
879 pct->parent = dev_get_drvdata(pdev->dev.parent);
880 pct->chip = abx500gpio_chip;
881 pct->chip.dev = &pdev->dev;
882 pct->chip.base = pdata->gpio_base;
883 pct->chip.base = (np) ? -1 : pdata->gpio_base;
884
885 /* initialize the lock */
886 mutex_init(&pct->lock);
887
888 /* Poke in other ASIC variants here */
889 switch (id) {
890 case PINCTRL_AB8500:
891 abx500_pinctrl_ab8500_init(&pct->soc);
892 break;
893 case PINCTRL_AB8540:
894 abx500_pinctrl_ab8540_init(&pct->soc);
895 break;
896 case PINCTRL_AB9540:
897 abx500_pinctrl_ab9540_init(&pct->soc);
898 break;
899 case PINCTRL_AB8505:
900 abx500_pinctrl_ab8505_init(&pct->soc);
901 break;
902 default:
903 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n",
904 (int) platid->driver_data);
905 mutex_destroy(&pct->lock);
906 return -EINVAL;
907 }
908
909 if (!pct->soc) {
910 dev_err(&pdev->dev, "Invalid SOC data\n");
911 mutex_destroy(&pct->lock);
912 return -EINVAL;
913 }
914
915 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
916 pct->irq_cluster = pct->soc->gpio_irq_cluster;
917 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
918
919 ret = gpiochip_add(&pct->chip);
920 if (ret) {
921 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
922 mutex_destroy(&pct->lock);
923 return ret;
924 }
925 dev_info(&pdev->dev, "added gpiochip\n");
926
927 abx500_pinctrl_desc.pins = pct->soc->pins;
928 abx500_pinctrl_desc.npins = pct->soc->npins;
929 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
930 if (!pct->pctldev) {
931 dev_err(&pdev->dev,
932 "could not register abx500 pinctrl driver\n");
933 ret = -EINVAL;
934 goto out_rem_chip;
935 }
936 dev_info(&pdev->dev, "registered pin controller\n");
937
938 /* We will handle a range of GPIO pins */
939 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
940 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
941
942 ret = gpiochip_add_pin_range(&pct->chip,
943 dev_name(&pdev->dev),
944 p->offset - 1, p->offset, p->npins);
945 if (ret < 0)
946 goto out_rem_chip;
947 }
948
949 platform_set_drvdata(pdev, pct);
950 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
951
952 return 0;
953
954out_rem_chip:
955 err = gpiochip_remove(&pct->chip);
956 if (err)
957 dev_info(&pdev->dev, "failed to remove gpiochip\n");
958
959 mutex_destroy(&pct->lock);
960 return ret;
961}
962
963/**
964 * abx500_gpio_remove() - remove Ab8500-gpio driver
965 * @pdev: Platform device registered
966 */
967static int abx500_gpio_remove(struct platform_device *pdev)
968{
969 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
970 int ret;
971
972 ret = gpiochip_remove(&pct->chip);
973 if (ret < 0) {
974 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
975 ret);
976 return ret;
977 }
978
979 mutex_destroy(&pct->lock);
980
981 return 0;
982}
983
984static const struct platform_device_id abx500_pinctrl_id[] = {
985 { "pinctrl-ab8500", PINCTRL_AB8500 },
986 { "pinctrl-ab8540", PINCTRL_AB8540 },
987 { "pinctrl-ab9540", PINCTRL_AB9540 },
988 { "pinctrl-ab8505", PINCTRL_AB8505 },
989 { },
990};
991
992static struct platform_driver abx500_gpio_driver = {
993 .driver = {
994 .name = "abx500-gpio",
995 .owner = THIS_MODULE,
996 .of_match_table = abx500_gpio_match,
997 },
998 .probe = abx500_gpio_probe,
999 .remove = abx500_gpio_remove,
1000 .id_table = abx500_pinctrl_id,
1001};
1002
1003static int __init abx500_gpio_init(void)
1004{
1005 return platform_driver_register(&abx500_gpio_driver);
1006}
1007core_initcall(abx500_gpio_init);
1008
1009MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1010MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1011MODULE_ALIAS("platform:abx500-gpio");
1012MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-abx500.h b/drivers/pinctrl/pinctrl-abx500.h
new file mode 100644
index 000000000000..eeca8f973999
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-abx500.h
@@ -0,0 +1,234 @@
1#ifndef PINCTRL_PINCTRL_ABx5O0_H
2#define PINCTRL_PINCTRL_ABx500_H
3
4/* Package definitions */
5#define PINCTRL_AB8500 0
6#define PINCTRL_AB8540 1
7#define PINCTRL_AB9540 2
8#define PINCTRL_AB8505 3
9
10/* pins alternate function */
11enum abx500_pin_func {
12 ABX500_DEFAULT,
13 ABX500_ALT_A,
14 ABX500_ALT_B,
15 ABX500_ALT_C,
16};
17
18/**
19 * struct abx500_function - ABx500 pinctrl mux function
20 * @name: The name of the function, exported to pinctrl core.
21 * @groups: An array of pin groups that may select this function.
22 * @ngroups: The number of entries in @groups.
23 */
24struct abx500_function {
25 const char *name;
26 const char * const *groups;
27 unsigned ngroups;
28};
29
30/**
31 * struct abx500_pingroup - describes a ABx500 pin group
32 * @name: the name of this specific pin group
33 * @pins: an array of discrete physical pins used in this group, taken
34 * from the driver-local pin enumeration space
35 * @num_pins: the number of pins in this group array, i.e. the number of
36 * elements in .pins so we can iterate over that array
37 * @altsetting: the altsetting to apply to all pins in this group to
38 * configure them to be used by a function
39 */
40struct abx500_pingroup {
41 const char *name;
42 const unsigned int *pins;
43 const unsigned npins;
44 int altsetting;
45};
46
47#define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
48{ \
49 .pin_number = pin, \
50 .gpiosel_bit = sel_bit, \
51 .alt_bit1 = alt1, \
52 .alt_bit2 = alt2, \
53 .alta_val = alta, \
54 .altb_val = altb, \
55 .altc_val = altc, \
56}
57
58#define UNUSED -1
59/**
60 * struct alternate_functions
61 * @pin_number: The pin number
62 * @gpiosel_bit: Control bit in GPIOSEL register,
63 * @alt_bit1: First AlternateFunction bit used to select the
64 * alternate function
65 * @alt_bit2: Second AlternateFunction bit used to select the
66 * alternate function
67 *
68 * these 3 following fields are necessary due to none
69 * coherency on how to select the altA, altB and altC
70 * function between the ABx500 SOC family when using
71 * alternatfunc register.
72 * @alta_val: value to write in alternatfunc to select altA function
73 * @altb_val: value to write in alternatfunc to select altB function
74 * @altc_val: value to write in alternatfunc to select altC function
75 */
76struct alternate_functions {
77 unsigned pin_number;
78 s8 gpiosel_bit;
79 s8 alt_bit1;
80 s8 alt_bit2;
81 u8 alta_val;
82 u8 altb_val;
83 u8 altc_val;
84};
85
86/**
87 * struct pullud - specific pull up/down feature
88 * @first_pin: The pin number of the first pins which support
89 * specific pull up/down
90 * @last_pin: The pin number of the last pins
91 */
92struct pullud {
93 unsigned first_pin;
94 unsigned last_pin;
95};
96
97#define GPIO_IRQ_CLUSTER(a, b, c) \
98{ \
99 .start = a, \
100 .end = b, \
101 .to_irq = c, \
102}
103
104/**
105 * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
106 * capable
107 * @start: The pin number of the first pin interrupt capable
108 * @end: The pin number of the last pin interrupt capable
109 * @to_irq: The ABx500 GPIO's associated IRQs are clustered
110 * together throughout the interrupt numbers at irregular
111 * intervals. To solve this quandary, we will place the
112 * read-in values into the cluster information table
113 */
114
115struct abx500_gpio_irq_cluster {
116 int start;
117 int end;
118 int to_irq;
119};
120
121/**
122 * struct abx500_pinrange - map pin numbers to GPIO offsets
123 * @offset: offset into the GPIO local numberspace, incidentally
124 * identical to the offset into the local pin numberspace
125 * @npins: number of pins to map from both offsets
126 * @altfunc: altfunc setting to be used to enable GPIO on a pin in
127 * this range (may vary)
128 */
129struct abx500_pinrange {
130 unsigned int offset;
131 unsigned int npins;
132 int altfunc;
133};
134
135#define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
136
137/**
138 * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
139 * @gpio_ranges: An array of GPIO ranges for this SoC
140 * @gpio_num_ranges: The number of GPIO ranges for this SoC
141 * @pins: An array describing all pins the pin controller affects.
142 * All pins which are also GPIOs must be listed first within the
143 * array, and be numbered identically to the GPIO controller's
144 * numbering.
145 * @npins: The number of entries in @pins.
146 * @functions: The functions supported on this SoC.
147 * @nfunction: The number of entries in @functions.
148 * @groups: An array describing all pin groups the pin SoC supports.
149 * @ngroups: The number of entries in @groups.
150 * @alternate_functions: array describing pins which supports alternate and
151 * how to set it.
152 * @pullud: array describing pins which supports pull up/down
153 * specific registers.
154 * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
155 * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
156 * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
157 * setting strategy of the rising interrupt line
158 * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
159 * setting strategy of the falling interrupt line
160 * @irq_gpio_factor: Factor used to compute specific setting strategy of
161 * the interrupt line
162 */
163
164struct abx500_pinctrl_soc_data {
165 const struct abx500_pinrange *gpio_ranges;
166 unsigned gpio_num_ranges;
167 const struct pinctrl_pin_desc *pins;
168 unsigned npins;
169 const struct abx500_function *functions;
170 unsigned nfunctions;
171 const struct abx500_pingroup *groups;
172 unsigned ngroups;
173 struct alternate_functions *alternate_functions;
174 struct pullud *pullud;
175 struct abx500_gpio_irq_cluster *gpio_irq_cluster;
176 unsigned ngpio_irq_cluster;
177 int irq_gpio_rising_offset;
178 int irq_gpio_falling_offset;
179 int irq_gpio_factor;
180};
181
182#ifdef CONFIG_PINCTRL_AB8500
183
184void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc);
185
186#else
187
188static inline void
189abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
190{
191}
192
193#endif
194
195#ifdef CONFIG_PINCTRL_AB8540
196
197void abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc);
198
199#else
200
201static inline void
202abx500_pinctrl_ab8540_init(struct abx500_pinctrl_soc_data **soc)
203{
204}
205
206#endif
207
208#ifdef CONFIG_PINCTRL_AB9540
209
210void abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc);
211
212#else
213
214static inline void
215abx500_pinctrl_ab9540_init(struct abx500_pinctrl_soc_data **soc)
216{
217}
218
219#endif
220
221#ifdef CONFIG_PINCTRL_AB8505
222
223void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
224
225#else
226
227static inline void
228abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
229{
230}
231
232#endif
233
234#endif /* PINCTRL_PINCTRL_ABx500_H */
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index 8ed20e84cb02..4a0d54a08890 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -170,7 +170,7 @@ static const unsigned pins_ntr[] = {GPIO4};
170static const unsigned pins_ntr8k[] = {GPIO5}; 170static const unsigned pins_ntr8k[] = {GPIO5};
171static const unsigned pins_hrst[] = {GPIO6}; 171static const unsigned pins_hrst[] = {GPIO6};
172static const unsigned pins_mdio[] = {GPIO7, GPIO8}; 172static const unsigned pins_mdio[] = {GPIO7, GPIO8};
173static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11, 173static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
174 GPIO12, GPIO13, GPIO14}; 174 GPIO12, GPIO13, GPIO14};
175static const unsigned pins_asc0[] = {GPIO32, GPIO33}; 175static const unsigned pins_asc0[] = {GPIO32, GPIO33};
176static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36}; 176static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
@@ -315,6 +315,37 @@ static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
315static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev, 315static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
316 struct seq_file *s, unsigned offset) 316 struct seq_file *s, unsigned offset)
317{ 317{
318 unsigned long config;
319 struct pin_desc *desc;
320
321 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
322 int port = PORT(offset);
323
324 seq_printf(s, " (port %d) mux %d -- ", port,
325 pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
326
327 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
328 if (!falcon_pinconf_get(pctrldev, offset, &config))
329 seq_printf(s, "pull %d ",
330 (int)LTQ_PINCONF_UNPACK_ARG(config));
331
332 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
333 if (!falcon_pinconf_get(pctrldev, offset, &config))
334 seq_printf(s, "drive-current %d ",
335 (int)LTQ_PINCONF_UNPACK_ARG(config));
336
337 config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
338 if (!falcon_pinconf_get(pctrldev, offset, &config))
339 seq_printf(s, "slew-rate %d ",
340 (int)LTQ_PINCONF_UNPACK_ARG(config));
341
342 desc = pin_desc_get(pctrldev, offset);
343 if (desc) {
344 if (desc->gpio_owner)
345 seq_printf(s, " owner: %s", desc->gpio_owner);
346 } else {
347 seq_printf(s, " not registered");
348 }
318} 349}
319 350
320static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev, 351static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
@@ -360,6 +391,8 @@ static const struct ltq_cfg_param falcon_cfg_params[] = {
360static struct ltq_pinmux_info falcon_info = { 391static struct ltq_pinmux_info falcon_info = {
361 .desc = &falcon_pctrl_desc, 392 .desc = &falcon_pctrl_desc,
362 .apply_mux = falcon_mux_apply, 393 .apply_mux = falcon_mux_apply,
394 .params = falcon_cfg_params,
395 .num_params = ARRAY_SIZE(falcon_cfg_params),
363}; 396};
364 397
365 398
@@ -398,6 +431,9 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
398 u32 avail; 431 u32 avail;
399 int pins; 432 int pins;
400 433
434 if (!of_device_is_available(np))
435 continue;
436
401 if (!ppdev) { 437 if (!ppdev) {
402 dev_err(&pdev->dev, "failed to find pad pdev\n"); 438 dev_err(&pdev->dev, "failed to find pad pdev\n");
403 continue; 439 continue;
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
index 15f501d89026..a70384611351 100644
--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -64,11 +64,13 @@ static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
64 seq_printf(s, " %s", dev_name(pctldev->dev)); 64 seq_printf(s, " %s", dev_name(pctldev->dev));
65} 65}
66 66
67static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, 67static void ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
68 struct device_node *np, 68 struct device_node *np,
69 struct pinctrl_map **map) 69 struct pinctrl_map **map)
70{ 70{
71 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev); 71 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
72 struct property *pins = of_find_property(np, "lantiq,pins", NULL);
73 struct property *groups = of_find_property(np, "lantiq,groups", NULL);
72 unsigned long configs[3]; 74 unsigned long configs[3];
73 unsigned num_configs = 0; 75 unsigned num_configs = 0;
74 struct property *prop; 76 struct property *prop;
@@ -76,8 +78,20 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
76 const char *function; 78 const char *function;
77 int ret, i; 79 int ret, i;
78 80
81 if (!pins && !groups) {
82 dev_err(pctldev->dev, "%s defines neither pins nor groups\n",
83 np->name);
84 return;
85 }
86
87 if (pins && groups) {
88 dev_err(pctldev->dev, "%s defines both pins and groups\n",
89 np->name);
90 return;
91 }
92
79 ret = of_property_read_string(np, "lantiq,function", &function); 93 ret = of_property_read_string(np, "lantiq,function", &function);
80 if (!ret) { 94 if (groups && !ret) {
81 of_property_for_each_string(np, "lantiq,groups", prop, group) { 95 of_property_for_each_string(np, "lantiq,groups", prop, group) {
82 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; 96 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
83 (*map)->name = function; 97 (*map)->name = function;
@@ -85,11 +99,6 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
85 (*map)->data.mux.function = function; 99 (*map)->data.mux.function = function;
86 (*map)++; 100 (*map)++;
87 } 101 }
88 if (of_find_property(np, "lantiq,pins", NULL))
89 dev_err(pctldev->dev,
90 "%s mixes pins and groups settings\n",
91 np->name);
92 return 0;
93 } 102 }
94 103
95 for (i = 0; i < info->num_params; i++) { 104 for (i = 0; i < info->num_params; i++) {
@@ -103,7 +112,7 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
103 } 112 }
104 113
105 if (!num_configs) 114 if (!num_configs)
106 return -EINVAL; 115 return;
107 116
108 of_property_for_each_string(np, "lantiq,pins", prop, pin) { 117 of_property_for_each_string(np, "lantiq,pins", prop, pin) {
109 (*map)->data.configs.configs = kmemdup(configs, 118 (*map)->data.configs.configs = kmemdup(configs,
@@ -115,7 +124,16 @@ static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
115 (*map)->data.configs.num_configs = num_configs; 124 (*map)->data.configs.num_configs = num_configs;
116 (*map)++; 125 (*map)++;
117 } 126 }
118 return 0; 127 of_property_for_each_string(np, "lantiq,groups", prop, group) {
128 (*map)->data.configs.configs = kmemdup(configs,
129 num_configs * sizeof(unsigned long),
130 GFP_KERNEL);
131 (*map)->type = PIN_MAP_TYPE_CONFIGS_GROUP;
132 (*map)->name = group;
133 (*map)->data.configs.group_or_pin = group;
134 (*map)->data.configs.num_configs = num_configs;
135 (*map)++;
136 }
119} 137}
120 138
121static int ltq_pinctrl_dt_subnode_size(struct device_node *np) 139static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
@@ -135,23 +153,19 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
135{ 153{
136 struct pinctrl_map *tmp; 154 struct pinctrl_map *tmp;
137 struct device_node *np; 155 struct device_node *np;
138 int ret; 156 int max_maps = 0;
139 157
140 *num_maps = 0;
141 for_each_child_of_node(np_config, np) 158 for_each_child_of_node(np_config, np)
142 *num_maps += ltq_pinctrl_dt_subnode_size(np); 159 max_maps += ltq_pinctrl_dt_subnode_size(np);
143 *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL); 160 *map = kzalloc(max_maps * sizeof(struct pinctrl_map) * 2, GFP_KERNEL);
144 if (!*map) 161 if (!*map)
145 return -ENOMEM; 162 return -ENOMEM;
146 tmp = *map; 163 tmp = *map;
147 164
148 for_each_child_of_node(np_config, np) { 165 for_each_child_of_node(np_config, np)
149 ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp); 166 ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
150 if (ret < 0) { 167 *num_maps = ((int)(tmp - *map));
151 ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps); 168
152 return ret;
153 }
154 }
155 return 0; 169 return 0;
156} 170}
157 171
@@ -280,7 +294,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
280 unsigned pin) 294 unsigned pin)
281{ 295{
282 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 296 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
283 int mfp = match_mfp(info, pin + (range->id * 32)); 297 int mfp = match_mfp(info, pin);
284 int pin_func; 298 int pin_func;
285 299
286 if (mfp < 0) { 300 if (mfp < 0) {
diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h
index 4419d32a0ade..6d07f0238532 100644
--- a/drivers/pinctrl/pinctrl-lantiq.h
+++ b/drivers/pinctrl/pinctrl-lantiq.h
@@ -34,6 +34,7 @@ enum ltq_pinconf_param {
34 LTQ_PINCONF_PARAM_OPEN_DRAIN, 34 LTQ_PINCONF_PARAM_OPEN_DRAIN,
35 LTQ_PINCONF_PARAM_DRIVE_CURRENT, 35 LTQ_PINCONF_PARAM_DRIVE_CURRENT,
36 LTQ_PINCONF_PARAM_SLEW_RATE, 36 LTQ_PINCONF_PARAM_SLEW_RATE,
37 LTQ_PINCONF_PARAM_OUTPUT,
37}; 38};
38 39
39struct ltq_cfg_param { 40struct ltq_cfg_param {
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 5767b18ebdff..de9e8519b803 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -25,6 +25,8 @@
25#include <linux/irqdomain.h> 25#include <linux/irqdomain.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/of_device.h> 27#include <linux/of_device.h>
28#include <linux/of_address.h>
29#include <linux/pinctrl/machine.h>
28#include <linux/pinctrl/pinctrl.h> 30#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/pinmux.h> 31#include <linux/pinctrl/pinmux.h>
30#include <linux/pinctrl/pinconf.h> 32#include <linux/pinctrl/pinconf.h>
@@ -32,8 +34,8 @@
32#include <linux/pinctrl/consumer.h> 34#include <linux/pinctrl/consumer.h>
33#include <linux/platform_data/pinctrl-nomadik.h> 35#include <linux/platform_data/pinctrl-nomadik.h>
34#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
35#include <mach/irqs.h>
36#include "pinctrl-nomadik.h" 37#include "pinctrl-nomadik.h"
38#include "core.h"
37 39
38/* 40/*
39 * The GPIO module in the Nomadik family of Systems-on-Chip is an 41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -216,7 +218,7 @@ nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
216 u32 falling = nmk_chip->fimsc & BIT(offset); 218 u32 falling = nmk_chip->fimsc & BIT(offset);
217 u32 rising = nmk_chip->rimsc & BIT(offset); 219 u32 rising = nmk_chip->rimsc & BIT(offset);
218 int gpio = nmk_chip->chip.base + offset; 220 int gpio = nmk_chip->chip.base + offset;
219 int irq = NOMADIK_GPIO_TO_IRQ(gpio); 221 int irq = irq_find_mapping(nmk_chip->domain, offset);
220 struct irq_data *d = irq_get_irq_data(irq); 222 struct irq_data *d = irq_get_irq_data(irq);
221 223
222 if (!rising && !falling) 224 if (!rising && !falling)
@@ -1341,8 +1343,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
1341 1343
1342 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1344 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1343 dev_err(&dev->dev, "gpio-bank property not found\n"); 1345 dev_err(&dev->dev, "gpio-bank property not found\n");
1344 ret = -EINVAL; 1346 return -EINVAL;
1345 goto out;
1346 } 1347 }
1347 1348
1348 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; 1349 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
@@ -1350,41 +1351,29 @@ static int nmk_gpio_probe(struct platform_device *dev)
1350 } 1351 }
1351 1352
1352 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1353 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1353 if (!res) { 1354 if (!res)
1354 ret = -ENOENT; 1355 return -ENOENT;
1355 goto out;
1356 }
1357 1356
1358 irq = platform_get_irq(dev, 0); 1357 irq = platform_get_irq(dev, 0);
1359 if (irq < 0) { 1358 if (irq < 0)
1360 ret = irq; 1359 return irq;
1361 goto out;
1362 }
1363 1360
1364 secondary_irq = platform_get_irq(dev, 1); 1361 secondary_irq = platform_get_irq(dev, 1);
1365 if (secondary_irq >= 0 && !pdata->get_secondary_status) { 1362 if (secondary_irq >= 0 && !pdata->get_secondary_status)
1366 ret = -EINVAL; 1363 return -EINVAL;
1367 goto out;
1368 }
1369 1364
1370 base = devm_request_and_ioremap(&dev->dev, res); 1365 base = devm_request_and_ioremap(&dev->dev, res);
1371 if (!base) { 1366 if (!base)
1372 ret = -ENOMEM; 1367 return -ENOMEM;
1373 goto out;
1374 }
1375 1368
1376 clk = devm_clk_get(&dev->dev, NULL); 1369 clk = devm_clk_get(&dev->dev, NULL);
1377 if (IS_ERR(clk)) { 1370 if (IS_ERR(clk))
1378 ret = PTR_ERR(clk); 1371 return PTR_ERR(clk);
1379 goto out;
1380 }
1381 clk_prepare(clk); 1372 clk_prepare(clk);
1382 1373
1383 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL); 1374 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1384 if (!nmk_chip) { 1375 if (!nmk_chip)
1385 ret = -ENOMEM; 1376 return -ENOMEM;
1386 goto out;
1387 }
1388 1377
1389 /* 1378 /*
1390 * The virt address in nmk_chip->addr is in the nomadik register space, 1379 * The virt address in nmk_chip->addr is in the nomadik register space,
@@ -1418,7 +1407,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
1418 1407
1419 ret = gpiochip_add(&nmk_chip->chip); 1408 ret = gpiochip_add(&nmk_chip->chip);
1420 if (ret) 1409 if (ret)
1421 goto out; 1410 return ret;
1422 1411
1423 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1412 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1424 1413
@@ -1427,14 +1416,15 @@ static int nmk_gpio_probe(struct platform_device *dev)
1427 platform_set_drvdata(dev, nmk_chip); 1416 platform_set_drvdata(dev, nmk_chip);
1428 1417
1429 if (!np) 1418 if (!np)
1430 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio); 1419 irq_start = pdata->first_irq;
1431 nmk_chip->domain = irq_domain_add_simple(np, 1420 nmk_chip->domain = irq_domain_add_simple(np,
1432 NMK_GPIO_PER_CHIP, irq_start, 1421 NMK_GPIO_PER_CHIP, irq_start,
1433 &nmk_gpio_irq_simple_ops, nmk_chip); 1422 &nmk_gpio_irq_simple_ops, nmk_chip);
1434 if (!nmk_chip->domain) { 1423 if (!nmk_chip->domain) {
1435 dev_err(&dev->dev, "failed to create irqdomain\n"); 1424 dev_err(&dev->dev, "failed to create irqdomain\n");
1436 ret = -ENOSYS; 1425 /* Just do this, no matter if it fails */
1437 goto out; 1426 ret = gpiochip_remove(&nmk_chip->chip);
1427 return -ENOSYS;
1438 } 1428 }
1439 1429
1440 nmk_gpio_init_irq(nmk_chip); 1430 nmk_gpio_init_irq(nmk_chip);
@@ -1442,12 +1432,6 @@ static int nmk_gpio_probe(struct platform_device *dev)
1442 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); 1432 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1443 1433
1444 return 0; 1434 return 0;
1445
1446out:
1447 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1448 pdata->first_gpio, pdata->first_gpio+31);
1449
1450 return ret;
1451} 1435}
1452 1436
1453static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) 1437static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
@@ -1508,11 +1492,285 @@ static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1508 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1492 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1509} 1493}
1510 1494
1495static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1496 struct pinctrl_map *map, unsigned num_maps)
1497{
1498 int i;
1499
1500 for (i = 0; i < num_maps; i++)
1501 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1502 kfree(map[i].data.configs.configs);
1503 kfree(map);
1504}
1505
1506static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1507 unsigned *num_maps, unsigned reserve)
1508{
1509 unsigned old_num = *reserved_maps;
1510 unsigned new_num = *num_maps + reserve;
1511 struct pinctrl_map *new_map;
1512
1513 if (old_num >= new_num)
1514 return 0;
1515
1516 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1517 if (!new_map)
1518 return -ENOMEM;
1519
1520 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1521
1522 *map = new_map;
1523 *reserved_maps = new_num;
1524
1525 return 0;
1526}
1527
1528static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1529 unsigned *num_maps, const char *group,
1530 const char *function)
1531{
1532 if (*num_maps == *reserved_maps)
1533 return -ENOSPC;
1534
1535 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1536 (*map)[*num_maps].data.mux.group = group;
1537 (*map)[*num_maps].data.mux.function = function;
1538 (*num_maps)++;
1539
1540 return 0;
1541}
1542
1543static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1544 unsigned *reserved_maps,
1545 unsigned *num_maps, const char *group,
1546 unsigned long *configs, unsigned num_configs)
1547{
1548 unsigned long *dup_configs;
1549
1550 if (*num_maps == *reserved_maps)
1551 return -ENOSPC;
1552
1553 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1554 GFP_KERNEL);
1555 if (!dup_configs)
1556 return -ENOMEM;
1557
1558 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1559
1560 (*map)[*num_maps].data.configs.group_or_pin = group;
1561 (*map)[*num_maps].data.configs.configs = dup_configs;
1562 (*map)[*num_maps].data.configs.num_configs = num_configs;
1563 (*num_maps)++;
1564
1565 return 0;
1566}
1567
1568#define NMK_CONFIG_PIN(x,y) { .property = x, .config = y, }
1569#define NMK_CONFIG_PIN_ARRAY(x,y) { .property = x, .choice = y, \
1570 .size = ARRAY_SIZE(y), }
1571
1572static const unsigned long nmk_pin_input_modes[] = {
1573 PIN_INPUT_NOPULL,
1574 PIN_INPUT_PULLUP,
1575 PIN_INPUT_PULLDOWN,
1576};
1577
1578static const unsigned long nmk_pin_output_modes[] = {
1579 PIN_OUTPUT_LOW,
1580 PIN_OUTPUT_HIGH,
1581 PIN_DIR_OUTPUT,
1582};
1583
1584static const unsigned long nmk_pin_sleep_modes[] = {
1585 PIN_SLEEPMODE_DISABLED,
1586 PIN_SLEEPMODE_ENABLED,
1587};
1588
1589static const unsigned long nmk_pin_sleep_input_modes[] = {
1590 PIN_SLPM_INPUT_NOPULL,
1591 PIN_SLPM_INPUT_PULLUP,
1592 PIN_SLPM_INPUT_PULLDOWN,
1593 PIN_SLPM_DIR_INPUT,
1594};
1595
1596static const unsigned long nmk_pin_sleep_output_modes[] = {
1597 PIN_SLPM_OUTPUT_LOW,
1598 PIN_SLPM_OUTPUT_HIGH,
1599 PIN_SLPM_DIR_OUTPUT,
1600};
1601
1602static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1603 PIN_SLPM_WAKEUP_DISABLE,
1604 PIN_SLPM_WAKEUP_ENABLE,
1605};
1606
1607static const unsigned long nmk_pin_gpio_modes[] = {
1608 PIN_GPIOMODE_DISABLED,
1609 PIN_GPIOMODE_ENABLED,
1610};
1611
1612static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1613 PIN_SLPM_PDIS_DISABLED,
1614 PIN_SLPM_PDIS_ENABLED,
1615};
1616
1617struct nmk_cfg_param {
1618 const char *property;
1619 unsigned long config;
1620 const unsigned long *choice;
1621 int size;
1622};
1623
1624static const struct nmk_cfg_param nmk_cfg_params[] = {
1625 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1626 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1627 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1628 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1629 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1630 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1631 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1632 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1633};
1634
1635static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1636{
1637 int ret = 0;
1638
1639 if (nmk_cfg_params[index].choice == NULL)
1640 *config = nmk_cfg_params[index].config;
1641 else {
1642 /* test if out of range */
1643 if (val < nmk_cfg_params[index].size) {
1644 *config = nmk_cfg_params[index].config |
1645 nmk_cfg_params[index].choice[val];
1646 }
1647 }
1648 return ret;
1649}
1650
1651static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1652{
1653 int i, pin_number;
1654 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1655
1656 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1657 for (i = 0; i < npct->soc->npins; i++)
1658 if (npct->soc->pins[i].number == pin_number)
1659 return npct->soc->pins[i].name;
1660 return NULL;
1661}
1662
1663static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1664 unsigned long *configs)
1665{
1666 bool has_config = 0;
1667 unsigned long cfg = 0;
1668 int i, val, ret;
1669
1670 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1671 ret = of_property_read_u32(np,
1672 nmk_cfg_params[i].property, &val);
1673 if (ret != -EINVAL) {
1674 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1675 *configs |= cfg;
1676 has_config = 1;
1677 }
1678 }
1679 }
1680
1681 return has_config;
1682}
1683
1684int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1685 struct device_node *np,
1686 struct pinctrl_map **map,
1687 unsigned *reserved_maps,
1688 unsigned *num_maps)
1689{
1690 int ret;
1691 const char *function = NULL;
1692 unsigned long configs = 0;
1693 bool has_config = 0;
1694 unsigned reserve = 0;
1695 struct property *prop;
1696 const char *group, *gpio_name;
1697 struct device_node *np_config;
1698
1699 ret = of_property_read_string(np, "ste,function", &function);
1700 if (ret >= 0)
1701 reserve = 1;
1702
1703 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1704
1705 np_config = of_parse_phandle(np, "ste,config", 0);
1706 if (np_config)
1707 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1708
1709 ret = of_property_count_strings(np, "ste,pins");
1710 if (ret < 0)
1711 goto exit;
1712
1713 if (has_config)
1714 reserve++;
1715
1716 reserve *= ret;
1717
1718 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1719 if (ret < 0)
1720 goto exit;
1721
1722 of_property_for_each_string(np, "ste,pins", prop, group) {
1723 if (function) {
1724 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1725 group, function);
1726 if (ret < 0)
1727 goto exit;
1728 }
1729 if (has_config) {
1730 gpio_name = nmk_find_pin_name(pctldev, group);
1731
1732 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1733 gpio_name, &configs, 1);
1734 if (ret < 0)
1735 goto exit;
1736 }
1737
1738 }
1739exit:
1740 return ret;
1741}
1742
1743int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1744 struct device_node *np_config,
1745 struct pinctrl_map **map, unsigned *num_maps)
1746{
1747 unsigned reserved_maps;
1748 struct device_node *np;
1749 int ret;
1750
1751 reserved_maps = 0;
1752 *map = NULL;
1753 *num_maps = 0;
1754
1755 for_each_child_of_node(np_config, np) {
1756 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1757 &reserved_maps, num_maps);
1758 if (ret < 0) {
1759 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1760 return ret;
1761 }
1762 }
1763
1764 return 0;
1765}
1766
1511static struct pinctrl_ops nmk_pinctrl_ops = { 1767static struct pinctrl_ops nmk_pinctrl_ops = {
1512 .get_groups_count = nmk_get_groups_cnt, 1768 .get_groups_count = nmk_get_groups_cnt,
1513 .get_group_name = nmk_get_group_name, 1769 .get_group_name = nmk_get_group_name,
1514 .get_group_pins = nmk_get_group_pins, 1770 .get_group_pins = nmk_get_group_pins,
1515 .pin_dbg_show = nmk_pin_dbg_show, 1771 .pin_dbg_show = nmk_pin_dbg_show,
1772 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1773 .dt_free_map = nmk_pinctrl_dt_free_map,
1516}; 1774};
1517 1775
1518static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1776static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@@ -1846,16 +2104,39 @@ static struct pinctrl_desc nmk_pinctrl_desc = {
1846 2104
1847static const struct of_device_id nmk_pinctrl_match[] = { 2105static const struct of_device_id nmk_pinctrl_match[] = {
1848 { 2106 {
1849 .compatible = "stericsson,nmk_pinctrl", 2107 .compatible = "stericsson,nmk-pinctrl",
1850 .data = (void *)PINCTRL_NMK_DB8500, 2108 .data = (void *)PINCTRL_NMK_DB8500,
1851 }, 2109 },
1852 {}, 2110 {},
1853}; 2111};
1854 2112
2113static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
2114{
2115 struct nmk_pinctrl *npct;
2116
2117 npct = platform_get_drvdata(pdev);
2118 if (!npct)
2119 return -EINVAL;
2120
2121 return pinctrl_force_sleep(npct->pctl);
2122}
2123
2124static int nmk_pinctrl_resume(struct platform_device *pdev)
2125{
2126 struct nmk_pinctrl *npct;
2127
2128 npct = platform_get_drvdata(pdev);
2129 if (!npct)
2130 return -EINVAL;
2131
2132 return pinctrl_force_default(npct->pctl);
2133}
2134
1855static int nmk_pinctrl_probe(struct platform_device *pdev) 2135static int nmk_pinctrl_probe(struct platform_device *pdev)
1856{ 2136{
1857 const struct platform_device_id *platid = platform_get_device_id(pdev); 2137 const struct platform_device_id *platid = platform_get_device_id(pdev);
1858 struct device_node *np = pdev->dev.of_node; 2138 struct device_node *np = pdev->dev.of_node;
2139 struct device_node *prcm_np;
1859 struct nmk_pinctrl *npct; 2140 struct nmk_pinctrl *npct;
1860 struct resource *res; 2141 struct resource *res;
1861 unsigned int version = 0; 2142 unsigned int version = 0;
@@ -1884,21 +2165,26 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
1884 if (version == PINCTRL_NMK_DB8540) 2165 if (version == PINCTRL_NMK_DB8540)
1885 nmk_pinctrl_db8540_init(&npct->soc); 2166 nmk_pinctrl_db8540_init(&npct->soc);
1886 2167
2168 if (np) {
2169 prcm_np = of_parse_phandle(np, "prcm", 0);
2170 if (prcm_np)
2171 npct->prcm_base = of_iomap(prcm_np, 0);
2172 }
2173
2174 /* Allow platform passed information to over-write DT. */
1887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1888 if (res) { 2176 if (res)
1889 npct->prcm_base = devm_ioremap(&pdev->dev, res->start, 2177 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1890 resource_size(res)); 2178 resource_size(res));
1891 if (!npct->prcm_base) { 2179 if (!npct->prcm_base) {
1892 dev_err(&pdev->dev, 2180 if (version == PINCTRL_NMK_STN8815) {
1893 "failed to ioremap PRCM registers\n"); 2181 dev_info(&pdev->dev,
1894 return -ENOMEM; 2182 "No PRCM base, "
2183 "assuming no ALT-Cx control is available\n");
2184 } else {
2185 dev_err(&pdev->dev, "missing PRCM base address\n");
2186 return -EINVAL;
1895 } 2187 }
1896 } else if (version == PINCTRL_NMK_STN8815) {
1897 dev_info(&pdev->dev,
1898 "No PRCM base, assume no ALT-Cx control is available\n");
1899 } else {
1900 dev_err(&pdev->dev, "missing PRCM base address\n");
1901 return -EINVAL;
1902 } 2188 }
1903 2189
1904 /* 2190 /*
@@ -1963,6 +2249,10 @@ static struct platform_driver nmk_pinctrl_driver = {
1963 }, 2249 },
1964 .probe = nmk_pinctrl_probe, 2250 .probe = nmk_pinctrl_probe,
1965 .id_table = nmk_pinctrl_id, 2251 .id_table = nmk_pinctrl_id,
2252#ifdef CONFIG_PM
2253 .suspend = nmk_pinctrl_suspend,
2254 .resume = nmk_pinctrl_resume,
2255#endif
1966}; 2256};
1967 2257
1968static int __init nmk_gpio_init(void) 2258static int __init nmk_gpio_init(void)
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index fd7b24cd8908..5c20ed056054 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -716,7 +716,6 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
716 } 716 }
717 ctrldesc->pins = pindesc; 717 ctrldesc->pins = pindesc;
718 ctrldesc->npins = drvdata->ctrl->nr_pins; 718 ctrldesc->npins = drvdata->ctrl->nr_pins;
719 ctrldesc->npins = drvdata->ctrl->nr_pins;
720 719
721 /* dynamically populate the pin number and pin name for pindesc */ 720 /* dynamically populate the pin number and pin name for pindesc */
722 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) 721 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
new file mode 100644
index 000000000000..80b11e3415bc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -0,0 +1,1505 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/io.h>
14#include <linux/gpio.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinconf-generic.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26
27#include "core.h"
28#include "pinctrl-sunxi.h"
29
30static const struct sunxi_desc_pin sun4i_a10_pins[] = {
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out")),
34 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out")),
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out")),
40 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out")),
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out")),
46 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out")),
49 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
50 SUNXI_FUNCTION(0x0, "gpio_in"),
51 SUNXI_FUNCTION(0x1, "gpio_out")),
52 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out")),
55 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out")),
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out")),
61 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
69 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
70 SUNXI_FUNCTION(0x0, "gpio_in"),
71 SUNXI_FUNCTION(0x1, "gpio_out"),
72 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
93 /* Hole */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
95 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out")),
97 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
98 SUNXI_FUNCTION(0x0, "gpio_in"),
99 SUNXI_FUNCTION(0x1, "gpio_out")),
100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out")),
103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out")),
106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out")),
109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
110 SUNXI_FUNCTION(0x0, "gpio_in"),
111 SUNXI_FUNCTION(0x1, "gpio_out")),
112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
113 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out")),
115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
116 SUNXI_FUNCTION(0x0, "gpio_in"),
117 SUNXI_FUNCTION(0x1, "gpio_out")),
118 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
119 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out")),
121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
122 SUNXI_FUNCTION(0x0, "gpio_in"),
123 SUNXI_FUNCTION(0x1, "gpio_out")),
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out")),
127 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out")),
130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
131 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out")),
133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out")),
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out")),
139 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
140 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out")),
142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
143 SUNXI_FUNCTION(0x0, "gpio_in"),
144 SUNXI_FUNCTION(0x1, "gpio_out")),
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out")),
148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
149 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out")),
151 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
152 SUNXI_FUNCTION(0x0, "gpio_in"),
153 SUNXI_FUNCTION(0x1, "gpio_out")),
154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out")),
157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
158 SUNXI_FUNCTION(0x0, "gpio_in"),
159 SUNXI_FUNCTION(0x1, "gpio_out")),
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
168 /* Hole */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
170 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out")),
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out")),
175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out")),
178 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
179 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out")),
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out")),
184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out")),
187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out")),
190 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out")),
193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
194 SUNXI_FUNCTION(0x0, "gpio_in"),
195 SUNXI_FUNCTION(0x1, "gpio_out")),
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out")),
199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out")),
202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out")),
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out")),
208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out")),
211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
212 SUNXI_FUNCTION(0x0, "gpio_in"),
213 SUNXI_FUNCTION(0x1, "gpio_out")),
214 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
215 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out")),
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out")),
220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out")),
223 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
224 SUNXI_FUNCTION(0x0, "gpio_in"),
225 SUNXI_FUNCTION(0x1, "gpio_out")),
226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
227 SUNXI_FUNCTION(0x0, "gpio_in"),
228 SUNXI_FUNCTION(0x1, "gpio_out")),
229 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out")),
232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out")),
235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out")),
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out")),
241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out")),
244 /* Hole */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out")),
248 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out")),
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out")),
254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
255 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out")),
257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out")),
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out")),
263 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out")),
266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
267 SUNXI_FUNCTION(0x0, "gpio_in"),
268 SUNXI_FUNCTION(0x1, "gpio_out")),
269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out")),
272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out")),
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out")),
278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out")),
281 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out")),
284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
285 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out")),
287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out")),
290 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
291 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out")),
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out")),
296 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
297 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out")),
299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out")),
302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out")),
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out")),
308 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out")),
311 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out")),
314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out")),
317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out")),
320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
321 SUNXI_FUNCTION(0x0, "gpio_in"),
322 SUNXI_FUNCTION(0x1, "gpio_out")),
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out")),
326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out")),
329 /* Hole */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
331 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out")),
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out")),
336 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out")),
339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out")),
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out")),
345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out")),
348 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
349 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out")),
351 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out")),
354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out")),
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out")),
360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out")),
363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out")),
366 /* Hole */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out")),
370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out")),
373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
374 SUNXI_FUNCTION(0x0, "gpio_in"),
375 SUNXI_FUNCTION(0x1, "gpio_out"),
376 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out")),
380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
384 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
385 SUNXI_FUNCTION(0x0, "gpio_in"),
386 SUNXI_FUNCTION(0x1, "gpio_out")),
387 /* Hole */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
389 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out")),
391 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out")),
394 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
395 SUNXI_FUNCTION(0x0, "gpio_in"),
396 SUNXI_FUNCTION(0x1, "gpio_out")),
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out")),
400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out")),
403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
404 SUNXI_FUNCTION(0x0, "gpio_in"),
405 SUNXI_FUNCTION(0x1, "gpio_out")),
406 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
407 SUNXI_FUNCTION(0x0, "gpio_in"),
408 SUNXI_FUNCTION(0x1, "gpio_out")),
409 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
410 SUNXI_FUNCTION(0x0, "gpio_in"),
411 SUNXI_FUNCTION(0x1, "gpio_out")),
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out")),
415 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out")),
418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
419 SUNXI_FUNCTION(0x0, "gpio_in"),
420 SUNXI_FUNCTION(0x1, "gpio_out")),
421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out")),
424 /* Hole */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out")),
428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
429 SUNXI_FUNCTION(0x0, "gpio_in"),
430 SUNXI_FUNCTION(0x1, "gpio_out")),
431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
432 SUNXI_FUNCTION(0x0, "gpio_in"),
433 SUNXI_FUNCTION(0x1, "gpio_out")),
434 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
435 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out")),
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out")),
440 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out")),
443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
444 SUNXI_FUNCTION(0x0, "gpio_in"),
445 SUNXI_FUNCTION(0x1, "gpio_out")),
446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out")),
449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
450 SUNXI_FUNCTION(0x0, "gpio_in"),
451 SUNXI_FUNCTION(0x1, "gpio_out")),
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out")),
455 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out")),
458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
459 SUNXI_FUNCTION(0x0, "gpio_in"),
460 SUNXI_FUNCTION(0x1, "gpio_out")),
461 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out")),
464 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
465 SUNXI_FUNCTION(0x0, "gpio_in"),
466 SUNXI_FUNCTION(0x1, "gpio_out")),
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out")),
470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out")),
473 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
474 SUNXI_FUNCTION(0x0, "gpio_in"),
475 SUNXI_FUNCTION(0x1, "gpio_out")),
476 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out")),
479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
480 SUNXI_FUNCTION(0x0, "gpio_in"),
481 SUNXI_FUNCTION(0x1, "gpio_out")),
482 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out")),
485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out")),
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out")),
491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
492 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out")),
494 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
495 SUNXI_FUNCTION(0x0, "gpio_in"),
496 SUNXI_FUNCTION(0x1, "gpio_out")),
497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
498 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out")),
500 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out")),
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out")),
506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
507 SUNXI_FUNCTION(0x0, "gpio_in"),
508 SUNXI_FUNCTION(0x1, "gpio_out")),
509 /* Hole */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out")),
513 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
514 SUNXI_FUNCTION(0x0, "gpio_in"),
515 SUNXI_FUNCTION(0x1, "gpio_out")),
516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out")),
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out")),
522 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
523 SUNXI_FUNCTION(0x0, "gpio_in"),
524 SUNXI_FUNCTION(0x1, "gpio_out")),
525 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
526 SUNXI_FUNCTION(0x0, "gpio_in"),
527 SUNXI_FUNCTION(0x1, "gpio_out")),
528 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
529 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out")),
531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
532 SUNXI_FUNCTION(0x0, "gpio_in"),
533 SUNXI_FUNCTION(0x1, "gpio_out")),
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out")),
537 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
538 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out")),
540 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out")),
543 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
544 SUNXI_FUNCTION(0x0, "gpio_in"),
545 SUNXI_FUNCTION(0x1, "gpio_out")),
546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
547 SUNXI_FUNCTION(0x0, "gpio_in"),
548 SUNXI_FUNCTION(0x1, "gpio_out")),
549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
550 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out")),
552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
553 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out")),
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out")),
558 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out")),
561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
562 SUNXI_FUNCTION(0x0, "gpio_in"),
563 SUNXI_FUNCTION(0x1, "gpio_out")),
564 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out")),
567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
568 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out")),
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out")),
573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out")),
576};
577
578static const struct sunxi_desc_pin sun5i_a13_pins[] = {
579 /* Hole */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
581 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out")),
583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x1, "gpio_out")),
586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
587 SUNXI_FUNCTION(0x0, "gpio_in"),
588 SUNXI_FUNCTION(0x1, "gpio_out")),
589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
590 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out")),
592 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
593 SUNXI_FUNCTION(0x0, "gpio_in"),
594 SUNXI_FUNCTION(0x1, "gpio_out")),
595 /* Hole */
596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
597 SUNXI_FUNCTION(0x0, "gpio_in"),
598 SUNXI_FUNCTION(0x1, "gpio_out")),
599 /* Hole */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out")),
603 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out")),
606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
607 SUNXI_FUNCTION(0x0, "gpio_in"),
608 SUNXI_FUNCTION(0x1, "gpio_out")),
609 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out")),
612 /* Hole */
613 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
614 SUNXI_FUNCTION(0x0, "gpio_in"),
615 SUNXI_FUNCTION(0x1, "gpio_out")),
616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
617 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out")),
619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
620 SUNXI_FUNCTION(0x0, "gpio_in"),
621 SUNXI_FUNCTION(0x1, "gpio_out")),
622 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
623 SUNXI_FUNCTION(0x0, "gpio_in"),
624 SUNXI_FUNCTION(0x1, "gpio_out")),
625 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
626 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out")),
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out")),
631 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
632 SUNXI_FUNCTION(0x0, "gpio_in"),
633 SUNXI_FUNCTION(0x1, "gpio_out")),
634 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
635 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out")),
637 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
638 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out")),
640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out")),
643 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
644 SUNXI_FUNCTION(0x0, "gpio_in"),
645 SUNXI_FUNCTION(0x1, "gpio_out")),
646 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out")),
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out")),
652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out")),
655 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
656 SUNXI_FUNCTION(0x0, "gpio_in"),
657 SUNXI_FUNCTION(0x1, "gpio_out")),
658 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
659 SUNXI_FUNCTION(0x0, "gpio_in"),
660 SUNXI_FUNCTION(0x1, "gpio_out")),
661 /* Hole */
662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
663 SUNXI_FUNCTION(0x0, "gpio_in"),
664 SUNXI_FUNCTION(0x1, "gpio_out")),
665 /* Hole */
666 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
667 SUNXI_FUNCTION(0x0, "gpio_in"),
668 SUNXI_FUNCTION(0x1, "gpio_out")),
669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
670 SUNXI_FUNCTION(0x0, "gpio_in"),
671 SUNXI_FUNCTION(0x1, "gpio_out")),
672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
673 SUNXI_FUNCTION(0x0, "gpio_in"),
674 SUNXI_FUNCTION(0x1, "gpio_out")),
675 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
676 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out")),
678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
679 SUNXI_FUNCTION(0x0, "gpio_in"),
680 SUNXI_FUNCTION(0x1, "gpio_out")),
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out")),
684 /* Hole */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
686 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out")),
688 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
689 SUNXI_FUNCTION(0x0, "gpio_in"),
690 SUNXI_FUNCTION(0x1, "gpio_out")),
691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
692 SUNXI_FUNCTION(0x0, "gpio_in"),
693 SUNXI_FUNCTION(0x1, "gpio_out")),
694 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
695 SUNXI_FUNCTION(0x0, "gpio_in"),
696 SUNXI_FUNCTION(0x1, "gpio_out")),
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out")),
700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
701 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out")),
703 /* Hole */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
705 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out")),
707 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
708 SUNXI_FUNCTION(0x0, "gpio_in"),
709 SUNXI_FUNCTION(0x1, "gpio_out")),
710 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
711 SUNXI_FUNCTION(0x0, "gpio_in"),
712 SUNXI_FUNCTION(0x1, "gpio_out")),
713 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
714 SUNXI_FUNCTION(0x0, "gpio_in"),
715 SUNXI_FUNCTION(0x1, "gpio_out")),
716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
717 SUNXI_FUNCTION(0x0, "gpio_in"),
718 SUNXI_FUNCTION(0x1, "gpio_out")),
719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
720 SUNXI_FUNCTION(0x0, "gpio_in"),
721 SUNXI_FUNCTION(0x1, "gpio_out")),
722 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
723 SUNXI_FUNCTION(0x0, "gpio_in"),
724 SUNXI_FUNCTION(0x1, "gpio_out")),
725 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out")),
728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
729 SUNXI_FUNCTION(0x0, "gpio_in"),
730 SUNXI_FUNCTION(0x1, "gpio_out")),
731 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
732 SUNXI_FUNCTION(0x0, "gpio_in"),
733 SUNXI_FUNCTION(0x1, "gpio_out")),
734 /* Hole */
735 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
736 SUNXI_FUNCTION(0x0, "gpio_in"),
737 SUNXI_FUNCTION(0x1, "gpio_out")),
738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
739 SUNXI_FUNCTION(0x0, "gpio_in"),
740 SUNXI_FUNCTION(0x1, "gpio_out")),
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out")),
744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
745 SUNXI_FUNCTION(0x0, "gpio_in"),
746 SUNXI_FUNCTION(0x1, "gpio_out")),
747 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
748 SUNXI_FUNCTION(0x0, "gpio_in"),
749 SUNXI_FUNCTION(0x1, "gpio_out")),
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out")),
753 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
754 SUNXI_FUNCTION(0x0, "gpio_in"),
755 SUNXI_FUNCTION(0x1, "gpio_out")),
756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
757 SUNXI_FUNCTION(0x0, "gpio_in"),
758 SUNXI_FUNCTION(0x1, "gpio_out")),
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out")),
762 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
763 SUNXI_FUNCTION(0x0, "gpio_in"),
764 SUNXI_FUNCTION(0x1, "gpio_out")),
765 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
766 SUNXI_FUNCTION(0x0, "gpio_in"),
767 SUNXI_FUNCTION(0x1, "gpio_out"),
768 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
770 SUNXI_FUNCTION(0x0, "gpio_in"),
771 SUNXI_FUNCTION(0x1, "gpio_out"),
772 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
773 /* Hole */
774 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
775 SUNXI_FUNCTION(0x0, "gpio_in"),
776 SUNXI_FUNCTION(0x1, "gpio_out")),
777 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
778 SUNXI_FUNCTION(0x0, "gpio_in"),
779 SUNXI_FUNCTION(0x1, "gpio_out")),
780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
781 SUNXI_FUNCTION(0x0, "gpio_in"),
782 SUNXI_FUNCTION(0x1, "gpio_out")),
783 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
784 SUNXI_FUNCTION(0x0, "gpio_in"),
785 SUNXI_FUNCTION(0x1, "gpio_out")),
786 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
787 SUNXI_FUNCTION(0x0, "gpio_in"),
788 SUNXI_FUNCTION(0x1, "gpio_out")),
789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
790 SUNXI_FUNCTION(0x0, "gpio_in"),
791 SUNXI_FUNCTION(0x1, "gpio_out")),
792 /* Hole */
793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
794 SUNXI_FUNCTION(0x0, "gpio_in"),
795 SUNXI_FUNCTION(0x1, "gpio_out")),
796 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
797 SUNXI_FUNCTION(0x0, "gpio_in"),
798 SUNXI_FUNCTION(0x1, "gpio_out")),
799 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
800 SUNXI_FUNCTION(0x0, "gpio_in"),
801 SUNXI_FUNCTION(0x1, "gpio_out")),
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
807 SUNXI_FUNCTION(0x0, "gpio_in"),
808 SUNXI_FUNCTION(0x1, "gpio_out"),
809 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
810 /* Hole */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out")),
814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out")),
817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out")),
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out")),
823};
824
825static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
826 .pins = sun4i_a10_pins,
827 .npins = ARRAY_SIZE(sun4i_a10_pins),
828};
829
830static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
831 .pins = sun5i_a13_pins,
832 .npins = ARRAY_SIZE(sun5i_a13_pins),
833};
834
835static struct sunxi_pinctrl_group *
836sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
837{
838 int i;
839
840 for (i = 0; i < pctl->ngroups; i++) {
841 struct sunxi_pinctrl_group *grp = pctl->groups + i;
842
843 if (!strcmp(grp->name, group))
844 return grp;
845 }
846
847 return NULL;
848}
849
850static struct sunxi_pinctrl_function *
851sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
852 const char *name)
853{
854 struct sunxi_pinctrl_function *func = pctl->functions;
855 int i;
856
857 for (i = 0; i < pctl->nfunctions; i++) {
858 if (!func[i].name)
859 break;
860
861 if (!strcmp(func[i].name, name))
862 return func + i;
863 }
864
865 return NULL;
866}
867
868static struct sunxi_desc_function *
869sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
870 const char *pin_name,
871 const char *func_name)
872{
873 int i;
874
875 for (i = 0; i < pctl->desc->npins; i++) {
876 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
877
878 if (!strcmp(pin->pin.name, pin_name)) {
879 struct sunxi_desc_function *func = pin->functions;
880
881 while (func->name) {
882 if (!strcmp(func->name, func_name))
883 return func;
884
885 func++;
886 }
887 }
888 }
889
890 return NULL;
891}
892
893static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
894{
895 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
896
897 return pctl->ngroups;
898}
899
900static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
901 unsigned group)
902{
903 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
904
905 return pctl->groups[group].name;
906}
907
908static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
909 unsigned group,
910 const unsigned **pins,
911 unsigned *num_pins)
912{
913 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
914
915 *pins = (unsigned *)&pctl->groups[group].pin;
916 *num_pins = 1;
917
918 return 0;
919}
920
921static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
922 struct device_node *node,
923 struct pinctrl_map **map,
924 unsigned *num_maps)
925{
926 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
927 unsigned long *pinconfig;
928 struct property *prop;
929 const char *function;
930 const char *group;
931 int ret, nmaps, i = 0;
932 u32 val;
933
934 *map = NULL;
935 *num_maps = 0;
936
937 ret = of_property_read_string(node, "allwinner,function", &function);
938 if (ret) {
939 dev_err(pctl->dev,
940 "missing allwinner,function property in node %s\n",
941 node->name);
942 return -EINVAL;
943 }
944
945 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
946 if (nmaps < 0) {
947 dev_err(pctl->dev,
948 "missing allwinner,pins property in node %s\n",
949 node->name);
950 return -EINVAL;
951 }
952
953 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
954 if (!map)
955 return -ENOMEM;
956
957 of_property_for_each_string(node, "allwinner,pins", prop, group) {
958 struct sunxi_pinctrl_group *grp =
959 sunxi_pinctrl_find_group_by_name(pctl, group);
960 int j = 0, configlen = 0;
961
962 if (!grp) {
963 dev_err(pctl->dev, "unknown pin %s", group);
964 continue;
965 }
966
967 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
968 grp->name,
969 function)) {
970 dev_err(pctl->dev, "unsupported function %s on pin %s",
971 function, group);
972 continue;
973 }
974
975 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
976 (*map)[i].data.mux.group = group;
977 (*map)[i].data.mux.function = function;
978
979 i++;
980
981 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
982 (*map)[i].data.configs.group_or_pin = group;
983
984 if (of_find_property(node, "allwinner,drive", NULL))
985 configlen++;
986 if (of_find_property(node, "allwinner,pull", NULL))
987 configlen++;
988
989 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
990
991 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
992 u16 strength = (val + 1) * 10;
993 pinconfig[j++] =
994 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
995 strength);
996 }
997
998 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
999 enum pin_config_param pull = PIN_CONFIG_END;
1000 if (val == 1)
1001 pull = PIN_CONFIG_BIAS_PULL_UP;
1002 else if (val == 2)
1003 pull = PIN_CONFIG_BIAS_PULL_DOWN;
1004 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
1005 }
1006
1007 (*map)[i].data.configs.configs = pinconfig;
1008 (*map)[i].data.configs.num_configs = configlen;
1009
1010 i++;
1011 }
1012
1013 *num_maps = nmaps;
1014
1015 return 0;
1016}
1017
1018static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
1019 struct pinctrl_map *map,
1020 unsigned num_maps)
1021{
1022 int i;
1023
1024 for (i = 0; i < num_maps; i++) {
1025 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
1026 kfree(map[i].data.configs.configs);
1027 }
1028
1029 kfree(map);
1030}
1031
1032static struct pinctrl_ops sunxi_pctrl_ops = {
1033 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
1034 .dt_free_map = sunxi_pctrl_dt_free_map,
1035 .get_groups_count = sunxi_pctrl_get_groups_count,
1036 .get_group_name = sunxi_pctrl_get_group_name,
1037 .get_group_pins = sunxi_pctrl_get_group_pins,
1038};
1039
1040static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
1041 unsigned group,
1042 unsigned long *config)
1043{
1044 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1045
1046 *config = pctl->groups[group].config;
1047
1048 return 0;
1049}
1050
1051static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
1052 unsigned group,
1053 unsigned long config)
1054{
1055 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1056 struct sunxi_pinctrl_group *g = &pctl->groups[group];
1057 u32 val, mask;
1058 u16 strength;
1059 u8 dlevel;
1060
1061 switch (pinconf_to_config_param(config)) {
1062 case PIN_CONFIG_DRIVE_STRENGTH:
1063 strength = pinconf_to_config_argument(config);
1064 if (strength > 40)
1065 return -EINVAL;
1066 /*
1067 * We convert from mA to what the register expects:
1068 * 0: 10mA
1069 * 1: 20mA
1070 * 2: 30mA
1071 * 3: 40mA
1072 */
1073 dlevel = strength / 10 - 1;
1074 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
1075 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
1076 writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
1077 pctl->membase + sunxi_dlevel_reg(g->pin));
1078 break;
1079 case PIN_CONFIG_BIAS_PULL_UP:
1080 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
1081 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
1082 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
1083 pctl->membase + sunxi_pull_reg(g->pin));
1084 break;
1085 case PIN_CONFIG_BIAS_PULL_DOWN:
1086 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
1087 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
1088 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
1089 pctl->membase + sunxi_pull_reg(g->pin));
1090 break;
1091 default:
1092 break;
1093 }
1094
1095 /* cache the config value */
1096 g->config = config;
1097
1098 return 0;
1099}
1100
1101static struct pinconf_ops sunxi_pconf_ops = {
1102 .pin_config_group_get = sunxi_pconf_group_get,
1103 .pin_config_group_set = sunxi_pconf_group_set,
1104};
1105
1106static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1107{
1108 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1109
1110 return pctl->nfunctions;
1111}
1112
1113static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
1114 unsigned function)
1115{
1116 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1117
1118 return pctl->functions[function].name;
1119}
1120
1121static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1122 unsigned function,
1123 const char * const **groups,
1124 unsigned * const num_groups)
1125{
1126 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1127
1128 *groups = pctl->functions[function].groups;
1129 *num_groups = pctl->functions[function].ngroups;
1130
1131 return 0;
1132}
1133
1134static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
1135 unsigned pin,
1136 u8 config)
1137{
1138 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1139
1140 u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
1141 u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
1142 writel((val & ~mask) | config << sunxi_mux_offset(pin),
1143 pctl->membase + sunxi_mux_reg(pin));
1144}
1145
1146static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
1147 unsigned function,
1148 unsigned group)
1149{
1150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1151 struct sunxi_pinctrl_group *g = pctl->groups + group;
1152 struct sunxi_pinctrl_function *func = pctl->functions + function;
1153 struct sunxi_desc_function *desc =
1154 sunxi_pinctrl_desc_find_function_by_name(pctl,
1155 g->name,
1156 func->name);
1157
1158 if (!desc)
1159 return -EINVAL;
1160
1161 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
1162
1163 return 0;
1164}
1165
1166static int
1167sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1168 struct pinctrl_gpio_range *range,
1169 unsigned offset,
1170 bool input)
1171{
1172 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1173 struct sunxi_desc_function *desc;
1174 char pin_name[SUNXI_PIN_NAME_MAX_LEN];
1175 const char *func;
1176 u8 bank, pin;
1177 int ret;
1178
1179 bank = (offset) / PINS_PER_BANK;
1180 pin = (offset) % PINS_PER_BANK;
1181
1182 ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin);
1183 if (!ret)
1184 goto error;
1185
1186 if (input)
1187 func = "gpio_in";
1188 else
1189 func = "gpio_out";
1190
1191 desc = sunxi_pinctrl_desc_find_function_by_name(pctl,
1192 pin_name,
1193 func);
1194 if (!desc) {
1195 ret = -EINVAL;
1196 goto error;
1197 }
1198
1199 sunxi_pmx_set(pctldev, offset, desc->muxval);
1200
1201 ret = 0;
1202
1203error:
1204 return ret;
1205}
1206
1207static struct pinmux_ops sunxi_pmx_ops = {
1208 .get_functions_count = sunxi_pmx_get_funcs_cnt,
1209 .get_function_name = sunxi_pmx_get_func_name,
1210 .get_function_groups = sunxi_pmx_get_func_groups,
1211 .enable = sunxi_pmx_enable,
1212 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
1213};
1214
1215static struct pinctrl_desc sunxi_pctrl_desc = {
1216 .confops = &sunxi_pconf_ops,
1217 .pctlops = &sunxi_pctrl_ops,
1218 .pmxops = &sunxi_pmx_ops,
1219};
1220
1221static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
1222{
1223 return pinctrl_request_gpio(chip->base + offset);
1224}
1225
1226static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
1227{
1228 pinctrl_free_gpio(chip->base + offset);
1229}
1230
1231static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
1232 unsigned offset)
1233{
1234 return pinctrl_gpio_direction_input(chip->base + offset);
1235}
1236
1237static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
1238{
1239 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
1240
1241 u32 reg = sunxi_data_reg(offset);
1242 u8 index = sunxi_data_offset(offset);
1243 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
1244
1245 return val;
1246}
1247
1248static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
1249 unsigned offset, int value)
1250{
1251 return pinctrl_gpio_direction_output(chip->base + offset);
1252}
1253
1254static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
1255 unsigned offset, int value)
1256{
1257 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
1258 u32 reg = sunxi_data_reg(offset);
1259 u8 index = sunxi_data_offset(offset);
1260
1261 writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
1262}
1263
1264static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
1265 const struct of_phandle_args *gpiospec,
1266 u32 *flags)
1267{
1268 int pin, base;
1269
1270 base = PINS_PER_BANK * gpiospec->args[0];
1271 pin = base + gpiospec->args[1];
1272
1273 if (pin > (gc->base + gc->ngpio))
1274 return -EINVAL;
1275
1276 if (flags)
1277 *flags = gpiospec->args[2];
1278
1279 return pin;
1280}
1281
1282static struct gpio_chip sunxi_pinctrl_gpio_chip = {
1283 .owner = THIS_MODULE,
1284 .request = sunxi_pinctrl_gpio_request,
1285 .free = sunxi_pinctrl_gpio_free,
1286 .direction_input = sunxi_pinctrl_gpio_direction_input,
1287 .direction_output = sunxi_pinctrl_gpio_direction_output,
1288 .get = sunxi_pinctrl_gpio_get,
1289 .set = sunxi_pinctrl_gpio_set,
1290 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
1291 .of_gpio_n_cells = 3,
1292 .can_sleep = 0,
1293};
1294
1295static struct of_device_id sunxi_pinctrl_match[] = {
1296 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
1297 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
1298 {}
1299};
1300MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
1301
1302static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1303 const char *name)
1304{
1305 struct sunxi_pinctrl_function *func = pctl->functions;
1306
1307 while (func->name) {
1308 /* function already there */
1309 if (strcmp(func->name, name) == 0) {
1310 func->ngroups++;
1311 return -EEXIST;
1312 }
1313 func++;
1314 }
1315
1316 func->name = name;
1317 func->ngroups = 1;
1318
1319 pctl->nfunctions++;
1320
1321 return 0;
1322}
1323
1324static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1325{
1326 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1327 int i;
1328
1329 pctl->ngroups = pctl->desc->npins;
1330
1331 /* Allocate groups */
1332 pctl->groups = devm_kzalloc(&pdev->dev,
1333 pctl->ngroups * sizeof(*pctl->groups),
1334 GFP_KERNEL);
1335 if (!pctl->groups)
1336 return -ENOMEM;
1337
1338 for (i = 0; i < pctl->desc->npins; i++) {
1339 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1340 struct sunxi_pinctrl_group *group = pctl->groups + i;
1341
1342 group->name = pin->pin.name;
1343 group->pin = pin->pin.number;
1344 }
1345
1346 /*
1347 * We suppose that we won't have any more functions than pins,
1348 * we'll reallocate that later anyway
1349 */
1350 pctl->functions = devm_kzalloc(&pdev->dev,
1351 pctl->desc->npins * sizeof(*pctl->functions),
1352 GFP_KERNEL);
1353 if (!pctl->functions)
1354 return -ENOMEM;
1355
1356 /* Count functions and their associated groups */
1357 for (i = 0; i < pctl->desc->npins; i++) {
1358 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1359 struct sunxi_desc_function *func = pin->functions;
1360
1361 while (func->name) {
1362 sunxi_pinctrl_add_function(pctl, func->name);
1363 func++;
1364 }
1365 }
1366
1367 pctl->functions = krealloc(pctl->functions,
1368 pctl->nfunctions * sizeof(*pctl->functions),
1369 GFP_KERNEL);
1370
1371 for (i = 0; i < pctl->desc->npins; i++) {
1372 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1373 struct sunxi_desc_function *func = pin->functions;
1374
1375 while (func->name) {
1376 struct sunxi_pinctrl_function *func_item;
1377 const char **func_grp;
1378
1379 func_item = sunxi_pinctrl_find_function_by_name(pctl,
1380 func->name);
1381 if (!func_item)
1382 return -EINVAL;
1383
1384 if (!func_item->groups) {
1385 func_item->groups =
1386 devm_kzalloc(&pdev->dev,
1387 func_item->ngroups * sizeof(*func_item->groups),
1388 GFP_KERNEL);
1389 if (!func_item->groups)
1390 return -ENOMEM;
1391 }
1392
1393 func_grp = func_item->groups;
1394 while (*func_grp)
1395 func_grp++;
1396
1397 *func_grp = pin->pin.name;
1398 func++;
1399 }
1400 }
1401
1402 return 0;
1403}
1404
1405static int sunxi_pinctrl_probe(struct platform_device *pdev)
1406{
1407 struct device_node *node = pdev->dev.of_node;
1408 const struct of_device_id *device;
1409 struct pinctrl_pin_desc *pins;
1410 struct sunxi_pinctrl *pctl;
1411 int i, ret, last_pin;
1412
1413 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1414 if (!pctl)
1415 return -ENOMEM;
1416 platform_set_drvdata(pdev, pctl);
1417
1418 pctl->membase = of_iomap(node, 0);
1419 if (!pctl->membase)
1420 return -ENOMEM;
1421
1422 device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
1423 if (!device)
1424 return -ENODEV;
1425
1426 pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
1427
1428 ret = sunxi_pinctrl_build_state(pdev);
1429 if (ret) {
1430 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1431 return ret;
1432 }
1433
1434 pins = devm_kzalloc(&pdev->dev,
1435 pctl->desc->npins * sizeof(*pins),
1436 GFP_KERNEL);
1437 if (!pins)
1438 return -ENOMEM;
1439
1440 for (i = 0; i < pctl->desc->npins; i++)
1441 pins[i] = pctl->desc->pins[i].pin;
1442
1443 sunxi_pctrl_desc.name = dev_name(&pdev->dev);
1444 sunxi_pctrl_desc.owner = THIS_MODULE;
1445 sunxi_pctrl_desc.pins = pins;
1446 sunxi_pctrl_desc.npins = pctl->desc->npins;
1447 pctl->dev = &pdev->dev;
1448 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
1449 &pdev->dev, pctl);
1450 if (!pctl->pctl_dev) {
1451 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1452 return -EINVAL;
1453 }
1454
1455 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1456 if (!pctl->chip) {
1457 ret = -ENOMEM;
1458 goto pinctrl_error;
1459 }
1460
1461 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1462 pctl->chip = &sunxi_pinctrl_gpio_chip;
1463 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
1464 pctl->chip->label = dev_name(&pdev->dev);
1465 pctl->chip->dev = &pdev->dev;
1466 pctl->chip->base = 0;
1467
1468 ret = gpiochip_add(pctl->chip);
1469 if (ret)
1470 goto pinctrl_error;
1471
1472 for (i = 0; i < pctl->desc->npins; i++) {
1473 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1474
1475 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1476 pin->pin.number,
1477 pin->pin.number, 1);
1478 if (ret)
1479 goto gpiochip_error;
1480 }
1481
1482 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1483
1484 return 0;
1485
1486gpiochip_error:
1487 ret = gpiochip_remove(pctl->chip);
1488pinctrl_error:
1489 pinctrl_unregister(pctl->pctl_dev);
1490 return ret;
1491}
1492
1493static struct platform_driver sunxi_pinctrl_driver = {
1494 .probe = sunxi_pinctrl_probe,
1495 .driver = {
1496 .name = "sunxi-pinctrl",
1497 .owner = THIS_MODULE,
1498 .of_match_table = sunxi_pinctrl_match,
1499 },
1500};
1501module_platform_driver(sunxi_pinctrl_driver);
1502
1503MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1504MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
1505MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
new file mode 100644
index 000000000000..e921621059ce
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -0,0 +1,478 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_H
14#define __PINCTRL_SUNXI_H
15
16#include <linux/kernel.h>
17
18#define PA_BASE 0
19#define PB_BASE 32
20#define PC_BASE 64
21#define PD_BASE 96
22#define PE_BASE 128
23#define PF_BASE 160
24#define PG_BASE 192
25#define PH_BASE 224
26#define PI_BASE 256
27
28#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0")
29#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1")
30#define SUNXI_PINCTRL_PIN_PA2 PINCTRL_PIN(PA_BASE + 2, "PA2")
31#define SUNXI_PINCTRL_PIN_PA3 PINCTRL_PIN(PA_BASE + 3, "PA3")
32#define SUNXI_PINCTRL_PIN_PA4 PINCTRL_PIN(PA_BASE + 4, "PA4")
33#define SUNXI_PINCTRL_PIN_PA5 PINCTRL_PIN(PA_BASE + 5, "PA5")
34#define SUNXI_PINCTRL_PIN_PA6 PINCTRL_PIN(PA_BASE + 6, "PA6")
35#define SUNXI_PINCTRL_PIN_PA7 PINCTRL_PIN(PA_BASE + 7, "PA7")
36#define SUNXI_PINCTRL_PIN_PA8 PINCTRL_PIN(PA_BASE + 8, "PA8")
37#define SUNXI_PINCTRL_PIN_PA9 PINCTRL_PIN(PA_BASE + 9, "PA9")
38#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10")
39#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11")
40#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12")
41#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13")
42#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14")
43#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15")
44#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16")
45#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17")
46#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18")
47#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19")
48#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20")
49#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21")
50#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22")
51#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23")
52#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24")
53#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25")
54#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26")
55#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27")
56#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28")
57#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29")
58#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30")
59#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31")
60
61#define SUNXI_PINCTRL_PIN_PB0 PINCTRL_PIN(PB_BASE + 0, "PB0")
62#define SUNXI_PINCTRL_PIN_PB1 PINCTRL_PIN(PB_BASE + 1, "PB1")
63#define SUNXI_PINCTRL_PIN_PB2 PINCTRL_PIN(PB_BASE + 2, "PB2")
64#define SUNXI_PINCTRL_PIN_PB3 PINCTRL_PIN(PB_BASE + 3, "PB3")
65#define SUNXI_PINCTRL_PIN_PB4 PINCTRL_PIN(PB_BASE + 4, "PB4")
66#define SUNXI_PINCTRL_PIN_PB5 PINCTRL_PIN(PB_BASE + 5, "PB5")
67#define SUNXI_PINCTRL_PIN_PB6 PINCTRL_PIN(PB_BASE + 6, "PB6")
68#define SUNXI_PINCTRL_PIN_PB7 PINCTRL_PIN(PB_BASE + 7, "PB7")
69#define SUNXI_PINCTRL_PIN_PB8 PINCTRL_PIN(PB_BASE + 8, "PB8")
70#define SUNXI_PINCTRL_PIN_PB9 PINCTRL_PIN(PB_BASE + 9, "PB9")
71#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10")
72#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11")
73#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12")
74#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13")
75#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14")
76#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15")
77#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16")
78#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17")
79#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18")
80#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19")
81#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20")
82#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21")
83#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22")
84#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23")
85#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24")
86#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25")
87#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26")
88#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27")
89#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28")
90#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29")
91#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30")
92#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31")
93
94#define SUNXI_PINCTRL_PIN_PC0 PINCTRL_PIN(PC_BASE + 0, "PC0")
95#define SUNXI_PINCTRL_PIN_PC1 PINCTRL_PIN(PC_BASE + 1, "PC1")
96#define SUNXI_PINCTRL_PIN_PC2 PINCTRL_PIN(PC_BASE + 2, "PC2")
97#define SUNXI_PINCTRL_PIN_PC3 PINCTRL_PIN(PC_BASE + 3, "PC3")
98#define SUNXI_PINCTRL_PIN_PC4 PINCTRL_PIN(PC_BASE + 4, "PC4")
99#define SUNXI_PINCTRL_PIN_PC5 PINCTRL_PIN(PC_BASE + 5, "PC5")
100#define SUNXI_PINCTRL_PIN_PC6 PINCTRL_PIN(PC_BASE + 6, "PC6")
101#define SUNXI_PINCTRL_PIN_PC7 PINCTRL_PIN(PC_BASE + 7, "PC7")
102#define SUNXI_PINCTRL_PIN_PC8 PINCTRL_PIN(PC_BASE + 8, "PC8")
103#define SUNXI_PINCTRL_PIN_PC9 PINCTRL_PIN(PC_BASE + 9, "PC9")
104#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10")
105#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11")
106#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12")
107#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13")
108#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14")
109#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15")
110#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16")
111#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17")
112#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18")
113#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19")
114#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20")
115#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21")
116#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22")
117#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23")
118#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24")
119#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25")
120#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26")
121#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27")
122#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28")
123#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29")
124#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30")
125#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31")
126
127#define SUNXI_PINCTRL_PIN_PD0 PINCTRL_PIN(PD_BASE + 0, "PD0")
128#define SUNXI_PINCTRL_PIN_PD1 PINCTRL_PIN(PD_BASE + 1, "PD1")
129#define SUNXI_PINCTRL_PIN_PD2 PINCTRL_PIN(PD_BASE + 2, "PD2")
130#define SUNXI_PINCTRL_PIN_PD3 PINCTRL_PIN(PD_BASE + 3, "PD3")
131#define SUNXI_PINCTRL_PIN_PD4 PINCTRL_PIN(PD_BASE + 4, "PD4")
132#define SUNXI_PINCTRL_PIN_PD5 PINCTRL_PIN(PD_BASE + 5, "PD5")
133#define SUNXI_PINCTRL_PIN_PD6 PINCTRL_PIN(PD_BASE + 6, "PD6")
134#define SUNXI_PINCTRL_PIN_PD7 PINCTRL_PIN(PD_BASE + 7, "PD7")
135#define SUNXI_PINCTRL_PIN_PD8 PINCTRL_PIN(PD_BASE + 8, "PD8")
136#define SUNXI_PINCTRL_PIN_PD9 PINCTRL_PIN(PD_BASE + 9, "PD9")
137#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10")
138#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11")
139#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12")
140#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13")
141#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14")
142#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15")
143#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16")
144#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17")
145#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18")
146#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19")
147#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20")
148#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21")
149#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22")
150#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23")
151#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24")
152#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25")
153#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26")
154#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27")
155#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28")
156#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29")
157#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30")
158#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31")
159
160#define SUNXI_PINCTRL_PIN_PE0 PINCTRL_PIN(PE_BASE + 0, "PE0")
161#define SUNXI_PINCTRL_PIN_PE1 PINCTRL_PIN(PE_BASE + 1, "PE1")
162#define SUNXI_PINCTRL_PIN_PE2 PINCTRL_PIN(PE_BASE + 2, "PE2")
163#define SUNXI_PINCTRL_PIN_PE3 PINCTRL_PIN(PE_BASE + 3, "PE3")
164#define SUNXI_PINCTRL_PIN_PE4 PINCTRL_PIN(PE_BASE + 4, "PE4")
165#define SUNXI_PINCTRL_PIN_PE5 PINCTRL_PIN(PE_BASE + 5, "PE5")
166#define SUNXI_PINCTRL_PIN_PE6 PINCTRL_PIN(PE_BASE + 6, "PE6")
167#define SUNXI_PINCTRL_PIN_PE7 PINCTRL_PIN(PE_BASE + 7, "PE7")
168#define SUNXI_PINCTRL_PIN_PE8 PINCTRL_PIN(PE_BASE + 8, "PE8")
169#define SUNXI_PINCTRL_PIN_PE9 PINCTRL_PIN(PE_BASE + 9, "PE9")
170#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10")
171#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11")
172#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12")
173#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13")
174#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14")
175#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15")
176#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16")
177#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17")
178#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18")
179#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19")
180#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20")
181#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21")
182#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22")
183#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23")
184#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24")
185#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25")
186#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26")
187#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27")
188#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28")
189#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29")
190#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30")
191#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31")
192
193#define SUNXI_PINCTRL_PIN_PF0 PINCTRL_PIN(PF_BASE + 0, "PF0")
194#define SUNXI_PINCTRL_PIN_PF1 PINCTRL_PIN(PF_BASE + 1, "PF1")
195#define SUNXI_PINCTRL_PIN_PF2 PINCTRL_PIN(PF_BASE + 2, "PF2")
196#define SUNXI_PINCTRL_PIN_PF3 PINCTRL_PIN(PF_BASE + 3, "PF3")
197#define SUNXI_PINCTRL_PIN_PF4 PINCTRL_PIN(PF_BASE + 4, "PF4")
198#define SUNXI_PINCTRL_PIN_PF5 PINCTRL_PIN(PF_BASE + 5, "PF5")
199#define SUNXI_PINCTRL_PIN_PF6 PINCTRL_PIN(PF_BASE + 6, "PF6")
200#define SUNXI_PINCTRL_PIN_PF7 PINCTRL_PIN(PF_BASE + 7, "PF7")
201#define SUNXI_PINCTRL_PIN_PF8 PINCTRL_PIN(PF_BASE + 8, "PF8")
202#define SUNXI_PINCTRL_PIN_PF9 PINCTRL_PIN(PF_BASE + 9, "PF9")
203#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10")
204#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11")
205#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12")
206#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13")
207#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14")
208#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15")
209#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16")
210#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17")
211#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18")
212#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19")
213#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20")
214#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21")
215#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22")
216#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23")
217#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24")
218#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25")
219#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26")
220#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27")
221#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28")
222#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29")
223#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30")
224#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31")
225
226#define SUNXI_PINCTRL_PIN_PG0 PINCTRL_PIN(PG_BASE + 0, "PG0")
227#define SUNXI_PINCTRL_PIN_PG1 PINCTRL_PIN(PG_BASE + 1, "PG1")
228#define SUNXI_PINCTRL_PIN_PG2 PINCTRL_PIN(PG_BASE + 2, "PG2")
229#define SUNXI_PINCTRL_PIN_PG3 PINCTRL_PIN(PG_BASE + 3, "PG3")
230#define SUNXI_PINCTRL_PIN_PG4 PINCTRL_PIN(PG_BASE + 4, "PG4")
231#define SUNXI_PINCTRL_PIN_PG5 PINCTRL_PIN(PG_BASE + 5, "PG5")
232#define SUNXI_PINCTRL_PIN_PG6 PINCTRL_PIN(PG_BASE + 6, "PG6")
233#define SUNXI_PINCTRL_PIN_PG7 PINCTRL_PIN(PG_BASE + 7, "PG7")
234#define SUNXI_PINCTRL_PIN_PG8 PINCTRL_PIN(PG_BASE + 8, "PG8")
235#define SUNXI_PINCTRL_PIN_PG9 PINCTRL_PIN(PG_BASE + 9, "PG9")
236#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10")
237#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11")
238#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12")
239#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13")
240#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14")
241#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15")
242#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16")
243#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17")
244#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18")
245#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19")
246#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20")
247#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21")
248#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22")
249#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23")
250#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24")
251#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25")
252#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26")
253#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27")
254#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28")
255#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29")
256#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30")
257#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31")
258
259#define SUNXI_PINCTRL_PIN_PH0 PINCTRL_PIN(PH_BASE + 0, "PH0")
260#define SUNXI_PINCTRL_PIN_PH1 PINCTRL_PIN(PH_BASE + 1, "PH1")
261#define SUNXI_PINCTRL_PIN_PH2 PINCTRL_PIN(PH_BASE + 2, "PH2")
262#define SUNXI_PINCTRL_PIN_PH3 PINCTRL_PIN(PH_BASE + 3, "PH3")
263#define SUNXI_PINCTRL_PIN_PH4 PINCTRL_PIN(PH_BASE + 4, "PH4")
264#define SUNXI_PINCTRL_PIN_PH5 PINCTRL_PIN(PH_BASE + 5, "PH5")
265#define SUNXI_PINCTRL_PIN_PH6 PINCTRL_PIN(PH_BASE + 6, "PH6")
266#define SUNXI_PINCTRL_PIN_PH7 PINCTRL_PIN(PH_BASE + 7, "PH7")
267#define SUNXI_PINCTRL_PIN_PH8 PINCTRL_PIN(PH_BASE + 8, "PH8")
268#define SUNXI_PINCTRL_PIN_PH9 PINCTRL_PIN(PH_BASE + 9, "PH9")
269#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10")
270#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11")
271#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12")
272#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13")
273#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14")
274#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15")
275#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16")
276#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17")
277#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18")
278#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19")
279#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20")
280#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21")
281#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22")
282#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23")
283#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24")
284#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25")
285#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26")
286#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27")
287#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28")
288#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29")
289#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30")
290#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31")
291
292#define SUNXI_PINCTRL_PIN_PI0 PINCTRL_PIN(PI_BASE + 0, "PI0")
293#define SUNXI_PINCTRL_PIN_PI1 PINCTRL_PIN(PI_BASE + 1, "PI1")
294#define SUNXI_PINCTRL_PIN_PI2 PINCTRL_PIN(PI_BASE + 2, "PI2")
295#define SUNXI_PINCTRL_PIN_PI3 PINCTRL_PIN(PI_BASE + 3, "PI3")
296#define SUNXI_PINCTRL_PIN_PI4 PINCTRL_PIN(PI_BASE + 4, "PI4")
297#define SUNXI_PINCTRL_PIN_PI5 PINCTRL_PIN(PI_BASE + 5, "PI5")
298#define SUNXI_PINCTRL_PIN_PI6 PINCTRL_PIN(PI_BASE + 6, "PI6")
299#define SUNXI_PINCTRL_PIN_PI7 PINCTRL_PIN(PI_BASE + 7, "PI7")
300#define SUNXI_PINCTRL_PIN_PI8 PINCTRL_PIN(PI_BASE + 8, "PI8")
301#define SUNXI_PINCTRL_PIN_PI9 PINCTRL_PIN(PI_BASE + 9, "PI9")
302#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10")
303#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11")
304#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12")
305#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13")
306#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14")
307#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15")
308#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16")
309#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17")
310#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18")
311#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19")
312#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20")
313#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21")
314#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22")
315#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23")
316#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24")
317#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25")
318#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26")
319#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27")
320#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28")
321#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29")
322#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
323#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
324
325#define SUNXI_PIN_NAME_MAX_LEN 5
326
327#define BANK_MEM_SIZE 0x24
328#define MUX_REGS_OFFSET 0x0
329#define DATA_REGS_OFFSET 0x10
330#define DLEVEL_REGS_OFFSET 0x14
331#define PULL_REGS_OFFSET 0x1c
332
333#define PINS_PER_BANK 32
334#define MUX_PINS_PER_REG 8
335#define MUX_PINS_BITS 4
336#define MUX_PINS_MASK 0x0f
337#define DATA_PINS_PER_REG 32
338#define DATA_PINS_BITS 1
339#define DATA_PINS_MASK 0x01
340#define DLEVEL_PINS_PER_REG 16
341#define DLEVEL_PINS_BITS 2
342#define DLEVEL_PINS_MASK 0x03
343#define PULL_PINS_PER_REG 16
344#define PULL_PINS_BITS 2
345#define PULL_PINS_MASK 0x03
346
347struct sunxi_desc_function {
348 const char *name;
349 u8 muxval;
350};
351
352struct sunxi_desc_pin {
353 struct pinctrl_pin_desc pin;
354 struct sunxi_desc_function *functions;
355};
356
357struct sunxi_pinctrl_desc {
358 const struct sunxi_desc_pin *pins;
359 int npins;
360 struct pinctrl_gpio_range *ranges;
361 int nranges;
362};
363
364struct sunxi_pinctrl_function {
365 const char *name;
366 const char **groups;
367 unsigned ngroups;
368};
369
370struct sunxi_pinctrl_group {
371 const char *name;
372 unsigned long config;
373 unsigned pin;
374};
375
376struct sunxi_pinctrl {
377 void __iomem *membase;
378 struct gpio_chip *chip;
379 struct sunxi_pinctrl_desc *desc;
380 struct device *dev;
381 struct sunxi_pinctrl_function *functions;
382 unsigned nfunctions;
383 struct sunxi_pinctrl_group *groups;
384 unsigned ngroups;
385 struct pinctrl_dev *pctl_dev;
386};
387
388#define SUNXI_PIN(_pin, ...) \
389 { \
390 .pin = _pin, \
391 .functions = (struct sunxi_desc_function[]){ \
392 __VA_ARGS__, { } }, \
393 }
394
395#define SUNXI_FUNCTION(_val, _name) \
396 { \
397 .name = _name, \
398 .muxval = _val, \
399 }
400
401/*
402 * The sunXi PIO registers are organized as is:
403 * 0x00 - 0x0c Muxing values.
404 * 8 pins per register, each pin having a 4bits value
405 * 0x10 Pin values
406 * 32 bits per register, each pin corresponding to one bit
407 * 0x14 - 0x18 Drive level
408 * 16 pins per register, each pin having a 2bits value
409 * 0x1c - 0x20 Pull-Up values
410 * 16 pins per register, each pin having a 2bits value
411 *
412 * This is for the first bank. Each bank will have the same layout,
413 * with an offset being a multiple of 0x24.
414 *
415 * The following functions calculate from the pin number the register
416 * and the bit offset that we should access.
417 */
418static inline u32 sunxi_mux_reg(u16 pin)
419{
420 u8 bank = pin / PINS_PER_BANK;
421 u32 offset = bank * BANK_MEM_SIZE;
422 offset += MUX_REGS_OFFSET;
423 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
424 return round_down(offset, 4);
425}
426
427static inline u32 sunxi_mux_offset(u16 pin)
428{
429 u32 pin_num = pin % MUX_PINS_PER_REG;
430 return pin_num * MUX_PINS_BITS;
431}
432
433static inline u32 sunxi_data_reg(u16 pin)
434{
435 u8 bank = pin / PINS_PER_BANK;
436 u32 offset = bank * BANK_MEM_SIZE;
437 offset += DATA_REGS_OFFSET;
438 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
439 return round_down(offset, 4);
440}
441
442static inline u32 sunxi_data_offset(u16 pin)
443{
444 u32 pin_num = pin % DATA_PINS_PER_REG;
445 return pin_num * DATA_PINS_BITS;
446}
447
448static inline u32 sunxi_dlevel_reg(u16 pin)
449{
450 u8 bank = pin / PINS_PER_BANK;
451 u32 offset = bank * BANK_MEM_SIZE;
452 offset += DLEVEL_REGS_OFFSET;
453 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
454 return round_down(offset, 4);
455}
456
457static inline u32 sunxi_dlevel_offset(u16 pin)
458{
459 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
460 return pin_num * DLEVEL_PINS_BITS;
461}
462
463static inline u32 sunxi_pull_reg(u16 pin)
464{
465 u8 bank = pin / PINS_PER_BANK;
466 u32 offset = bank * BANK_MEM_SIZE;
467 offset += PULL_REGS_OFFSET;
468 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
469 return round_down(offset, 4);
470}
471
472static inline u32 sunxi_pull_offset(u16 pin)
473{
474 u32 pin_num = pin % PULL_PINS_PER_REG;
475 return pin_num * PULL_PINS_BITS;
476}
477
478#endif /* __PINCTRL_SUNXI_H */
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index ae1e4bb3259d..f195d77a3572 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -201,6 +201,7 @@ static const struct cfg_param {
201 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, 201 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
202 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 202 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
203 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 203 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
204 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
204 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 205 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
205 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 206 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
206 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 207 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
@@ -208,6 +209,7 @@ static const struct cfg_param {
208 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, 209 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
209 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, 210 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
210 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, 211 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
212 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
211}; 213};
212 214
213static int tegra_pinctrl_dt_subnode_to_map(struct device *dev, 215static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
@@ -450,6 +452,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
450 *bit = g->ioreset_bit; 452 *bit = g->ioreset_bit;
451 *width = 1; 453 *width = 1;
452 break; 454 break;
455 case TEGRA_PINCONF_PARAM_RCV_SEL:
456 *bank = g->rcv_sel_bank;
457 *reg = g->rcv_sel_reg;
458 *bit = g->rcv_sel_bit;
459 *width = 1;
460 break;
453 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 461 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
454 *bank = g->drv_bank; 462 *bank = g->drv_bank;
455 *reg = g->drv_reg; 463 *reg = g->drv_reg;
@@ -492,6 +500,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
492 *bit = g->slwr_bit; 500 *bit = g->slwr_bit;
493 *width = g->slwr_width; 501 *width = g->slwr_width;
494 break; 502 break;
503 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
504 *bank = g->drvtype_bank;
505 *reg = g->drvtype_reg;
506 *bit = g->drvtype_bit;
507 *width = 2;
508 break;
495 default: 509 default:
496 dev_err(pmx->dev, "Invalid config param %04x\n", param); 510 dev_err(pmx->dev, "Invalid config param %04x\n", param);
497 return -ENOTSUPP; 511 return -ENOTSUPP;
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 62e380965c68..817f7061dc4c 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -30,6 +30,8 @@ enum tegra_pinconf_param {
30 /* argument: Boolean */ 30 /* argument: Boolean */
31 TEGRA_PINCONF_PARAM_IORESET, 31 TEGRA_PINCONF_PARAM_IORESET,
32 /* argument: Boolean */ 32 /* argument: Boolean */
33 TEGRA_PINCONF_PARAM_RCV_SEL,
34 /* argument: Boolean */
33 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 35 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
34 /* argument: Boolean */ 36 /* argument: Boolean */
35 TEGRA_PINCONF_PARAM_SCHMITT, 37 TEGRA_PINCONF_PARAM_SCHMITT,
@@ -43,6 +45,8 @@ enum tegra_pinconf_param {
43 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 45 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
44 /* argument: Integer, range is HW-dependant */ 46 /* argument: Integer, range is HW-dependant */
45 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 47 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
48 /* argument: Integer, range is HW-dependant */
49 TEGRA_PINCONF_PARAM_DRIVE_TYPE,
46}; 50};
47 51
48enum tegra_pinconf_pull { 52enum tegra_pinconf_pull {
@@ -95,6 +99,9 @@ struct tegra_function {
95 * @ioreset_reg: IO reset register offset. -1 if unsupported. 99 * @ioreset_reg: IO reset register offset. -1 if unsupported.
96 * @ioreset_bank: IO reset register bank. 0 if unsupported. 100 * @ioreset_bank: IO reset register bank. 0 if unsupported.
97 * @ioreset_bit: IO reset register bit. 0 if unsupported. 101 * @ioreset_bit: IO reset register bit. 0 if unsupported.
102 * @rcv_sel_reg: Receiver select offset. -1 if unsupported.
103 * @rcv_sel_bank: Receiver select bank. 0 if unsupported.
104 * @rcv_sel_bit: Receiver select bit. 0 if unsupported.
98 * @drv_reg: Drive fields register offset. -1 if unsupported. 105 * @drv_reg: Drive fields register offset. -1 if unsupported.
99 * This register contains the hsm, schmitt, lpmd, drvdn, 106 * This register contains the hsm, schmitt, lpmd, drvdn,
100 * drvup, slwr, and slwf parameters. 107 * drvup, slwr, and slwf parameters.
@@ -110,6 +117,9 @@ struct tegra_function {
110 * @slwr_width: Slew Rising field width. 0 if unsupported. 117 * @slwr_width: Slew Rising field width. 0 if unsupported.
111 * @slwf_bit: Slew Falling register bit. 0 if unsupported. 118 * @slwf_bit: Slew Falling register bit. 0 if unsupported.
112 * @slwf_width: Slew Falling field width. 0 if unsupported. 119 * @slwf_width: Slew Falling field width. 0 if unsupported.
120 * @drvtype_reg: Drive type fields register offset. -1 if unsupported.
121 * @drvtype_bank: Drive type fields register bank. 0 if unsupported.
122 * @drvtype_bit: Drive type register bit. 0 if unsupported.
113 * 123 *
114 * A representation of a group of pins (possibly just one pin) in the Tegra 124 * A representation of a group of pins (possibly just one pin) in the Tegra
115 * pin controller. Each group allows some parameter or parameters to be 125 * pin controller. Each group allows some parameter or parameters to be
@@ -131,15 +141,19 @@ struct tegra_pingroup {
131 s16 odrain_reg; 141 s16 odrain_reg;
132 s16 lock_reg; 142 s16 lock_reg;
133 s16 ioreset_reg; 143 s16 ioreset_reg;
144 s16 rcv_sel_reg;
134 s16 drv_reg; 145 s16 drv_reg;
146 s16 drvtype_reg;
135 u32 mux_bank:2; 147 u32 mux_bank:2;
136 u32 pupd_bank:2; 148 u32 pupd_bank:2;
137 u32 tri_bank:2; 149 u32 tri_bank:2;
138 u32 einput_bank:2; 150 u32 einput_bank:2;
139 u32 odrain_bank:2; 151 u32 odrain_bank:2;
140 u32 ioreset_bank:2; 152 u32 ioreset_bank:2;
153 u32 rcv_sel_bank:2;
141 u32 lock_bank:2; 154 u32 lock_bank:2;
142 u32 drv_bank:2; 155 u32 drv_bank:2;
156 u32 drvtype_bank:2;
143 u32 mux_bit:5; 157 u32 mux_bit:5;
144 u32 pupd_bit:5; 158 u32 pupd_bit:5;
145 u32 tri_bit:5; 159 u32 tri_bit:5;
@@ -147,6 +161,7 @@ struct tegra_pingroup {
147 u32 odrain_bit:5; 161 u32 odrain_bit:5;
148 u32 lock_bit:5; 162 u32 lock_bit:5;
149 u32 ioreset_bit:5; 163 u32 ioreset_bit:5;
164 u32 rcv_sel_bit:5;
150 u32 hsm_bit:5; 165 u32 hsm_bit:5;
151 u32 schmitt_bit:5; 166 u32 schmitt_bit:5;
152 u32 lpmd_bit:5; 167 u32 lpmd_bit:5;
@@ -154,6 +169,7 @@ struct tegra_pingroup {
154 u32 drvup_bit:5; 169 u32 drvup_bit:5;
155 u32 slwr_bit:5; 170 u32 slwr_bit:5;
156 u32 slwf_bit:5; 171 u32 slwf_bit:5;
172 u32 drvtype_bit:5;
157 u32 drvdn_width:6; 173 u32 drvdn_width:6;
158 u32 drvup_width:6; 174 u32 drvup_width:6;
159 u32 slwr_width:6; 175 u32 slwr_width:6;
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
new file mode 100644
index 000000000000..622c4854977e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -0,0 +1,2769 @@
1/*
2 * Pinctrl data and driver for the NVIDIA Tegra114 pinmux
3 *
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Arthur: Pritesh Raithatha <praithatha@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26
27#include "pinctrl-tegra.h"
28
29/*
30 * Most pins affected by the pinmux can also be GPIOs. Define these first.
31 * These must match how the GPIO driver names/numbers its pins.
32 */
33#define _GPIO(offset) (offset)
34
35#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
36#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
37#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
38#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
39#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
40#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
41#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
42#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
43#define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
44#define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
45#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
46#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
47#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
48#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
49#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
50#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
51#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
52#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
53#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
54#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
55#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
56#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
57#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
58#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
59#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
60#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
61#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
62#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
63#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
64#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
65#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
66#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
67#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
68#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
69#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
70#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
71#define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
72#define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
73#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
74#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
75#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
76#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
77#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
78#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
79#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
80#define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75)
81#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
82#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
83#define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
84#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
85#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
86#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
87#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
88#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
89#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
90#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
91#define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
92#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
93#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
94#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
95#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
96#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
97#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
98#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
99#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
100#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
101#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
102#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
103#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
104#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
105#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
106#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
107#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
108#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
109#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
110#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
111#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
112#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
113#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
114#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
115#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
116#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
117#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
118#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
119#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
120#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
121#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
122#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
123#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
124#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
125#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
126#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
127#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
128#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
129#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
130#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
131#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
132#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
133#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
134#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
135#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
136#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
137#define TEGRA_PIN_PU0 _GPIO(160)
138#define TEGRA_PIN_PU1 _GPIO(161)
139#define TEGRA_PIN_PU2 _GPIO(162)
140#define TEGRA_PIN_PU3 _GPIO(163)
141#define TEGRA_PIN_PU4 _GPIO(164)
142#define TEGRA_PIN_PU5 _GPIO(165)
143#define TEGRA_PIN_PU6 _GPIO(166)
144#define TEGRA_PIN_PV0 _GPIO(168)
145#define TEGRA_PIN_PV1 _GPIO(169)
146#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
147#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
148#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
149#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
150#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
151#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
152#define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
153#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
154#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
155#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
156#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
157#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
158#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
159#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
160#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
161#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
162#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
163#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
164#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
165#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
166#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
167#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
168#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
169#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
170#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
171#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
172#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
173#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
174#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
175#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
176#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
177#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
178#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
179#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
180#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
181#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
182#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
183#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
184#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
185#define TEGRA_PIN_PBB0 _GPIO(216)
186#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
187#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
188#define TEGRA_PIN_PBB3 _GPIO(219)
189#define TEGRA_PIN_PBB4 _GPIO(220)
190#define TEGRA_PIN_PBB5 _GPIO(221)
191#define TEGRA_PIN_PBB6 _GPIO(222)
192#define TEGRA_PIN_PBB7 _GPIO(223)
193#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
194#define TEGRA_PIN_PCC1 _GPIO(225)
195#define TEGRA_PIN_PCC2 _GPIO(226)
196#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
197#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
198#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
199#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
200#define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
201#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
202#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
203#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
204
205/* All non-GPIO pins follow */
206#define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
207#define _PIN(offset) (NUM_GPIOS + (offset))
208
209/* Non-GPIO pins */
210#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
211#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
212#define TEGRA_PIN_PWR_INT_N _PIN(2)
213#define TEGRA_PIN_RESET_OUT_N _PIN(3)
214#define TEGRA_PIN_OWR _PIN(4)
215
216static const struct pinctrl_pin_desc tegra114_pins[] = {
217 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
218 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
219 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
220 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
221 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
222 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
223 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
224 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
225 PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
226 PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
227 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
228 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
229 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
230 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
231 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
232 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
233 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
234 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
235 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
236 PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
237 PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
238 PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
239 PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
240 PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
241 PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
242 PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
243 PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
244 PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
245 PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
246 PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
247 PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
248 PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
249 PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
250 PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
251 PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
252 PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
253 PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
254 PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
255 PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
256 PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
257 PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
258 PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
259 PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
260 PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
261 PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
262 PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
263 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
264 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
265 PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
266 PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
267 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
268 PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
269 PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
270 PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
271 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
272 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
273 PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
274 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
275 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
276 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
277 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
278 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
279 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
280 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
281 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
282 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
283 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
284 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
285 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
286 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
287 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
288 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
289 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
290 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
291 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
292 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
293 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
294 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
295 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
296 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
297 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
298 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
299 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
300 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
301 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
302 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
303 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
304 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
305 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
306 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
307 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
308 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
309 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
310 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
311 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
312 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
313 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
314 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
315 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
316 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
317 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
318 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
319 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
320 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
321 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
322 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
323 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
324 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
325 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
326 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
327 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
328 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
329 PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
330 PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
331 PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
332 PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
333 PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
334 PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
335 PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
336 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
337 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
338 PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
339 PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
340 PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
341 PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
342 PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
343 PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
344 PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
345 PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
346 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
347 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
348 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
349 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
350 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
351 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
352 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
353 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
354 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
355 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
356 PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
357 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
358 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
359 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
360 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
361 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
362 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
363 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
364 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
365 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
366 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
367 PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
368 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
369 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
370 PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
371 PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
372 PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
373 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
374 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
375 PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
376 PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
377 PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
378 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
379 PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
380 PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
381 PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
382 PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
383 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
384 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
385 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
386 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
387 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
388 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
389 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
390 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
391};
392
393static const unsigned clk_32k_out_pa0_pins[] = {
394 TEGRA_PIN_CLK_32K_OUT_PA0,
395};
396
397static const unsigned uart3_cts_n_pa1_pins[] = {
398 TEGRA_PIN_UART3_CTS_N_PA1,
399};
400
401static const unsigned dap2_fs_pa2_pins[] = {
402 TEGRA_PIN_DAP2_FS_PA2,
403};
404
405static const unsigned dap2_sclk_pa3_pins[] = {
406 TEGRA_PIN_DAP2_SCLK_PA3,
407};
408
409static const unsigned dap2_din_pa4_pins[] = {
410 TEGRA_PIN_DAP2_DIN_PA4,
411};
412
413static const unsigned dap2_dout_pa5_pins[] = {
414 TEGRA_PIN_DAP2_DOUT_PA5,
415};
416
417static const unsigned sdmmc3_clk_pa6_pins[] = {
418 TEGRA_PIN_SDMMC3_CLK_PA6,
419};
420
421static const unsigned sdmmc3_cmd_pa7_pins[] = {
422 TEGRA_PIN_SDMMC3_CMD_PA7,
423};
424
425static const unsigned gmi_a17_pb0_pins[] = {
426 TEGRA_PIN_GMI_A17_PB0,
427};
428
429static const unsigned gmi_a18_pb1_pins[] = {
430 TEGRA_PIN_GMI_A18_PB1,
431};
432
433static const unsigned sdmmc3_dat3_pb4_pins[] = {
434 TEGRA_PIN_SDMMC3_DAT3_PB4,
435};
436
437static const unsigned sdmmc3_dat2_pb5_pins[] = {
438 TEGRA_PIN_SDMMC3_DAT2_PB5,
439};
440
441static const unsigned sdmmc3_dat1_pb6_pins[] = {
442 TEGRA_PIN_SDMMC3_DAT1_PB6,
443};
444
445static const unsigned sdmmc3_dat0_pb7_pins[] = {
446 TEGRA_PIN_SDMMC3_DAT0_PB7,
447};
448
449static const unsigned uart3_rts_n_pc0_pins[] = {
450 TEGRA_PIN_UART3_RTS_N_PC0,
451};
452
453static const unsigned uart2_txd_pc2_pins[] = {
454 TEGRA_PIN_UART2_TXD_PC2,
455};
456
457static const unsigned uart2_rxd_pc3_pins[] = {
458 TEGRA_PIN_UART2_RXD_PC3,
459};
460
461static const unsigned gen1_i2c_scl_pc4_pins[] = {
462 TEGRA_PIN_GEN1_I2C_SCL_PC4,
463};
464
465static const unsigned gen1_i2c_sda_pc5_pins[] = {
466 TEGRA_PIN_GEN1_I2C_SDA_PC5,
467};
468
469static const unsigned gmi_wp_n_pc7_pins[] = {
470 TEGRA_PIN_GMI_WP_N_PC7,
471};
472
473static const unsigned gmi_ad0_pg0_pins[] = {
474 TEGRA_PIN_GMI_AD0_PG0,
475};
476
477static const unsigned gmi_ad1_pg1_pins[] = {
478 TEGRA_PIN_GMI_AD1_PG1,
479};
480
481static const unsigned gmi_ad2_pg2_pins[] = {
482 TEGRA_PIN_GMI_AD2_PG2,
483};
484
485static const unsigned gmi_ad3_pg3_pins[] = {
486 TEGRA_PIN_GMI_AD3_PG3,
487};
488
489static const unsigned gmi_ad4_pg4_pins[] = {
490 TEGRA_PIN_GMI_AD4_PG4,
491};
492
493static const unsigned gmi_ad5_pg5_pins[] = {
494 TEGRA_PIN_GMI_AD5_PG5,
495};
496
497static const unsigned gmi_ad6_pg6_pins[] = {
498 TEGRA_PIN_GMI_AD6_PG6,
499};
500
501static const unsigned gmi_ad7_pg7_pins[] = {
502 TEGRA_PIN_GMI_AD7_PG7,
503};
504
505static const unsigned gmi_ad8_ph0_pins[] = {
506 TEGRA_PIN_GMI_AD8_PH0,
507};
508
509static const unsigned gmi_ad9_ph1_pins[] = {
510 TEGRA_PIN_GMI_AD9_PH1,
511};
512
513static const unsigned gmi_ad10_ph2_pins[] = {
514 TEGRA_PIN_GMI_AD10_PH2,
515};
516
517static const unsigned gmi_ad11_ph3_pins[] = {
518 TEGRA_PIN_GMI_AD11_PH3,
519};
520
521static const unsigned gmi_ad12_ph4_pins[] = {
522 TEGRA_PIN_GMI_AD12_PH4,
523};
524
525static const unsigned gmi_ad13_ph5_pins[] = {
526 TEGRA_PIN_GMI_AD13_PH5,
527};
528
529static const unsigned gmi_ad14_ph6_pins[] = {
530 TEGRA_PIN_GMI_AD14_PH6,
531};
532
533static const unsigned gmi_ad15_ph7_pins[] = {
534 TEGRA_PIN_GMI_AD15_PH7,
535};
536
537static const unsigned gmi_wr_n_pi0_pins[] = {
538 TEGRA_PIN_GMI_WR_N_PI0,
539};
540
541static const unsigned gmi_oe_n_pi1_pins[] = {
542 TEGRA_PIN_GMI_OE_N_PI1,
543};
544
545static const unsigned gmi_cs6_n_pi3_pins[] = {
546 TEGRA_PIN_GMI_CS6_N_PI3,
547};
548
549static const unsigned gmi_rst_n_pi4_pins[] = {
550 TEGRA_PIN_GMI_RST_N_PI4,
551};
552
553static const unsigned gmi_iordy_pi5_pins[] = {
554 TEGRA_PIN_GMI_IORDY_PI5,
555};
556
557static const unsigned gmi_cs7_n_pi6_pins[] = {
558 TEGRA_PIN_GMI_CS7_N_PI6,
559};
560
561static const unsigned gmi_wait_pi7_pins[] = {
562 TEGRA_PIN_GMI_WAIT_PI7,
563};
564
565static const unsigned gmi_cs0_n_pj0_pins[] = {
566 TEGRA_PIN_GMI_CS0_N_PJ0,
567};
568
569static const unsigned gmi_cs1_n_pj2_pins[] = {
570 TEGRA_PIN_GMI_CS1_N_PJ2,
571};
572
573static const unsigned gmi_dqs_p_pj3_pins[] = {
574 TEGRA_PIN_GMI_DQS_P_PJ3,
575};
576
577static const unsigned uart2_cts_n_pj5_pins[] = {
578 TEGRA_PIN_UART2_CTS_N_PJ5,
579};
580
581static const unsigned uart2_rts_n_pj6_pins[] = {
582 TEGRA_PIN_UART2_RTS_N_PJ6,
583};
584
585static const unsigned gmi_a16_pj7_pins[] = {
586 TEGRA_PIN_GMI_A16_PJ7,
587};
588
589static const unsigned gmi_adv_n_pk0_pins[] = {
590 TEGRA_PIN_GMI_ADV_N_PK0,
591};
592
593static const unsigned gmi_clk_pk1_pins[] = {
594 TEGRA_PIN_GMI_CLK_PK1,
595};
596
597static const unsigned gmi_cs4_n_pk2_pins[] = {
598 TEGRA_PIN_GMI_CS4_N_PK2,
599};
600
601static const unsigned gmi_cs2_n_pk3_pins[] = {
602 TEGRA_PIN_GMI_CS2_N_PK3,
603};
604
605static const unsigned gmi_cs3_n_pk4_pins[] = {
606 TEGRA_PIN_GMI_CS3_N_PK4,
607};
608
609static const unsigned spdif_out_pk5_pins[] = {
610 TEGRA_PIN_SPDIF_OUT_PK5,
611};
612
613static const unsigned spdif_in_pk6_pins[] = {
614 TEGRA_PIN_SPDIF_IN_PK6,
615};
616
617static const unsigned gmi_a19_pk7_pins[] = {
618 TEGRA_PIN_GMI_A19_PK7,
619};
620
621static const unsigned dap1_fs_pn0_pins[] = {
622 TEGRA_PIN_DAP1_FS_PN0,
623};
624
625static const unsigned dap1_din_pn1_pins[] = {
626 TEGRA_PIN_DAP1_DIN_PN1,
627};
628
629static const unsigned dap1_dout_pn2_pins[] = {
630 TEGRA_PIN_DAP1_DOUT_PN2,
631};
632
633static const unsigned dap1_sclk_pn3_pins[] = {
634 TEGRA_PIN_DAP1_SCLK_PN3,
635};
636
637static const unsigned usb_vbus_en0_pn4_pins[] = {
638 TEGRA_PIN_USB_VBUS_EN0_PN4,
639};
640
641static const unsigned usb_vbus_en1_pn5_pins[] = {
642 TEGRA_PIN_USB_VBUS_EN1_PN5,
643};
644
645static const unsigned hdmi_int_pn7_pins[] = {
646 TEGRA_PIN_HDMI_INT_PN7,
647};
648
649static const unsigned ulpi_data7_po0_pins[] = {
650 TEGRA_PIN_ULPI_DATA7_PO0,
651};
652
653static const unsigned ulpi_data0_po1_pins[] = {
654 TEGRA_PIN_ULPI_DATA0_PO1,
655};
656
657static const unsigned ulpi_data1_po2_pins[] = {
658 TEGRA_PIN_ULPI_DATA1_PO2,
659};
660
661static const unsigned ulpi_data2_po3_pins[] = {
662 TEGRA_PIN_ULPI_DATA2_PO3,
663};
664
665static const unsigned ulpi_data3_po4_pins[] = {
666 TEGRA_PIN_ULPI_DATA3_PO4,
667};
668
669static const unsigned ulpi_data4_po5_pins[] = {
670 TEGRA_PIN_ULPI_DATA4_PO5,
671};
672
673static const unsigned ulpi_data5_po6_pins[] = {
674 TEGRA_PIN_ULPI_DATA5_PO6,
675};
676
677static const unsigned ulpi_data6_po7_pins[] = {
678 TEGRA_PIN_ULPI_DATA6_PO7,
679};
680
681static const unsigned dap3_fs_pp0_pins[] = {
682 TEGRA_PIN_DAP3_FS_PP0,
683};
684
685static const unsigned dap3_din_pp1_pins[] = {
686 TEGRA_PIN_DAP3_DIN_PP1,
687};
688
689static const unsigned dap3_dout_pp2_pins[] = {
690 TEGRA_PIN_DAP3_DOUT_PP2,
691};
692
693static const unsigned dap3_sclk_pp3_pins[] = {
694 TEGRA_PIN_DAP3_SCLK_PP3,
695};
696
697static const unsigned dap4_fs_pp4_pins[] = {
698 TEGRA_PIN_DAP4_FS_PP4,
699};
700
701static const unsigned dap4_din_pp5_pins[] = {
702 TEGRA_PIN_DAP4_DIN_PP5,
703};
704
705static const unsigned dap4_dout_pp6_pins[] = {
706 TEGRA_PIN_DAP4_DOUT_PP6,
707};
708
709static const unsigned dap4_sclk_pp7_pins[] = {
710 TEGRA_PIN_DAP4_SCLK_PP7,
711};
712
713static const unsigned kb_col0_pq0_pins[] = {
714 TEGRA_PIN_KB_COL0_PQ0,
715};
716
717static const unsigned kb_col1_pq1_pins[] = {
718 TEGRA_PIN_KB_COL1_PQ1,
719};
720
721static const unsigned kb_col2_pq2_pins[] = {
722 TEGRA_PIN_KB_COL2_PQ2,
723};
724
725static const unsigned kb_col3_pq3_pins[] = {
726 TEGRA_PIN_KB_COL3_PQ3,
727};
728
729static const unsigned kb_col4_pq4_pins[] = {
730 TEGRA_PIN_KB_COL4_PQ4,
731};
732
733static const unsigned kb_col5_pq5_pins[] = {
734 TEGRA_PIN_KB_COL5_PQ5,
735};
736
737static const unsigned kb_col6_pq6_pins[] = {
738 TEGRA_PIN_KB_COL6_PQ6,
739};
740
741static const unsigned kb_col7_pq7_pins[] = {
742 TEGRA_PIN_KB_COL7_PQ7,
743};
744
745static const unsigned kb_row0_pr0_pins[] = {
746 TEGRA_PIN_KB_ROW0_PR0,
747};
748
749static const unsigned kb_row1_pr1_pins[] = {
750 TEGRA_PIN_KB_ROW1_PR1,
751};
752
753static const unsigned kb_row2_pr2_pins[] = {
754 TEGRA_PIN_KB_ROW2_PR2,
755};
756
757static const unsigned kb_row3_pr3_pins[] = {
758 TEGRA_PIN_KB_ROW3_PR3,
759};
760
761static const unsigned kb_row4_pr4_pins[] = {
762 TEGRA_PIN_KB_ROW4_PR4,
763};
764
765static const unsigned kb_row5_pr5_pins[] = {
766 TEGRA_PIN_KB_ROW5_PR5,
767};
768
769static const unsigned kb_row6_pr6_pins[] = {
770 TEGRA_PIN_KB_ROW6_PR6,
771};
772
773static const unsigned kb_row7_pr7_pins[] = {
774 TEGRA_PIN_KB_ROW7_PR7,
775};
776
777static const unsigned kb_row8_ps0_pins[] = {
778 TEGRA_PIN_KB_ROW8_PS0,
779};
780
781static const unsigned kb_row9_ps1_pins[] = {
782 TEGRA_PIN_KB_ROW9_PS1,
783};
784
785static const unsigned kb_row10_ps2_pins[] = {
786 TEGRA_PIN_KB_ROW10_PS2,
787};
788
789static const unsigned gen2_i2c_scl_pt5_pins[] = {
790 TEGRA_PIN_GEN2_I2C_SCL_PT5,
791};
792
793static const unsigned gen2_i2c_sda_pt6_pins[] = {
794 TEGRA_PIN_GEN2_I2C_SDA_PT6,
795};
796
797static const unsigned sdmmc4_cmd_pt7_pins[] = {
798 TEGRA_PIN_SDMMC4_CMD_PT7,
799};
800
801static const unsigned pu0_pins[] = {
802 TEGRA_PIN_PU0,
803};
804
805static const unsigned pu1_pins[] = {
806 TEGRA_PIN_PU1,
807};
808
809static const unsigned pu2_pins[] = {
810 TEGRA_PIN_PU2,
811};
812
813static const unsigned pu3_pins[] = {
814 TEGRA_PIN_PU3,
815};
816
817static const unsigned pu4_pins[] = {
818 TEGRA_PIN_PU4,
819};
820
821static const unsigned pu5_pins[] = {
822 TEGRA_PIN_PU5,
823};
824
825static const unsigned pu6_pins[] = {
826 TEGRA_PIN_PU6,
827};
828
829static const unsigned pv0_pins[] = {
830 TEGRA_PIN_PV0,
831};
832
833static const unsigned pv1_pins[] = {
834 TEGRA_PIN_PV1,
835};
836
837static const unsigned sdmmc3_cd_n_pv2_pins[] = {
838 TEGRA_PIN_SDMMC3_CD_N_PV2,
839};
840
841static const unsigned sdmmc1_wp_n_pv3_pins[] = {
842 TEGRA_PIN_SDMMC1_WP_N_PV3,
843};
844
845static const unsigned ddc_scl_pv4_pins[] = {
846 TEGRA_PIN_DDC_SCL_PV4,
847};
848
849static const unsigned ddc_sda_pv5_pins[] = {
850 TEGRA_PIN_DDC_SDA_PV5,
851};
852
853static const unsigned gpio_w2_aud_pw2_pins[] = {
854 TEGRA_PIN_GPIO_W2_AUD_PW2,
855};
856
857static const unsigned gpio_w3_aud_pw3_pins[] = {
858 TEGRA_PIN_GPIO_W3_AUD_PW3,
859};
860
861static const unsigned clk1_out_pw4_pins[] = {
862 TEGRA_PIN_CLK1_OUT_PW4,
863};
864
865static const unsigned clk2_out_pw5_pins[] = {
866 TEGRA_PIN_CLK2_OUT_PW5,
867};
868
869static const unsigned uart3_txd_pw6_pins[] = {
870 TEGRA_PIN_UART3_TXD_PW6,
871};
872
873static const unsigned uart3_rxd_pw7_pins[] = {
874 TEGRA_PIN_UART3_RXD_PW7,
875};
876
877static const unsigned dvfs_pwm_px0_pins[] = {
878 TEGRA_PIN_DVFS_PWM_PX0,
879};
880
881static const unsigned gpio_x1_aud_px1_pins[] = {
882 TEGRA_PIN_GPIO_X1_AUD_PX1,
883};
884
885static const unsigned dvfs_clk_px2_pins[] = {
886 TEGRA_PIN_DVFS_CLK_PX2,
887};
888
889static const unsigned gpio_x3_aud_px3_pins[] = {
890 TEGRA_PIN_GPIO_X3_AUD_PX3,
891};
892
893static const unsigned gpio_x4_aud_px4_pins[] = {
894 TEGRA_PIN_GPIO_X4_AUD_PX4,
895};
896
897static const unsigned gpio_x5_aud_px5_pins[] = {
898 TEGRA_PIN_GPIO_X5_AUD_PX5,
899};
900
901static const unsigned gpio_x6_aud_px6_pins[] = {
902 TEGRA_PIN_GPIO_X6_AUD_PX6,
903};
904
905static const unsigned gpio_x7_aud_px7_pins[] = {
906 TEGRA_PIN_GPIO_X7_AUD_PX7,
907};
908
909static const unsigned ulpi_clk_py0_pins[] = {
910 TEGRA_PIN_ULPI_CLK_PY0,
911};
912
913static const unsigned ulpi_dir_py1_pins[] = {
914 TEGRA_PIN_ULPI_DIR_PY1,
915};
916
917static const unsigned ulpi_nxt_py2_pins[] = {
918 TEGRA_PIN_ULPI_NXT_PY2,
919};
920
921static const unsigned ulpi_stp_py3_pins[] = {
922 TEGRA_PIN_ULPI_STP_PY3,
923};
924
925static const unsigned sdmmc1_dat3_py4_pins[] = {
926 TEGRA_PIN_SDMMC1_DAT3_PY4,
927};
928
929static const unsigned sdmmc1_dat2_py5_pins[] = {
930 TEGRA_PIN_SDMMC1_DAT2_PY5,
931};
932
933static const unsigned sdmmc1_dat1_py6_pins[] = {
934 TEGRA_PIN_SDMMC1_DAT1_PY6,
935};
936
937static const unsigned sdmmc1_dat0_py7_pins[] = {
938 TEGRA_PIN_SDMMC1_DAT0_PY7,
939};
940
941static const unsigned sdmmc1_clk_pz0_pins[] = {
942 TEGRA_PIN_SDMMC1_CLK_PZ0,
943};
944
945static const unsigned sdmmc1_cmd_pz1_pins[] = {
946 TEGRA_PIN_SDMMC1_CMD_PZ1,
947};
948
949static const unsigned sys_clk_req_pz5_pins[] = {
950 TEGRA_PIN_SYS_CLK_REQ_PZ5,
951};
952
953static const unsigned pwr_i2c_scl_pz6_pins[] = {
954 TEGRA_PIN_PWR_I2C_SCL_PZ6,
955};
956
957static const unsigned pwr_i2c_sda_pz7_pins[] = {
958 TEGRA_PIN_PWR_I2C_SDA_PZ7,
959};
960
961static const unsigned sdmmc4_dat0_paa0_pins[] = {
962 TEGRA_PIN_SDMMC4_DAT0_PAA0,
963};
964
965static const unsigned sdmmc4_dat1_paa1_pins[] = {
966 TEGRA_PIN_SDMMC4_DAT1_PAA1,
967};
968
969static const unsigned sdmmc4_dat2_paa2_pins[] = {
970 TEGRA_PIN_SDMMC4_DAT2_PAA2,
971};
972
973static const unsigned sdmmc4_dat3_paa3_pins[] = {
974 TEGRA_PIN_SDMMC4_DAT3_PAA3,
975};
976
977static const unsigned sdmmc4_dat4_paa4_pins[] = {
978 TEGRA_PIN_SDMMC4_DAT4_PAA4,
979};
980
981static const unsigned sdmmc4_dat5_paa5_pins[] = {
982 TEGRA_PIN_SDMMC4_DAT5_PAA5,
983};
984
985static const unsigned sdmmc4_dat6_paa6_pins[] = {
986 TEGRA_PIN_SDMMC4_DAT6_PAA6,
987};
988
989static const unsigned sdmmc4_dat7_paa7_pins[] = {
990 TEGRA_PIN_SDMMC4_DAT7_PAA7,
991};
992
993static const unsigned pbb0_pins[] = {
994 TEGRA_PIN_PBB0,
995};
996
997static const unsigned cam_i2c_scl_pbb1_pins[] = {
998 TEGRA_PIN_CAM_I2C_SCL_PBB1,
999};
1000
1001static const unsigned cam_i2c_sda_pbb2_pins[] = {
1002 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1003};
1004
1005static const unsigned pbb3_pins[] = {
1006 TEGRA_PIN_PBB3,
1007};
1008
1009static const unsigned pbb4_pins[] = {
1010 TEGRA_PIN_PBB4,
1011};
1012
1013static const unsigned pbb5_pins[] = {
1014 TEGRA_PIN_PBB5,
1015};
1016
1017static const unsigned pbb6_pins[] = {
1018 TEGRA_PIN_PBB6,
1019};
1020
1021static const unsigned pbb7_pins[] = {
1022 TEGRA_PIN_PBB7,
1023};
1024
1025static const unsigned cam_mclk_pcc0_pins[] = {
1026 TEGRA_PIN_CAM_MCLK_PCC0,
1027};
1028
1029static const unsigned pcc1_pins[] = {
1030 TEGRA_PIN_PCC1,
1031};
1032
1033static const unsigned pcc2_pins[] = {
1034 TEGRA_PIN_PCC2,
1035};
1036
1037static const unsigned sdmmc4_clk_pcc4_pins[] = {
1038 TEGRA_PIN_SDMMC4_CLK_PCC4,
1039};
1040
1041static const unsigned clk2_req_pcc5_pins[] = {
1042 TEGRA_PIN_CLK2_REQ_PCC5,
1043};
1044
1045static const unsigned clk3_out_pee0_pins[] = {
1046 TEGRA_PIN_CLK3_OUT_PEE0,
1047};
1048
1049static const unsigned clk3_req_pee1_pins[] = {
1050 TEGRA_PIN_CLK3_REQ_PEE1,
1051};
1052
1053static const unsigned clk1_req_pee2_pins[] = {
1054 TEGRA_PIN_CLK1_REQ_PEE2,
1055};
1056
1057static const unsigned hdmi_cec_pee3_pins[] = {
1058 TEGRA_PIN_HDMI_CEC_PEE3,
1059};
1060
1061static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1062 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1063};
1064
1065static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1066 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1067};
1068
1069static const unsigned core_pwr_req_pins[] = {
1070 TEGRA_PIN_CORE_PWR_REQ,
1071};
1072
1073static const unsigned cpu_pwr_req_pins[] = {
1074 TEGRA_PIN_CPU_PWR_REQ,
1075};
1076
1077static const unsigned owr_pins[] = {
1078 TEGRA_PIN_OWR,
1079};
1080
1081static const unsigned pwr_int_n_pins[] = {
1082 TEGRA_PIN_PWR_INT_N,
1083};
1084
1085static const unsigned reset_out_n_pins[] = {
1086 TEGRA_PIN_RESET_OUT_N,
1087};
1088
1089static const unsigned drive_ao1_pins[] = {
1090 TEGRA_PIN_KB_ROW0_PR0,
1091 TEGRA_PIN_KB_ROW1_PR1,
1092 TEGRA_PIN_KB_ROW2_PR2,
1093 TEGRA_PIN_KB_ROW3_PR3,
1094 TEGRA_PIN_KB_ROW4_PR4,
1095 TEGRA_PIN_KB_ROW5_PR5,
1096 TEGRA_PIN_KB_ROW6_PR6,
1097 TEGRA_PIN_KB_ROW7_PR7,
1098 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1099 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1100};
1101
1102static const unsigned drive_ao2_pins[] = {
1103 TEGRA_PIN_CLK_32K_OUT_PA0,
1104 TEGRA_PIN_KB_COL0_PQ0,
1105 TEGRA_PIN_KB_COL1_PQ1,
1106 TEGRA_PIN_KB_COL2_PQ2,
1107 TEGRA_PIN_KB_COL3_PQ3,
1108 TEGRA_PIN_KB_COL4_PQ4,
1109 TEGRA_PIN_KB_COL5_PQ5,
1110 TEGRA_PIN_KB_COL6_PQ6,
1111 TEGRA_PIN_KB_COL7_PQ7,
1112 TEGRA_PIN_KB_ROW8_PS0,
1113 TEGRA_PIN_KB_ROW9_PS1,
1114 TEGRA_PIN_KB_ROW10_PS2,
1115 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1116 TEGRA_PIN_CORE_PWR_REQ,
1117 TEGRA_PIN_CPU_PWR_REQ,
1118 TEGRA_PIN_RESET_OUT_N,
1119};
1120
1121static const unsigned drive_at1_pins[] = {
1122 TEGRA_PIN_GMI_AD8_PH0,
1123 TEGRA_PIN_GMI_AD9_PH1,
1124 TEGRA_PIN_GMI_AD10_PH2,
1125 TEGRA_PIN_GMI_AD11_PH3,
1126 TEGRA_PIN_GMI_AD12_PH4,
1127 TEGRA_PIN_GMI_AD13_PH5,
1128 TEGRA_PIN_GMI_AD14_PH6,
1129 TEGRA_PIN_GMI_AD15_PH7,
1130
1131 TEGRA_PIN_GMI_IORDY_PI5,
1132 TEGRA_PIN_GMI_CS7_N_PI6,
1133};
1134
1135static const unsigned drive_at2_pins[] = {
1136 TEGRA_PIN_GMI_AD0_PG0,
1137 TEGRA_PIN_GMI_AD1_PG1,
1138 TEGRA_PIN_GMI_AD2_PG2,
1139 TEGRA_PIN_GMI_AD3_PG3,
1140 TEGRA_PIN_GMI_AD4_PG4,
1141 TEGRA_PIN_GMI_AD5_PG5,
1142 TEGRA_PIN_GMI_AD6_PG6,
1143 TEGRA_PIN_GMI_AD7_PG7,
1144
1145 TEGRA_PIN_GMI_WR_N_PI0,
1146 TEGRA_PIN_GMI_OE_N_PI1,
1147 TEGRA_PIN_GMI_CS6_N_PI3,
1148 TEGRA_PIN_GMI_RST_N_PI4,
1149 TEGRA_PIN_GMI_WAIT_PI7,
1150
1151 TEGRA_PIN_GMI_DQS_P_PJ3,
1152
1153 TEGRA_PIN_GMI_ADV_N_PK0,
1154 TEGRA_PIN_GMI_CLK_PK1,
1155 TEGRA_PIN_GMI_CS4_N_PK2,
1156 TEGRA_PIN_GMI_CS2_N_PK3,
1157 TEGRA_PIN_GMI_CS3_N_PK4,
1158};
1159
1160static const unsigned drive_at3_pins[] = {
1161 TEGRA_PIN_GMI_WP_N_PC7,
1162 TEGRA_PIN_GMI_CS0_N_PJ0,
1163};
1164
1165static const unsigned drive_at4_pins[] = {
1166 TEGRA_PIN_GMI_A17_PB0,
1167 TEGRA_PIN_GMI_A18_PB1,
1168 TEGRA_PIN_GMI_CS1_N_PJ2,
1169 TEGRA_PIN_GMI_A16_PJ7,
1170 TEGRA_PIN_GMI_A19_PK7,
1171};
1172
1173static const unsigned drive_at5_pins[] = {
1174 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1175 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1176};
1177
1178static const unsigned drive_cdev1_pins[] = {
1179 TEGRA_PIN_CLK1_OUT_PW4,
1180 TEGRA_PIN_CLK1_REQ_PEE2,
1181};
1182
1183static const unsigned drive_cdev2_pins[] = {
1184 TEGRA_PIN_CLK2_OUT_PW5,
1185 TEGRA_PIN_CLK2_REQ_PCC5,
1186 TEGRA_PIN_SDMMC1_WP_N_PV3,
1187};
1188
1189static const unsigned drive_dap1_pins[] = {
1190 TEGRA_PIN_DAP1_FS_PN0,
1191 TEGRA_PIN_DAP1_DIN_PN1,
1192 TEGRA_PIN_DAP1_DOUT_PN2,
1193 TEGRA_PIN_DAP1_SCLK_PN3,
1194};
1195
1196static const unsigned drive_dap2_pins[] = {
1197 TEGRA_PIN_DAP2_FS_PA2,
1198 TEGRA_PIN_DAP2_SCLK_PA3,
1199 TEGRA_PIN_DAP2_DIN_PA4,
1200 TEGRA_PIN_DAP2_DOUT_PA5,
1201};
1202
1203static const unsigned drive_dap3_pins[] = {
1204 TEGRA_PIN_DAP3_FS_PP0,
1205 TEGRA_PIN_DAP3_DIN_PP1,
1206 TEGRA_PIN_DAP3_DOUT_PP2,
1207 TEGRA_PIN_DAP3_SCLK_PP3,
1208};
1209
1210static const unsigned drive_dap4_pins[] = {
1211 TEGRA_PIN_DAP4_FS_PP4,
1212 TEGRA_PIN_DAP4_DIN_PP5,
1213 TEGRA_PIN_DAP4_DOUT_PP6,
1214 TEGRA_PIN_DAP4_SCLK_PP7,
1215};
1216
1217static const unsigned drive_dbg_pins[] = {
1218 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1219 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1220 TEGRA_PIN_PU0,
1221 TEGRA_PIN_PU1,
1222 TEGRA_PIN_PU2,
1223 TEGRA_PIN_PU3,
1224 TEGRA_PIN_PU4,
1225 TEGRA_PIN_PU5,
1226 TEGRA_PIN_PU6,
1227};
1228
1229static const unsigned drive_sdio3_pins[] = {
1230 TEGRA_PIN_SDMMC3_CLK_PA6,
1231 TEGRA_PIN_SDMMC3_CMD_PA7,
1232 TEGRA_PIN_SDMMC3_DAT3_PB4,
1233 TEGRA_PIN_SDMMC3_DAT2_PB5,
1234 TEGRA_PIN_SDMMC3_DAT1_PB6,
1235 TEGRA_PIN_SDMMC3_DAT0_PB7,
1236 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1237 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1238};
1239
1240static const unsigned drive_spi_pins[] = {
1241 TEGRA_PIN_DVFS_PWM_PX0,
1242 TEGRA_PIN_GPIO_X1_AUD_PX1,
1243 TEGRA_PIN_DVFS_CLK_PX2,
1244 TEGRA_PIN_GPIO_X3_AUD_PX3,
1245 TEGRA_PIN_GPIO_X4_AUD_PX4,
1246 TEGRA_PIN_GPIO_X5_AUD_PX5,
1247 TEGRA_PIN_GPIO_X6_AUD_PX6,
1248 TEGRA_PIN_GPIO_X7_AUD_PX7,
1249 TEGRA_PIN_GPIO_W2_AUD_PW2,
1250 TEGRA_PIN_GPIO_W3_AUD_PW3,
1251};
1252
1253static const unsigned drive_uaa_pins[] = {
1254 TEGRA_PIN_ULPI_DATA0_PO1,
1255 TEGRA_PIN_ULPI_DATA1_PO2,
1256 TEGRA_PIN_ULPI_DATA2_PO3,
1257 TEGRA_PIN_ULPI_DATA3_PO4,
1258};
1259
1260static const unsigned drive_uab_pins[] = {
1261 TEGRA_PIN_ULPI_DATA7_PO0,
1262 TEGRA_PIN_ULPI_DATA4_PO5,
1263 TEGRA_PIN_ULPI_DATA5_PO6,
1264 TEGRA_PIN_ULPI_DATA6_PO7,
1265 TEGRA_PIN_PV0,
1266 TEGRA_PIN_PV1,
1267};
1268
1269static const unsigned drive_uart2_pins[] = {
1270 TEGRA_PIN_UART2_TXD_PC2,
1271 TEGRA_PIN_UART2_RXD_PC3,
1272 TEGRA_PIN_UART2_CTS_N_PJ5,
1273 TEGRA_PIN_UART2_RTS_N_PJ6,
1274};
1275
1276static const unsigned drive_uart3_pins[] = {
1277 TEGRA_PIN_UART3_CTS_N_PA1,
1278 TEGRA_PIN_UART3_RTS_N_PC0,
1279 TEGRA_PIN_UART3_TXD_PW6,
1280 TEGRA_PIN_UART3_RXD_PW7,
1281};
1282
1283static const unsigned drive_sdio1_pins[] = {
1284 TEGRA_PIN_SDMMC1_DAT3_PY4,
1285 TEGRA_PIN_SDMMC1_DAT2_PY5,
1286 TEGRA_PIN_SDMMC1_DAT1_PY6,
1287 TEGRA_PIN_SDMMC1_DAT0_PY7,
1288 TEGRA_PIN_SDMMC1_CLK_PZ0,
1289 TEGRA_PIN_SDMMC1_CMD_PZ1,
1290};
1291
1292static const unsigned drive_ddc_pins[] = {
1293 TEGRA_PIN_DDC_SCL_PV4,
1294 TEGRA_PIN_DDC_SDA_PV5,
1295};
1296
1297static const unsigned drive_gma_pins[] = {
1298 TEGRA_PIN_SDMMC4_CLK_PCC4,
1299 TEGRA_PIN_SDMMC4_CMD_PT7,
1300 TEGRA_PIN_SDMMC4_DAT0_PAA0,
1301 TEGRA_PIN_SDMMC4_DAT1_PAA1,
1302 TEGRA_PIN_SDMMC4_DAT2_PAA2,
1303 TEGRA_PIN_SDMMC4_DAT3_PAA3,
1304 TEGRA_PIN_SDMMC4_DAT4_PAA4,
1305 TEGRA_PIN_SDMMC4_DAT5_PAA5,
1306 TEGRA_PIN_SDMMC4_DAT6_PAA6,
1307 TEGRA_PIN_SDMMC4_DAT7_PAA7,
1308};
1309
1310static const unsigned drive_gme_pins[] = {
1311 TEGRA_PIN_PBB0,
1312 TEGRA_PIN_CAM_I2C_SCL_PBB1,
1313 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1314 TEGRA_PIN_PBB3,
1315 TEGRA_PIN_PCC2,
1316};
1317
1318static const unsigned drive_gmf_pins[] = {
1319 TEGRA_PIN_PBB4,
1320 TEGRA_PIN_PBB5,
1321 TEGRA_PIN_PBB6,
1322 TEGRA_PIN_PBB7,
1323};
1324
1325static const unsigned drive_gmg_pins[] = {
1326 TEGRA_PIN_CAM_MCLK_PCC0,
1327};
1328
1329static const unsigned drive_gmh_pins[] = {
1330 TEGRA_PIN_PCC1,
1331};
1332
1333static const unsigned drive_owr_pins[] = {
1334 TEGRA_PIN_SDMMC3_CD_N_PV2,
1335};
1336
1337static const unsigned drive_uda_pins[] = {
1338 TEGRA_PIN_ULPI_CLK_PY0,
1339 TEGRA_PIN_ULPI_DIR_PY1,
1340 TEGRA_PIN_ULPI_NXT_PY2,
1341 TEGRA_PIN_ULPI_STP_PY3,
1342};
1343
1344static const unsigned drive_dev3_pins[] = {
1345 TEGRA_PIN_CLK3_OUT_PEE0,
1346 TEGRA_PIN_CLK3_REQ_PEE1,
1347};
1348
1349enum tegra_mux {
1350 TEGRA_MUX_BLINK,
1351 TEGRA_MUX_CEC,
1352 TEGRA_MUX_CLDVFS,
1353 TEGRA_MUX_CLK12,
1354 TEGRA_MUX_CPU,
1355 TEGRA_MUX_DAP,
1356 TEGRA_MUX_DAP1,
1357 TEGRA_MUX_DAP2,
1358 TEGRA_MUX_DEV3,
1359 TEGRA_MUX_DISPLAYA,
1360 TEGRA_MUX_DISPLAYA_ALT,
1361 TEGRA_MUX_DISPLAYB,
1362 TEGRA_MUX_DTV,
1363 TEGRA_MUX_EMC_DLL,
1364 TEGRA_MUX_EXTPERIPH1,
1365 TEGRA_MUX_EXTPERIPH2,
1366 TEGRA_MUX_EXTPERIPH3,
1367 TEGRA_MUX_GMI,
1368 TEGRA_MUX_GMI_ALT,
1369 TEGRA_MUX_HDA,
1370 TEGRA_MUX_HSI,
1371 TEGRA_MUX_I2C1,
1372 TEGRA_MUX_I2C2,
1373 TEGRA_MUX_I2C3,
1374 TEGRA_MUX_I2C4,
1375 TEGRA_MUX_I2CPWR,
1376 TEGRA_MUX_I2S0,
1377 TEGRA_MUX_I2S1,
1378 TEGRA_MUX_I2S2,
1379 TEGRA_MUX_I2S3,
1380 TEGRA_MUX_I2S4,
1381 TEGRA_MUX_IRDA,
1382 TEGRA_MUX_KBC,
1383 TEGRA_MUX_NAND,
1384 TEGRA_MUX_NAND_ALT,
1385 TEGRA_MUX_OWR,
1386 TEGRA_MUX_PMI,
1387 TEGRA_MUX_PWM0,
1388 TEGRA_MUX_PWM1,
1389 TEGRA_MUX_PWM2,
1390 TEGRA_MUX_PWM3,
1391 TEGRA_MUX_PWRON,
1392 TEGRA_MUX_RESET_OUT_N,
1393 TEGRA_MUX_RSVD1,
1394 TEGRA_MUX_RSVD2,
1395 TEGRA_MUX_RSVD3,
1396 TEGRA_MUX_RSVD4,
1397 TEGRA_MUX_SDMMC1,
1398 TEGRA_MUX_SDMMC2,
1399 TEGRA_MUX_SDMMC3,
1400 TEGRA_MUX_SDMMC4,
1401 TEGRA_MUX_SOC,
1402 TEGRA_MUX_SPDIF,
1403 TEGRA_MUX_SPI1,
1404 TEGRA_MUX_SPI2,
1405 TEGRA_MUX_SPI3,
1406 TEGRA_MUX_SPI4,
1407 TEGRA_MUX_SPI5,
1408 TEGRA_MUX_SPI6,
1409 TEGRA_MUX_SYSCLK,
1410 TEGRA_MUX_TRACE,
1411 TEGRA_MUX_UARTA,
1412 TEGRA_MUX_UARTB,
1413 TEGRA_MUX_UARTC,
1414 TEGRA_MUX_UARTD,
1415 TEGRA_MUX_ULPI,
1416 TEGRA_MUX_USB,
1417 TEGRA_MUX_VGP1,
1418 TEGRA_MUX_VGP2,
1419 TEGRA_MUX_VGP3,
1420 TEGRA_MUX_VGP4,
1421 TEGRA_MUX_VGP5,
1422 TEGRA_MUX_VGP6,
1423 TEGRA_MUX_VI,
1424 TEGRA_MUX_VI_ALT1,
1425 TEGRA_MUX_VI_ALT3,
1426};
1427
1428static const char * const blink_groups[] = {
1429 "clk_32k_out_pa0",
1430};
1431
1432static const char * const cec_groups[] = {
1433 "hdmi_cec_pee3",
1434};
1435
1436static const char * const cldvfs_groups[] = {
1437 "gmi_ad9_ph1",
1438 "gmi_ad10_ph2",
1439 "kb_row7_pr7",
1440 "kb_row8_ps0",
1441 "dvfs_pwm_px0",
1442 "dvfs_clk_px2",
1443};
1444
1445static const char * const clk12_groups[] = {
1446 "sdmmc1_wp_n_pv3",
1447 "sdmmc1_clk_pz0",
1448};
1449
1450static const char * const cpu_groups[] = {
1451 "cpu_pwr_req",
1452};
1453
1454static const char * const dap_groups[] = {
1455 "clk1_req_pee2",
1456 "clk2_req_pcc5",
1457};
1458
1459static const char * const dap1_groups[] = {
1460 "clk1_req_pee2",
1461};
1462
1463static const char * const dap2_groups[] = {
1464 "clk1_out_pw4",
1465 "gpio_x4_aud_px4",
1466};
1467
1468static const char * const dev3_groups[] = {
1469 "clk3_req_pee1",
1470};
1471
1472static const char * const displaya_groups[] = {
1473 "dap3_fs_pp0",
1474 "dap3_din_pp1",
1475 "dap3_dout_pp2",
1476 "dap3_sclk_pp3",
1477 "uart3_rts_n_pc0",
1478 "pu3",
1479 "pu4",
1480 "pu5",
1481 "pbb3",
1482 "pbb4",
1483 "pbb5",
1484 "pbb6",
1485 "kb_row3_pr3",
1486 "kb_row4_pr4",
1487 "kb_row5_pr5",
1488 "kb_row6_pr6",
1489 "kb_col3_pq3",
1490 "sdmmc3_dat2_pb5",
1491};
1492
1493static const char * const displaya_alt_groups[] = {
1494 "kb_row6_pr6",
1495};
1496
1497static const char * const displayb_groups[] = {
1498 "dap3_fs_pp0",
1499 "dap3_din_pp1",
1500 "dap3_dout_pp2",
1501 "dap3_sclk_pp3",
1502 "pu3",
1503 "pu4",
1504 "pu5",
1505 "pu6",
1506 "pbb3",
1507 "pbb4",
1508 "pbb5",
1509 "pbb6",
1510 "kb_row3_pr3",
1511 "kb_row4_pr4",
1512 "kb_row5_pr5",
1513 "kb_row6_pr6",
1514 "sdmmc3_dat3_pb4",
1515};
1516
1517static const char * const dtv_groups[] = {
1518 "uart3_cts_n_pa1",
1519 "uart3_rts_n_pc0",
1520 "dap4_fs_pp4",
1521 "dap4_dout_pp6",
1522 "gmi_wait_pi7",
1523 "gmi_ad8_ph0",
1524 "gmi_ad14_ph6",
1525 "gmi_ad15_ph7",
1526};
1527
1528static const char * const emc_dll_groups[] = {
1529 "kb_col0_pq0",
1530 "kb_col1_pq1",
1531};
1532
1533static const char * const extperiph1_groups[] = {
1534 "clk1_out_pw4",
1535};
1536
1537static const char * const extperiph2_groups[] = {
1538 "clk2_out_pw5",
1539};
1540
1541static const char * const extperiph3_groups[] = {
1542 "clk3_out_pee0",
1543};
1544
1545static const char * const gmi_groups[] = {
1546 "gmi_wp_n_pc7",
1547
1548 "gmi_ad0_pg0",
1549 "gmi_ad1_pg1",
1550 "gmi_ad2_pg2",
1551 "gmi_ad3_pg3",
1552 "gmi_ad4_pg4",
1553 "gmi_ad5_pg5",
1554 "gmi_ad6_pg6",
1555 "gmi_ad7_pg7",
1556 "gmi_ad8_ph0",
1557 "gmi_ad9_ph1",
1558 "gmi_ad10_ph2",
1559 "gmi_ad11_ph3",
1560 "gmi_ad12_ph4",
1561 "gmi_ad13_ph5",
1562 "gmi_ad14_ph6",
1563 "gmi_ad15_ph7",
1564 "gmi_wr_n_pi0",
1565 "gmi_oe_n_pi1",
1566 "gmi_cs6_n_pi3",
1567 "gmi_rst_n_pi4",
1568 "gmi_iordy_pi5",
1569 "gmi_cs7_n_pi6",
1570 "gmi_wait_pi7",
1571 "gmi_cs0_n_pj0",
1572 "gmi_cs1_n_pj2",
1573 "gmi_dqs_p_pj3",
1574 "gmi_adv_n_pk0",
1575 "gmi_clk_pk1",
1576 "gmi_cs4_n_pk2",
1577 "gmi_cs2_n_pk3",
1578 "gmi_cs3_n_pk4",
1579 "gmi_a16_pj7",
1580 "gmi_a17_pb0",
1581 "gmi_a18_pb1",
1582 "gmi_a19_pk7",
1583 "gen2_i2c_scl_pt5",
1584 "gen2_i2c_sda_pt6",
1585 "sdmmc4_dat0_paa0",
1586 "sdmmc4_dat1_paa1",
1587 "sdmmc4_dat2_paa2",
1588 "sdmmc4_dat3_paa3",
1589 "sdmmc4_dat4_paa4",
1590 "sdmmc4_dat5_paa5",
1591 "sdmmc4_dat6_paa6",
1592 "sdmmc4_dat7_paa7",
1593 "sdmmc4_clk_pcc4",
1594 "sdmmc4_cmd_pt7",
1595 "dap1_fs_pn0",
1596 "dap1_din_pn1",
1597 "dap1_dout_pn2",
1598 "dap1_sclk_pn3",
1599};
1600
1601static const char * const gmi_alt_groups[] = {
1602 "gmi_wp_n_pc7",
1603 "gmi_cs3_n_pk4",
1604 "gmi_a16_pj7",
1605};
1606
1607static const char * const hda_groups[] = {
1608 "dap1_fs_pn0",
1609 "dap1_din_pn1",
1610 "dap1_dout_pn2",
1611 "dap1_sclk_pn3",
1612 "dap2_fs_pa2",
1613 "dap2_sclk_pa3",
1614 "dap2_din_pa4",
1615 "dap2_dout_pa5",
1616};
1617
1618static const char * const hsi_groups[] = {
1619 "ulpi_data0_po1",
1620 "ulpi_data1_po2",
1621 "ulpi_data2_po3",
1622 "ulpi_data3_po4",
1623 "ulpi_data4_po5",
1624 "ulpi_data5_po6",
1625 "ulpi_data6_po7",
1626 "ulpi_data7_po0",
1627};
1628
1629static const char * const i2c1_groups[] = {
1630 "gen1_i2c_scl_pc4",
1631 "gen1_i2c_sda_pc5",
1632 "gpio_w2_aud_pw2",
1633 "gpio_w3_aud_pw3",
1634};
1635
1636static const char * const i2c2_groups[] = {
1637 "gen2_i2c_scl_pt5",
1638 "gen2_i2c_sda_pt6",
1639};
1640
1641static const char * const i2c3_groups[] = {
1642 "cam_i2c_scl_pbb1",
1643 "cam_i2c_sda_pbb2",
1644};
1645
1646static const char * const i2c4_groups[] = {
1647 "ddc_scl_pv4",
1648 "ddc_sda_pv5",
1649};
1650
1651static const char * const i2cpwr_groups[] = {
1652 "pwr_i2c_scl_pz6",
1653 "pwr_i2c_sda_pz7",
1654};
1655
1656static const char * const i2s0_groups[] = {
1657 "dap1_fs_pn0",
1658 "dap1_din_pn1",
1659 "dap1_dout_pn2",
1660 "dap1_sclk_pn3",
1661};
1662
1663static const char * const i2s1_groups[] = {
1664 "dap2_fs_pa2",
1665 "dap2_sclk_pa3",
1666 "dap2_din_pa4",
1667 "dap2_dout_pa5",
1668};
1669
1670static const char * const i2s2_groups[] = {
1671 "dap3_fs_pp0",
1672 "dap3_din_pp1",
1673 "dap3_dout_pp2",
1674 "dap3_sclk_pp3",
1675};
1676
1677static const char * const i2s3_groups[] = {
1678 "dap4_fs_pp4",
1679 "dap4_din_pp5",
1680 "dap4_dout_pp6",
1681 "dap4_sclk_pp7",
1682};
1683
1684static const char * const i2s4_groups[] = {
1685 "pcc1",
1686 "pbb0",
1687 "pbb7",
1688 "pcc2",
1689};
1690
1691static const char * const irda_groups[] = {
1692 "uart2_rxd_pc3",
1693 "uart2_txd_pc2",
1694};
1695
1696static const char * const kbc_groups[] = {
1697 "kb_row0_pr0",
1698 "kb_row1_pr1",
1699 "kb_row2_pr2",
1700 "kb_row3_pr3",
1701 "kb_row4_pr4",
1702 "kb_row5_pr5",
1703 "kb_row6_pr6",
1704 "kb_row7_pr7",
1705 "kb_row8_ps0",
1706 "kb_row9_ps1",
1707 "kb_row10_ps2",
1708 "kb_col0_pq0",
1709 "kb_col1_pq1",
1710 "kb_col2_pq2",
1711 "kb_col3_pq3",
1712 "kb_col4_pq4",
1713 "kb_col5_pq5",
1714 "kb_col6_pq6",
1715 "kb_col7_pq7",
1716};
1717
1718static const char * const nand_groups[] = {
1719 "gmi_wp_n_pc7",
1720 "gmi_wait_pi7",
1721 "gmi_adv_n_pk0",
1722 "gmi_clk_pk1",
1723 "gmi_cs0_n_pj0",
1724 "gmi_cs1_n_pj2",
1725 "gmi_cs2_n_pk3",
1726 "gmi_cs3_n_pk4",
1727 "gmi_cs4_n_pk2",
1728 "gmi_cs6_n_pi3",
1729 "gmi_cs7_n_pi6",
1730 "gmi_ad0_pg0",
1731 "gmi_ad1_pg1",
1732 "gmi_ad2_pg2",
1733 "gmi_ad3_pg3",
1734 "gmi_ad4_pg4",
1735 "gmi_ad5_pg5",
1736 "gmi_ad6_pg6",
1737 "gmi_ad7_pg7",
1738 "gmi_ad8_ph0",
1739 "gmi_ad9_ph1",
1740 "gmi_ad10_ph2",
1741 "gmi_ad11_ph3",
1742 "gmi_ad12_ph4",
1743 "gmi_ad13_ph5",
1744 "gmi_ad14_ph6",
1745 "gmi_ad15_ph7",
1746 "gmi_wr_n_pi0",
1747 "gmi_oe_n_pi1",
1748 "gmi_dqs_p_pj3",
1749 "gmi_rst_n_pi4",
1750};
1751
1752static const char * const nand_alt_groups[] = {
1753 "gmi_cs6_n_pi3",
1754 "gmi_cs7_n_pi6",
1755 "gmi_rst_n_pi4",
1756};
1757
1758static const char * const owr_groups[] = {
1759 "pu0",
1760 "kb_col4_pq4",
1761 "owr",
1762 "sdmmc3_cd_n_pv2",
1763};
1764
1765static const char * const pmi_groups[] = {
1766 "pwr_int_n",
1767};
1768
1769static const char * const pwm0_groups[] = {
1770 "sdmmc1_dat2_py5",
1771 "uart3_rts_n_pc0",
1772 "pu3",
1773 "gmi_ad8_ph0",
1774 "sdmmc3_dat3_pb4",
1775};
1776
1777static const char * const pwm1_groups[] = {
1778 "sdmmc1_dat1_py6",
1779 "pu4",
1780 "gmi_ad9_ph1",
1781 "sdmmc3_dat2_pb5",
1782};
1783
1784static const char * const pwm2_groups[] = {
1785 "pu5",
1786 "gmi_ad10_ph2",
1787 "kb_col3_pq3",
1788 "sdmmc3_dat1_pb6",
1789};
1790
1791static const char * const pwm3_groups[] = {
1792 "pu6",
1793 "gmi_ad11_ph3",
1794 "sdmmc3_cmd_pa7",
1795};
1796
1797static const char * const pwron_groups[] = {
1798 "core_pwr_req",
1799};
1800
1801static const char * const reset_out_n_groups[] = {
1802 "reset_out_n",
1803};
1804
1805static const char * const rsvd1_groups[] = {
1806 "pv1",
1807 "hdmi_int_pn7",
1808 "pu1",
1809 "pu2",
1810 "gmi_wp_n_pc7",
1811 "gmi_adv_n_pk0",
1812 "gmi_cs0_n_pj0",
1813 "gmi_cs1_n_pj2",
1814 "gmi_ad0_pg0",
1815 "gmi_ad1_pg1",
1816 "gmi_ad2_pg2",
1817 "gmi_ad3_pg3",
1818 "gmi_ad4_pg4",
1819 "gmi_ad5_pg5",
1820 "gmi_ad6_pg6",
1821 "gmi_ad7_pg7",
1822 "gmi_wr_n_pi0",
1823 "gmi_oe_n_pi1",
1824 "gpio_x4_aud_px4",
1825 "gpio_x5_aud_px5",
1826 "gpio_x7_aud_px7",
1827
1828 "reset_out_n",
1829};
1830
1831static const char * const rsvd2_groups[] = {
1832 "pv0",
1833 "pv1",
1834 "sdmmc1_dat0_py7",
1835 "clk2_out_pw5",
1836 "clk2_req_pcc5",
1837 "hdmi_int_pn7",
1838 "ddc_scl_pv4",
1839 "ddc_sda_pv5",
1840 "uart3_txd_pw6",
1841 "uart3_rxd_pw7",
1842 "gen1_i2c_scl_pc4",
1843 "gen1_i2c_sda_pc5",
1844 "dap4_fs_pp4",
1845 "dap4_din_pp5",
1846 "dap4_dout_pp6",
1847 "dap4_sclk_pp7",
1848 "clk3_out_pee0",
1849 "clk3_req_pee1",
1850 "gmi_iordy_pi5",
1851 "gmi_a17_pb0",
1852 "gmi_a18_pb1",
1853 "gen2_i2c_scl_pt5",
1854 "gen2_i2c_sda_pt6",
1855 "sdmmc4_clk_pcc4",
1856 "sdmmc4_cmd_pt7",
1857 "sdmmc4_dat7_paa7",
1858 "pcc1",
1859 "pbb7",
1860 "pcc2",
1861 "pwr_i2c_scl_pz6",
1862 "pwr_i2c_sda_pz7",
1863 "kb_row0_pr0",
1864 "kb_row1_pr1",
1865 "kb_row2_pr2",
1866 "kb_row7_pr7",
1867 "kb_row8_ps0",
1868 "kb_row9_ps1",
1869 "kb_row10_ps2",
1870 "kb_col1_pq1",
1871 "kb_col2_pq2",
1872 "kb_col5_pq5",
1873 "kb_col6_pq6",
1874 "kb_col7_pq7",
1875 "sys_clk_req_pz5",
1876 "core_pwr_req",
1877 "cpu_pwr_req",
1878 "pwr_int_n",
1879 "owr",
1880 "spdif_out_pk5",
1881 "gpio_x1_aud_px1",
1882 "sdmmc3_clk_pa6",
1883 "sdmmc3_dat0_pb7",
1884 "gpio_w2_aud_pw2",
1885 "usb_vbus_en0_pn4",
1886 "usb_vbus_en1_pn5",
1887 "sdmmc3_clk_lb_out_pee4",
1888 "sdmmc3_clk_lb_in_pee5",
1889 "reset_out_n",
1890};
1891
1892static const char * const rsvd3_groups[] = {
1893 "pv0",
1894 "pv1",
1895 "sdmmc1_clk_pz0",
1896 "clk2_out_pw5",
1897 "clk2_req_pcc5",
1898 "hdmi_int_pn7",
1899 "ddc_scl_pv4",
1900 "ddc_sda_pv5",
1901 "uart2_rts_n_pj6",
1902 "uart2_cts_n_pj5",
1903 "uart3_txd_pw6",
1904 "uart3_rxd_pw7",
1905 "pu0",
1906 "pu1",
1907 "pu2",
1908 "gen1_i2c_scl_pc4",
1909 "gen1_i2c_sda_pc5",
1910 "dap4_din_pp5",
1911 "dap4_sclk_pp7",
1912 "clk3_out_pee0",
1913 "clk3_req_pee1",
1914 "pcc1",
1915 "cam_i2c_scl_pbb1",
1916 "cam_i2c_sda_pbb2",
1917 "pbb7",
1918 "pcc2",
1919 "pwr_i2c_scl_pz6",
1920 "pwr_i2c_sda_pz7",
1921 "kb_row0_pr0",
1922 "kb_row1_pr1",
1923 "kb_row2_pr2",
1924 "kb_row3_pr3",
1925 "kb_row9_ps1",
1926 "kb_row10_ps2",
1927 "clk_32k_out_pa0",
1928 "sys_clk_req_pz5",
1929 "core_pwr_req",
1930 "cpu_pwr_req",
1931 "pwr_int_n",
1932 "owr",
1933 "clk1_req_pee2",
1934 "clk1_out_pw4",
1935 "spdif_out_pk5",
1936 "spdif_in_pk6",
1937 "dap2_fs_pa2",
1938 "dap2_sclk_pa3",
1939 "dap2_din_pa4",
1940 "dap2_dout_pa5",
1941 "dvfs_pwm_px0",
1942 "gpio_x1_aud_px1",
1943 "gpio_x3_aud_px3",
1944 "dvfs_clk_px2",
1945 "sdmmc3_clk_pa6",
1946 "sdmmc3_dat0_pb7",
1947 "hdmi_cec_pee3",
1948 "sdmmc3_cd_n_pv2",
1949 "usb_vbus_en0_pn4",
1950 "usb_vbus_en1_pn5",
1951 "sdmmc3_clk_lb_out_pee4",
1952 "sdmmc3_clk_lb_in_pee5",
1953 "reset_out_n",
1954};
1955
1956static const char * const rsvd4_groups[] = {
1957 "pv0",
1958 "pv1",
1959 "sdmmc1_clk_pz0",
1960 "clk2_out_pw5",
1961 "clk2_req_pcc5",
1962 "hdmi_int_pn7",
1963 "ddc_scl_pv4",
1964 "ddc_sda_pv5",
1965 "pu0",
1966 "pu1",
1967 "pu2",
1968 "gen1_i2c_scl_pc4",
1969 "gen1_i2c_sda_pc5",
1970 "dap4_fs_pp4",
1971 "dap4_din_pp5",
1972 "dap4_dout_pp6",
1973 "dap4_sclk_pp7",
1974 "clk3_out_pee0",
1975 "clk3_req_pee1",
1976 "gmi_ad0_pg0",
1977 "gmi_ad1_pg1",
1978 "gmi_ad2_pg2",
1979 "gmi_ad3_pg3",
1980 "gmi_ad4_pg4",
1981 "gmi_ad12_ph4",
1982 "gmi_ad13_ph5",
1983 "gmi_rst_n_pi4",
1984 "gen2_i2c_scl_pt5",
1985 "gen2_i2c_sda_pt6",
1986 "sdmmc4_clk_pcc4",
1987 "sdmmc4_cmd_pt7",
1988 "sdmmc4_dat0_paa0",
1989 "sdmmc4_dat1_paa1",
1990 "sdmmc4_dat2_paa2",
1991 "sdmmc4_dat3_paa3",
1992 "sdmmc4_dat4_paa4",
1993 "sdmmc4_dat5_paa5",
1994 "sdmmc4_dat6_paa6",
1995 "sdmmc4_dat7_paa7",
1996 "cam_mclk_pcc0",
1997 "pcc1",
1998 "cam_i2c_scl_pbb1",
1999 "cam_i2c_sda_pbb2",
2000 "pbb3",
2001 "pbb4",
2002 "pbb5",
2003 "pbb6",
2004 "pbb7",
2005 "pcc2",
2006 "pwr_i2c_scl_pz6",
2007 "pwr_i2c_sda_pz7",
2008 "kb_row0_pr0",
2009 "kb_row1_pr1",
2010 "kb_row2_pr2",
2011 "kb_col2_pq2",
2012 "kb_col5_pq5",
2013 "kb_col6_pq6",
2014 "kb_col7_pq7",
2015 "clk_32k_out_pa0",
2016 "sys_clk_req_pz5",
2017 "core_pwr_req",
2018 "cpu_pwr_req",
2019 "pwr_int_n",
2020 "owr",
2021 "dap1_fs_pn0",
2022 "dap1_din_pn1",
2023 "dap1_dout_pn2",
2024 "dap1_sclk_pn3",
2025 "clk1_req_pee2",
2026 "clk1_out_pw4",
2027 "spdif_in_pk6",
2028 "spdif_out_pk5",
2029 "dap2_fs_pa2",
2030 "dap2_sclk_pa3",
2031 "dap2_din_pa4",
2032 "dap2_dout_pa5",
2033 "dvfs_pwm_px0",
2034 "gpio_x1_aud_px1",
2035 "gpio_x3_aud_px3",
2036 "dvfs_clk_px2",
2037 "gpio_x5_aud_px5",
2038 "gpio_x6_aud_px6",
2039 "gpio_x7_aud_px7",
2040 "sdmmc3_cd_n_pv2",
2041 "usb_vbus_en0_pn4",
2042 "usb_vbus_en1_pn5",
2043 "sdmmc3_clk_lb_in_pee5",
2044 "sdmmc3_clk_lb_out_pee4",
2045};
2046
2047static const char * const sdmmc1_groups[] = {
2048
2049 "sdmmc1_clk_pz0",
2050 "sdmmc1_cmd_pz1",
2051 "sdmmc1_dat3_py4",
2052 "sdmmc1_dat2_py5",
2053 "sdmmc1_dat1_py6",
2054 "sdmmc1_dat0_py7",
2055 "uart3_cts_n_pa1",
2056 "kb_col5_pq5",
2057 "sdmmc1_wp_n_pv3",
2058};
2059
2060static const char * const sdmmc2_groups[] = {
2061 "gmi_iordy_pi5",
2062 "gmi_clk_pk1",
2063 "gmi_cs2_n_pk3",
2064 "gmi_cs3_n_pk4",
2065 "gmi_cs7_n_pi6",
2066 "gmi_ad12_ph4",
2067 "gmi_ad13_ph5",
2068 "gmi_ad14_ph6",
2069 "gmi_ad15_ph7",
2070 "gmi_dqs_p_pj3",
2071};
2072
2073static const char * const sdmmc3_groups[] = {
2074 "kb_col4_pq4",
2075 "sdmmc3_clk_pa6",
2076 "sdmmc3_cmd_pa7",
2077 "sdmmc3_dat0_pb7",
2078 "sdmmc3_dat1_pb6",
2079 "sdmmc3_dat2_pb5",
2080 "sdmmc3_dat3_pb4",
2081 "hdmi_cec_pee3",
2082 "sdmmc3_cd_n_pv2",
2083 "sdmmc3_clk_lb_in_pee5",
2084 "sdmmc3_clk_lb_out_pee4",
2085};
2086
2087static const char * const sdmmc4_groups[] = {
2088 "sdmmc4_clk_pcc4",
2089 "sdmmc4_cmd_pt7",
2090 "sdmmc4_dat0_paa0",
2091 "sdmmc4_dat1_paa1",
2092 "sdmmc4_dat2_paa2",
2093 "sdmmc4_dat3_paa3",
2094 "sdmmc4_dat4_paa4",
2095 "sdmmc4_dat5_paa5",
2096 "sdmmc4_dat6_paa6",
2097 "sdmmc4_dat7_paa7",
2098};
2099
2100static const char * const soc_groups[] = {
2101 "gmi_cs1_n_pj2",
2102 "gmi_oe_n_pi1",
2103 "clk_32k_out_pa0",
2104 "hdmi_cec_pee3",
2105};
2106
2107static const char * const spdif_groups[] = {
2108 "sdmmc1_cmd_pz1",
2109 "sdmmc1_dat3_py4",
2110 "uart2_rxd_pc3",
2111 "uart2_txd_pc2",
2112 "spdif_in_pk6",
2113 "spdif_out_pk5",
2114};
2115
2116static const char * const spi1_groups[] = {
2117 "ulpi_clk_py0",
2118 "ulpi_dir_py1",
2119 "ulpi_nxt_py2",
2120 "ulpi_stp_py3",
2121 "gpio_x3_aud_px3",
2122 "gpio_x4_aud_px4",
2123 "gpio_x5_aud_px5",
2124 "gpio_x6_aud_px6",
2125 "gpio_x7_aud_px7",
2126 "gpio_w3_aud_pw3",
2127};
2128
2129static const char * const spi2_groups[] = {
2130 "ulpi_data4_po5",
2131 "ulpi_data5_po6",
2132 "ulpi_data6_po7",
2133 "ulpi_data7_po0",
2134 "kb_row4_pr4",
2135 "kb_row5_pr5",
2136 "kb_col0_pq0",
2137 "kb_col1_pq1",
2138 "kb_col2_pq2",
2139 "kb_col6_pq6",
2140 "kb_col7_pq7",
2141 "gpio_x4_aud_px4",
2142 "gpio_x5_aud_px5",
2143 "gpio_x6_aud_px6",
2144 "gpio_x7_aud_px7",
2145 "gpio_w2_aud_pw2",
2146 "gpio_w3_aud_pw3",
2147};
2148
2149static const char * const spi3_groups[] = {
2150 "ulpi_data0_po1",
2151 "ulpi_data1_po2",
2152 "ulpi_data2_po3",
2153 "ulpi_data3_po4",
2154 "sdmmc4_dat0_paa0",
2155 "sdmmc4_dat1_paa1",
2156 "sdmmc4_dat2_paa2",
2157 "sdmmc4_dat3_paa3",
2158 "sdmmc4_dat4_paa4",
2159 "sdmmc4_dat5_paa5",
2160 "sdmmc4_dat6_paa6",
2161 "sdmmc3_clk_pa6",
2162 "sdmmc3_cmd_pa7",
2163 "sdmmc3_dat0_pb7",
2164 "sdmmc3_dat1_pb6",
2165 "sdmmc3_dat2_pb5",
2166 "sdmmc3_dat3_pb4",
2167};
2168
2169static const char * const spi4_groups[] = {
2170 "sdmmc1_cmd_pz1",
2171 "sdmmc1_dat3_py4",
2172 "sdmmc1_dat2_py5",
2173 "sdmmc1_dat1_py6",
2174 "sdmmc1_dat0_py7",
2175 "uart2_rxd_pc3",
2176 "uart2_txd_pc2",
2177 "uart2_rts_n_pj6",
2178 "uart2_cts_n_pj5",
2179 "uart3_txd_pw6",
2180 "uart3_rxd_pw7",
2181 "uart3_cts_n_pa1",
2182 "gmi_wait_pi7",
2183 "gmi_cs6_n_pi3",
2184 "gmi_ad5_pg5",
2185 "gmi_ad6_pg6",
2186 "gmi_ad7_pg7",
2187 "gmi_a19_pk7",
2188 "gmi_wr_n_pi0",
2189 "sdmmc1_wp_n_pv3",
2190};
2191
2192static const char * const spi5_groups[] = {
2193 "ulpi_clk_py0",
2194 "ulpi_dir_py1",
2195 "ulpi_nxt_py2",
2196 "ulpi_stp_py3",
2197 "dap3_fs_pp0",
2198 "dap3_din_pp1",
2199 "dap3_dout_pp2",
2200 "dap3_sclk_pp3",
2201};
2202
2203static const char * const spi6_groups[] = {
2204 "dvfs_pwm_px0",
2205 "gpio_x1_aud_px1",
2206 "gpio_x3_aud_px3",
2207 "dvfs_clk_px2",
2208 "gpio_x6_aud_px6",
2209 "gpio_w2_aud_pw2",
2210 "gpio_w3_aud_pw3",
2211};
2212
2213static const char * const sysclk_groups[] = {
2214 "sys_clk_req_pz5",
2215};
2216
2217static const char * const trace_groups[] = {
2218 "gmi_iordy_pi5",
2219 "gmi_adv_n_pk0",
2220 "gmi_clk_pk1",
2221 "gmi_cs2_n_pk3",
2222 "gmi_cs4_n_pk2",
2223 "gmi_a16_pj7",
2224 "gmi_a17_pb0",
2225 "gmi_a18_pb1",
2226 "gmi_a19_pk7",
2227 "gmi_dqs_p_pj3",
2228};
2229
2230static const char * const uarta_groups[] = {
2231 "ulpi_data0_po1",
2232 "ulpi_data1_po2",
2233 "ulpi_data2_po3",
2234 "ulpi_data3_po4",
2235 "ulpi_data4_po5",
2236 "ulpi_data5_po6",
2237 "ulpi_data6_po7",
2238 "ulpi_data7_po0",
2239 "sdmmc1_cmd_pz1",
2240 "sdmmc1_dat3_py4",
2241 "sdmmc1_dat2_py5",
2242 "sdmmc1_dat1_py6",
2243 "sdmmc1_dat0_py7",
2244 "uart2_rxd_pc3",
2245 "uart2_txd_pc2",
2246 "uart2_rts_n_pj6",
2247 "uart2_cts_n_pj5",
2248 "pu0",
2249 "pu1",
2250 "pu2",
2251 "pu3",
2252 "pu4",
2253 "pu5",
2254 "pu6",
2255 "kb_row7_pr7",
2256 "kb_row8_ps0",
2257 "kb_row9_ps1",
2258 "kb_row10_ps2",
2259 "kb_col3_pq3",
2260 "kb_col4_pq4",
2261 "sdmmc3_cmd_pa7",
2262 "sdmmc3_dat1_pb6",
2263 "sdmmc1_wp_n_pv3",
2264};
2265
2266static const char * const uartb_groups[] = {
2267 "uart2_rts_n_pj6",
2268 "uart2_cts_n_pj5",
2269};
2270
2271static const char * const uartc_groups[] = {
2272 "uart3_txd_pw6",
2273 "uart3_rxd_pw7",
2274 "uart3_cts_n_pa1",
2275 "uart3_rts_n_pc0",
2276};
2277
2278static const char * const uartd_groups[] = {
2279 "ulpi_clk_py0",
2280 "ulpi_dir_py1",
2281 "ulpi_nxt_py2",
2282 "ulpi_stp_py3",
2283 "gmi_a16_pj7",
2284 "gmi_a17_pb0",
2285 "gmi_a18_pb1",
2286 "gmi_a19_pk7",
2287};
2288
2289static const char * const ulpi_groups[] = {
2290 "ulpi_data0_po1",
2291 "ulpi_data1_po2",
2292 "ulpi_data2_po3",
2293 "ulpi_data3_po4",
2294 "ulpi_data4_po5",
2295 "ulpi_data5_po6",
2296 "ulpi_data6_po7",
2297 "ulpi_data7_po0",
2298 "ulpi_clk_py0",
2299 "ulpi_dir_py1",
2300 "ulpi_nxt_py2",
2301 "ulpi_stp_py3",
2302};
2303
2304static const char * const usb_groups[] = {
2305 "pv0",
2306 "pu6",
2307 "gmi_cs0_n_pj0",
2308 "gmi_cs4_n_pk2",
2309 "gmi_ad11_ph3",
2310 "kb_col0_pq0",
2311 "spdif_in_pk6",
2312 "usb_vbus_en0_pn4",
2313 "usb_vbus_en1_pn5",
2314};
2315
2316static const char * const vgp1_groups[] = {
2317 "cam_i2c_scl_pbb1",
2318};
2319
2320static const char * const vgp2_groups[] = {
2321 "cam_i2c_sda_pbb2",
2322};
2323
2324static const char * const vgp3_groups[] = {
2325 "pbb3",
2326};
2327
2328static const char * const vgp4_groups[] = {
2329 "pbb4",
2330};
2331
2332static const char * const vgp5_groups[] = {
2333 "pbb5",
2334};
2335
2336static const char * const vgp6_groups[] = {
2337 "pbb6",
2338};
2339
2340static const char * const vi_groups[] = {
2341 "cam_mclk_pcc0",
2342 "pbb0",
2343};
2344
2345static const char * const vi_alt1_groups[] = {
2346 "cam_mclk_pcc0",
2347 "pbb0",
2348};
2349
2350static const char * const vi_alt3_groups[] = {
2351 "cam_mclk_pcc0",
2352 "pbb0",
2353};
2354
2355#define FUNCTION(fname) \
2356 { \
2357 .name = #fname, \
2358 .groups = fname##_groups, \
2359 .ngroups = ARRAY_SIZE(fname##_groups), \
2360 }
2361
2362static const struct tegra_function tegra114_functions[] = {
2363 FUNCTION(blink),
2364 FUNCTION(cec),
2365 FUNCTION(cldvfs),
2366 FUNCTION(clk12),
2367 FUNCTION(cpu),
2368 FUNCTION(dap),
2369 FUNCTION(dap1),
2370 FUNCTION(dap2),
2371 FUNCTION(dev3),
2372 FUNCTION(displaya),
2373 FUNCTION(displaya_alt),
2374 FUNCTION(displayb),
2375 FUNCTION(dtv),
2376 FUNCTION(emc_dll),
2377 FUNCTION(extperiph1),
2378 FUNCTION(extperiph2),
2379 FUNCTION(extperiph3),
2380 FUNCTION(gmi),
2381 FUNCTION(gmi_alt),
2382 FUNCTION(hda),
2383 FUNCTION(hsi),
2384 FUNCTION(i2c1),
2385 FUNCTION(i2c2),
2386 FUNCTION(i2c3),
2387 FUNCTION(i2c4),
2388 FUNCTION(i2cpwr),
2389 FUNCTION(i2s0),
2390 FUNCTION(i2s1),
2391 FUNCTION(i2s2),
2392 FUNCTION(i2s3),
2393 FUNCTION(i2s4),
2394 FUNCTION(irda),
2395 FUNCTION(kbc),
2396 FUNCTION(nand),
2397 FUNCTION(nand_alt),
2398 FUNCTION(owr),
2399 FUNCTION(pmi),
2400 FUNCTION(pwm0),
2401 FUNCTION(pwm1),
2402 FUNCTION(pwm2),
2403 FUNCTION(pwm3),
2404 FUNCTION(pwron),
2405 FUNCTION(reset_out_n),
2406 FUNCTION(rsvd1),
2407 FUNCTION(rsvd2),
2408 FUNCTION(rsvd3),
2409 FUNCTION(rsvd4),
2410 FUNCTION(sdmmc1),
2411 FUNCTION(sdmmc2),
2412 FUNCTION(sdmmc3),
2413 FUNCTION(sdmmc4),
2414 FUNCTION(soc),
2415 FUNCTION(spdif),
2416 FUNCTION(spi1),
2417 FUNCTION(spi2),
2418 FUNCTION(spi3),
2419 FUNCTION(spi4),
2420 FUNCTION(spi5),
2421 FUNCTION(spi6),
2422 FUNCTION(sysclk),
2423 FUNCTION(trace),
2424 FUNCTION(uarta),
2425 FUNCTION(uartb),
2426 FUNCTION(uartc),
2427 FUNCTION(uartd),
2428 FUNCTION(ulpi),
2429 FUNCTION(usb),
2430 FUNCTION(vgp1),
2431 FUNCTION(vgp2),
2432 FUNCTION(vgp3),
2433 FUNCTION(vgp4),
2434 FUNCTION(vgp5),
2435 FUNCTION(vgp6),
2436 FUNCTION(vi),
2437 FUNCTION(vi_alt1),
2438 FUNCTION(vi_alt3),
2439};
2440
2441#define DRV_PINGROUP_REG_START 0x868 /* bank 0 */
2442#define PINGROUP_REG_START 0x3000 /* bank 1 */
2443
2444#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_START)
2445#define PINGROUP_REG_N(r) -1
2446
2447#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
2448 { \
2449 .name = #pg_name, \
2450 .pins = pg_name##_pins, \
2451 .npins = ARRAY_SIZE(pg_name##_pins), \
2452 .funcs = { \
2453 TEGRA_MUX_##f0, \
2454 TEGRA_MUX_##f1, \
2455 TEGRA_MUX_##f2, \
2456 TEGRA_MUX_##f3, \
2457 }, \
2458 .func_safe = TEGRA_MUX_##f_safe, \
2459 .mux_reg = PINGROUP_REG_Y(r), \
2460 .mux_bank = 1, \
2461 .mux_bit = 0, \
2462 .pupd_reg = PINGROUP_REG_Y(r), \
2463 .pupd_bank = 1, \
2464 .pupd_bit = 2, \
2465 .tri_reg = PINGROUP_REG_Y(r), \
2466 .tri_bank = 1, \
2467 .tri_bit = 4, \
2468 .einput_reg = PINGROUP_REG_Y(r), \
2469 .einput_bank = 1, \
2470 .einput_bit = 5, \
2471 .odrain_reg = PINGROUP_REG_##od(r), \
2472 .odrain_bank = 1, \
2473 .odrain_bit = 6, \
2474 .lock_reg = PINGROUP_REG_Y(r), \
2475 .lock_bank = 1, \
2476 .lock_bit = 7, \
2477 .ioreset_reg = PINGROUP_REG_##ior(r), \
2478 .ioreset_bank = 1, \
2479 .ioreset_bit = 8, \
2480 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
2481 .rcv_sel_bank = 1, \
2482 .rcv_sel_bit = 9, \
2483 .drv_reg = -1, \
2484 .drvtype_reg = -1, \
2485 }
2486
2487#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_START)
2488#define DRV_PINGROUP_DVRTYPE_N(r) -1
2489
2490#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2491 drvdn_b, drvdn_w, drvup_b, drvup_w, \
2492 slwr_b, slwr_w, slwf_b, slwf_w, \
2493 drvtype) \
2494 { \
2495 .name = "drive_" #pg_name, \
2496 .pins = drive_##pg_name##_pins, \
2497 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2498 .mux_reg = -1, \
2499 .pupd_reg = -1, \
2500 .tri_reg = -1, \
2501 .einput_reg = -1, \
2502 .odrain_reg = -1, \
2503 .lock_reg = -1, \
2504 .ioreset_reg = -1, \
2505 .rcv_sel_reg = -1, \
2506 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \
2507 .drv_bank = 0, \
2508 .hsm_bit = hsm_b, \
2509 .schmitt_bit = schmitt_b, \
2510 .lpmd_bit = lpmd_b, \
2511 .drvdn_bit = drvdn_b, \
2512 .drvdn_width = drvdn_w, \
2513 .drvup_bit = drvup_b, \
2514 .drvup_width = drvup_w, \
2515 .slwr_bit = slwr_b, \
2516 .slwr_width = slwr_w, \
2517 .slwf_bit = slwf_b, \
2518 .slwf_width = slwf_w, \
2519 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \
2520 .drvtype_bank = 0, \
2521 .drvtype_bit = 6, \
2522 }
2523
2524static const struct tegra_pingroup tegra114_groups[] = {
2525 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
2526 /* FIXME: Fill in correct data in safe column */
2527 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N),
2528 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N),
2529 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N),
2530 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, ULPI, 0x300c, N, N, N),
2531 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, ULPI, 0x3010, N, N, N),
2532 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, ULPI, 0x3014, N, N, N),
2533 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, ULPI, 0x3018, N, N, N),
2534 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, ULPI, 0x301c, N, N, N),
2535 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3020, N, N, N),
2536 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3024, N, N, N),
2537 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3028, N, N, N),
2538 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, ULPI, 0x302c, N, N, N),
2539 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N),
2540 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N),
2541 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3038, N, N, N),
2542 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x303c, N, N, N),
2543 PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x3040, N, N, N),
2544 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3044, N, N, N),
2545 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD4, 0x3048, N, N, N),
2546 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N),
2547 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N),
2548 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N),
2549 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N),
2550 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, RSVD2, 0x305c, N, N, N),
2551 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, RSVD4, 0x3068, N, N, N),
2552 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, RSVD4, 0x306c, N, N, N),
2553 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3110, N, N, Y),
2554 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3114, N, N, Y),
2555 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3118, N, N, Y),
2556 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N),
2557 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N),
2558 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x316c, N, N, N),
2559 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x3170, N, N, N),
2560 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3174, N, N, N),
2561 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3178, N, N, N),
2562 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, UARTC, 0x317c, N, N, N),
2563 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, UARTC, 0x3180, N, N, N),
2564 PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, RSVD4, 0x3184, N, N, N),
2565 PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x3188, N, N, N),
2566 PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x318c, N, N, N),
2567 PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, PWM0, 0x3190, N, N, N),
2568 PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, PWM1, 0x3194, N, N, N),
2569 PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, PWM2, 0x3198, N, N, N),
2570 PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, PWM3, 0x319c, N, N, N),
2571 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a0, Y, N, N),
2572 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a4, Y, N, N),
2573 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31a8, N, N, N),
2574 PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31ac, N, N, N),
2575 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31b0, N, N, N),
2576 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b4, N, N, N),
2577 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b8, N, N, N),
2578 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N),
2579 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N),
2580 PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, RSVD2, 0x31c4, N, N, N),
2581 PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, NAND, 0x31c8, N, N, N),
2582 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, RSVD1, 0x31cc, N, N, N),
2583 PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, GMI, 0x31d0, N, N, N),
2584 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, RSVD1, 0x31d4, N, N, N),
2585 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, RSVD1, 0x31d8, N, N, N),
2586 PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, GMI, 0x31dc, N, N, N),
2587 PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, GMI, 0x31e0, N, N, N),
2588 PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, GMI, 0x31e4, N, N, N),
2589 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, NAND, 0x31e8, N, N, N),
2590 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, NAND, 0x31ec, N, N, N),
2591 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f0, N, N, N),
2592 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f4, N, N, N),
2593 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f8, N, N, N),
2594 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31fc, N, N, N),
2595 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3200, N, N, N),
2596 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3204, N, N, N),
2597 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3208, N, N, N),
2598 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, RSVD1, 0x320c, N, N, N),
2599 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, GMI, 0x3210, N, N, N),
2600 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, GMI, 0x3214, N, N, N),
2601 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, GMI, 0x3218, N, N, N),
2602 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, GMI, 0x321c, N, N, N),
2603 PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3220, N, N, N),
2604 PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3224, N, N, N),
2605 PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, GMI, 0x3228, N, N, N),
2606 PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, GMI, 0x322c, N, N, N),
2607 PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, GMI, 0x3230, N, N, N),
2608 PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3234, N, N, N),
2609 PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3238, N, N, N),
2610 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, GMI, 0x323c, N, N, N),
2611 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3240, N, N, N),
2612 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, RSVD1, 0x3244, N, N, N),
2613 PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, NAND, 0x3248, N, N, N),
2614 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, RSVD4, 0x324c, N, N, N),
2615 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3250, Y, N, N),
2616 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3254, Y, N, N),
2617 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x3258, N, Y, N),
2618 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x325c, N, Y, N),
2619 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3260, N, Y, N),
2620 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3264, N, Y, N),
2621 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3268, N, Y, N),
2622 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x326c, N, Y, N),
2623 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3270, N, Y, N),
2624 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3274, N, Y, N),
2625 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3278, N, Y, N),
2626 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x327c, N, Y, N),
2627 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, RSVD4, 0x3284, N, N, N),
2628 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3288, N, N, N),
2629 PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, I2S4, 0x328c, N, N, N),
2630 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, RSVD4, 0x3290, Y, N, N),
2631 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, RSVD4, 0x3294, Y, N, N),
2632 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x3298, N, N, N),
2633 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x329c, N, N, N),
2634 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a0, N, N, N),
2635 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a4, N, N, N),
2636 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32a8, N, N, N),
2637 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N, N),
2638 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N, N),
2639 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N, N),
2640 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N),
2641 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N),
2642 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N),
2643 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32c8, N, N, N),
2644 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32cc, N, N, N),
2645 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32d0, N, N, N),
2646 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N),
2647 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N),
2648 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N),
2649 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e0, N, N, N),
2650 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e4, N, N, N),
2651 PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, KBC, 0x32fc, N, N, N),
2652 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, RSVD2, 0x3300, N, N, N),
2653 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD2, 0x3304, N, N, N),
2654 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N),
2655 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N),
2656 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, RSVD4, 0x3310, N, N, N),
2657 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3314, N, N, N),
2658 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3318, N, N, N),
2659 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD4, 0x331c, N, N, N),
2660 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, RSVD4, 0x3320, N, N, N),
2661 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N, N),
2662 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N, N),
2663 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N, N),
2664 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3334, N, N, Y),
2665 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N),
2666 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N),
2667 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3340, N, N, N),
2668 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3344, N, N, N),
2669 PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, RSVD4, 0x3348, N, N, N),
2670 PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD4, 0x334c, N, N, N),
2671 PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, RSVD4, 0x3350, N, N, N),
2672 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, RSVD4, 0x3354, N, N, N),
2673 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3358, N, N, N),
2674 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x335c, N, N, N),
2675 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3360, N, N, N),
2676 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3364, N, N, N),
2677 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3368, N, N, N),
2678 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, RSVD4, 0x336c, N, N, N),
2679 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, RSVD4, 0x3370, N, N, N),
2680 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3374, N, N, N),
2681 PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, RSVD1, 0x3378, N, N, N),
2682 PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, RSVD1, 0x337c, N, N, N),
2683 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, RSVD4, 0x3380, N, N, N),
2684 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, RSVD4, 0x3384, N, N, N),
2685 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3390, N, N, N),
2686 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N),
2687 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3398, N, N, N),
2688 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N),
2689 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N),
2690 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N),
2691 PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, RSVD3, 0x33e0, Y, N, N),
2692 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N),
2693 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, RSVD4, 0x33e8, N, N, N),
2694 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N),
2695 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI6, 0x33f0, N, N, N),
2696 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f4, Y, N, N),
2697 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f8, Y, N, N),
2698 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x33fc, N, N, N),
2699 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x3400, N, N, N),
2700 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD3, 0x3408, N, N, N),
2701
2702 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
2703 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2704 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2705 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2706 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2707 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2708 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2709 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2710 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2711 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2712 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2713 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2714 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2715 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2716 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2717 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
2718 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2719 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2720 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2721 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2722 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2723 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
2724 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2725 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
2726 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2727 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2728 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2729 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2730 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2731 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2732};
2733
2734static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
2735 .ngpios = NUM_GPIOS,
2736 .pins = tegra114_pins,
2737 .npins = ARRAY_SIZE(tegra114_pins),
2738 .functions = tegra114_functions,
2739 .nfunctions = ARRAY_SIZE(tegra114_functions),
2740 .groups = tegra114_groups,
2741 .ngroups = ARRAY_SIZE(tegra114_groups),
2742};
2743
2744static int tegra114_pinctrl_probe(struct platform_device *pdev)
2745{
2746 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
2747}
2748
2749static struct of_device_id tegra114_pinctrl_of_match[] = {
2750 { .compatible = "nvidia,tegra114-pinmux", },
2751 { },
2752};
2753MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match);
2754
2755static struct platform_driver tegra114_pinctrl_driver = {
2756 .driver = {
2757 .name = "tegra114-pinctrl",
2758 .owner = THIS_MODULE,
2759 .of_match_table = tegra114_pinctrl_of_match,
2760 },
2761 .probe = tegra114_pinctrl_probe,
2762 .remove = tegra_pinctrl_remove,
2763};
2764module_platform_driver(tegra114_pinctrl_driver);
2765
2766MODULE_ALIAS("platform:tegra114-pinctrl");
2767MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
2768MODULE_DESCRIPTION("NVIDIA Tegra114 pincontrol driver");
2769MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index e848189038f0..fcfb7d012c5b 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -2624,7 +2624,9 @@ static const struct tegra_function tegra20_functions[] = {
2624 .odrain_reg = -1, \ 2624 .odrain_reg = -1, \
2625 .lock_reg = -1, \ 2625 .lock_reg = -1, \
2626 .ioreset_reg = -1, \ 2626 .ioreset_reg = -1, \
2627 .rcv_sel_reg = -1, \
2627 .drv_reg = -1, \ 2628 .drv_reg = -1, \
2629 .drvtype_reg = -1, \
2628 } 2630 }
2629 2631
2630/* Pin groups with only pull up and pull down control */ 2632/* Pin groups with only pull up and pull down control */
@@ -2642,7 +2644,9 @@ static const struct tegra_function tegra20_functions[] = {
2642 .odrain_reg = -1, \ 2644 .odrain_reg = -1, \
2643 .lock_reg = -1, \ 2645 .lock_reg = -1, \
2644 .ioreset_reg = -1, \ 2646 .ioreset_reg = -1, \
2647 .rcv_sel_reg = -1, \
2645 .drv_reg = -1, \ 2648 .drv_reg = -1, \
2649 .drvtype_reg = -1, \
2646 } 2650 }
2647 2651
2648/* Pin groups for drive strength registers (configurable version) */ 2652/* Pin groups for drive strength registers (configurable version) */
@@ -2660,6 +2664,7 @@ static const struct tegra_function tegra20_functions[] = {
2660 .odrain_reg = -1, \ 2664 .odrain_reg = -1, \
2661 .lock_reg = -1, \ 2665 .lock_reg = -1, \
2662 .ioreset_reg = -1, \ 2666 .ioreset_reg = -1, \
2667 .rcv_sel_reg = -1, \
2663 .drv_reg = ((r) - PINGROUP_REG_A), \ 2668 .drv_reg = ((r) - PINGROUP_REG_A), \
2664 .drv_bank = 3, \ 2669 .drv_bank = 3, \
2665 .hsm_bit = hsm_b, \ 2670 .hsm_bit = hsm_b, \
@@ -2673,6 +2678,7 @@ static const struct tegra_function tegra20_functions[] = {
2673 .slwr_width = slwr_w, \ 2678 .slwr_width = slwr_w, \
2674 .slwf_bit = slwf_b, \ 2679 .slwf_bit = slwf_b, \
2675 .slwf_width = slwf_w, \ 2680 .slwf_width = slwf_w, \
2681 .drvtype_reg = -1, \
2676 } 2682 }
2677 2683
2678/* Pin groups for drive strength registers (simple version) */ 2684/* Pin groups for drive strength registers (simple version) */
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 9ad87ea735d4..2300deba25bd 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -3384,7 +3384,9 @@ static const struct tegra_function tegra30_functions[] = {
3384 .ioreset_reg = PINGROUP_REG_##ior(r), \ 3384 .ioreset_reg = PINGROUP_REG_##ior(r), \
3385 .ioreset_bank = 1, \ 3385 .ioreset_bank = 1, \
3386 .ioreset_bit = 8, \ 3386 .ioreset_bit = 8, \
3387 .rcv_sel_reg = -1, \
3387 .drv_reg = -1, \ 3388 .drv_reg = -1, \
3389 .drvtype_reg = -1, \
3388 } 3390 }
3389 3391
3390#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 3392#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
@@ -3401,6 +3403,7 @@ static const struct tegra_function tegra30_functions[] = {
3401 .odrain_reg = -1, \ 3403 .odrain_reg = -1, \
3402 .lock_reg = -1, \ 3404 .lock_reg = -1, \
3403 .ioreset_reg = -1, \ 3405 .ioreset_reg = -1, \
3406 .rcv_sel_reg = -1, \
3404 .drv_reg = ((r) - DRV_PINGROUP_REG_A), \ 3407 .drv_reg = ((r) - DRV_PINGROUP_REG_A), \
3405 .drv_bank = 0, \ 3408 .drv_bank = 0, \
3406 .hsm_bit = hsm_b, \ 3409 .hsm_bit = hsm_b, \
@@ -3414,6 +3417,7 @@ static const struct tegra_function tegra30_functions[] = {
3414 .slwr_width = slwr_w, \ 3417 .slwr_width = slwr_w, \
3415 .slwf_bit = slwf_b, \ 3418 .slwf_bit = slwf_b, \
3416 .slwf_width = slwf_w, \ 3419 .slwf_width = slwf_w, \
3420 .drvtype_reg = -1, \
3417 } 3421 }
3418 3422
3419static const struct tegra_pingroup tegra30_groups[] = { 3423static const struct tegra_pingroup tegra30_groups[] = {
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index 5f0eb04c2336..53cb6a3a56ed 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -441,17 +441,17 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
441 if (port == PORT3) 441 if (port == PORT3)
442 reg = GPIO3_OD; 442 reg = GPIO3_OD;
443 else 443 else
444 reg = GPIO_OD(port); 444 reg = GPIO_OD(pin);
445 *config = LTQ_PINCONF_PACK(param, 445 *config = LTQ_PINCONF_PACK(param,
446 !!gpio_getbit(info->membase[0], reg, PORT_PIN(port))); 446 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
447 break; 447 break;
448 448
449 case LTQ_PINCONF_PARAM_PULL: 449 case LTQ_PINCONF_PARAM_PULL:
450 if (port == PORT3) 450 if (port == PORT3)
451 reg = GPIO3_PUDEN; 451 reg = GPIO3_PUDEN;
452 else 452 else
453 reg = GPIO_PUDEN(port); 453 reg = GPIO_PUDEN(pin);
454 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) { 454 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
455 *config = LTQ_PINCONF_PACK(param, 0); 455 *config = LTQ_PINCONF_PACK(param, 0);
456 break; 456 break;
457 } 457 }
@@ -459,13 +459,18 @@ static int xway_pinconf_get(struct pinctrl_dev *pctldev,
459 if (port == PORT3) 459 if (port == PORT3)
460 reg = GPIO3_PUDSEL; 460 reg = GPIO3_PUDSEL;
461 else 461 else
462 reg = GPIO_PUDSEL(port); 462 reg = GPIO_PUDSEL(pin);
463 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) 463 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
464 *config = LTQ_PINCONF_PACK(param, 2); 464 *config = LTQ_PINCONF_PACK(param, 2);
465 else 465 else
466 *config = LTQ_PINCONF_PACK(param, 1); 466 *config = LTQ_PINCONF_PACK(param, 1);
467 break; 467 break;
468 468
469 case LTQ_PINCONF_PARAM_OUTPUT:
470 reg = GPIO_DIR(pin);
471 *config = LTQ_PINCONF_PACK(param,
472 gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
473 break;
469 default: 474 default:
470 dev_err(pctldev->dev, "Invalid config param %04x\n", param); 475 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
471 return -ENOTSUPP; 476 return -ENOTSUPP;
@@ -488,33 +493,44 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev,
488 if (port == PORT3) 493 if (port == PORT3)
489 reg = GPIO3_OD; 494 reg = GPIO3_OD;
490 else 495 else
491 reg = GPIO_OD(port); 496 reg = GPIO_OD(pin);
492 gpio_setbit(info->membase[0], reg, PORT_PIN(port)); 497 if (arg == 0)
498 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
499 else
500 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
493 break; 501 break;
494 502
495 case LTQ_PINCONF_PARAM_PULL: 503 case LTQ_PINCONF_PARAM_PULL:
496 if (port == PORT3) 504 if (port == PORT3)
497 reg = GPIO3_PUDEN; 505 reg = GPIO3_PUDEN;
498 else 506 else
499 reg = GPIO_PUDEN(port); 507 reg = GPIO_PUDEN(pin);
500 if (arg == 0) { 508 if (arg == 0) {
501 gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); 509 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
502 break; 510 break;
503 } 511 }
504 gpio_setbit(info->membase[0], reg, PORT_PIN(port)); 512 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
505 513
506 if (port == PORT3) 514 if (port == PORT3)
507 reg = GPIO3_PUDSEL; 515 reg = GPIO3_PUDSEL;
508 else 516 else
509 reg = GPIO_PUDSEL(port); 517 reg = GPIO_PUDSEL(pin);
510 if (arg == 1) 518 if (arg == 1)
511 gpio_clearbit(info->membase[0], reg, PORT_PIN(port)); 519 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
512 else if (arg == 2) 520 else if (arg == 2)
513 gpio_setbit(info->membase[0], reg, PORT_PIN(port)); 521 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
514 else 522 else
515 dev_err(pctldev->dev, "Invalid pull value %d\n", arg); 523 dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
516 break; 524 break;
517 525
526 case LTQ_PINCONF_PARAM_OUTPUT:
527 reg = GPIO_DIR(pin);
528 if (arg == 0)
529 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
530 else
531 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
532 break;
533
518 default: 534 default:
519 dev_err(pctldev->dev, "Invalid config param %04x\n", param); 535 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
520 return -ENOTSUPP; 536 return -ENOTSUPP;
@@ -522,9 +538,24 @@ static int xway_pinconf_set(struct pinctrl_dev *pctldev,
522 return 0; 538 return 0;
523} 539}
524 540
541int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
542 unsigned selector,
543 unsigned long config)
544{
545 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
546 int i, ret = 0;
547
548 for (i = 0; i < info->grps[selector].npins && !ret; i++)
549 ret = xway_pinconf_set(pctldev,
550 info->grps[selector].pins[i], config);
551
552 return ret;
553}
554
525static struct pinconf_ops xway_pinconf_ops = { 555static struct pinconf_ops xway_pinconf_ops = {
526 .pin_config_get = xway_pinconf_get, 556 .pin_config_get = xway_pinconf_get,
527 .pin_config_set = xway_pinconf_set, 557 .pin_config_set = xway_pinconf_set,
558 .pin_config_group_set = xway_pinconf_group_set,
528}; 559};
529 560
530static struct pinctrl_desc xway_pctrl_desc = { 561static struct pinctrl_desc xway_pctrl_desc = {
@@ -558,6 +589,7 @@ static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
558static const struct ltq_cfg_param xway_cfg_params[] = { 589static const struct ltq_cfg_param xway_cfg_params[] = {
559 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL}, 590 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
560 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN}, 591 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
592 {"lantiq,output", LTQ_PINCONF_PARAM_OUTPUT},
561}; 593};
562 594
563static struct ltq_pinmux_info xway_info = { 595static struct ltq_pinmux_info xway_info = {
diff --git a/include/linux/device.h b/include/linux/device.h
index 43dcda937ddf..001f6637aa47 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -21,6 +21,7 @@
21#include <linux/compiler.h> 21#include <linux/compiler.h>
22#include <linux/types.h> 22#include <linux/types.h>
23#include <linux/mutex.h> 23#include <linux/mutex.h>
24#include <linux/pinctrl/devinfo.h>
24#include <linux/pm.h> 25#include <linux/pm.h>
25#include <linux/atomic.h> 26#include <linux/atomic.h>
26#include <linux/ratelimit.h> 27#include <linux/ratelimit.h>
@@ -620,6 +621,8 @@ struct acpi_dev_node {
620 * @pm_domain: Provide callbacks that are executed during system suspend, 621 * @pm_domain: Provide callbacks that are executed during system suspend,
621 * hibernation, system resume and during runtime PM transitions 622 * hibernation, system resume and during runtime PM transitions
622 * along with subsystem-level and driver-level callbacks. 623 * along with subsystem-level and driver-level callbacks.
624 * @pins: For device pin management.
625 * See Documentation/pinctrl.txt for details.
623 * @numa_node: NUMA node this device is close to. 626 * @numa_node: NUMA node this device is close to.
624 * @dma_mask: Dma mask (if dma'ble device). 627 * @dma_mask: Dma mask (if dma'ble device).
625 * @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all 628 * @coherent_dma_mask: Like dma_mask, but for alloc_coherent mapping as not all
@@ -672,6 +675,10 @@ struct device {
672 struct dev_pm_info power; 675 struct dev_pm_info power;
673 struct dev_pm_domain *pm_domain; 676 struct dev_pm_domain *pm_domain;
674 677
678#ifdef CONFIG_PINCTRL
679 struct dev_pin_info *pins;
680#endif
681
675#ifdef CONFIG_NUMA 682#ifdef CONFIG_NUMA
676 int numa_node; /* NUMA node this device is close to */ 683 int numa_node; /* NUMA node this device is close to */
677#endif 684#endif
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
index 2387c207ea86..172b2f201ae0 100644
--- a/include/linux/mfd/abx500/ab8500-gpio.h
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
@@ -14,10 +14,20 @@
14 * registers. 14 * registers.
15 */ 15 */
16 16
17struct ab8500_gpio_platform_data { 17struct abx500_gpio_platform_data {
18 int gpio_base; 18 int gpio_base;
19 u32 irq_base; 19};
20 u8 config_reg[8]; 20
21enum abx500_gpio_pull_updown {
22 ABX500_GPIO_PULL_DOWN = 0x0,
23 ABX500_GPIO_PULL_NONE = 0x1,
24 ABX500_GPIO_PULL_UP = 0x3,
25};
26
27enum abx500_gpio_vinsel {
28 ABX500_GPIO_VINSEL_VBAT = 0x0,
29 ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
30 ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
21}; 31};
22 32
23#endif /* _AB8500_GPIO_H */ 33#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 1cb5698b4d76..fc0534483c72 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -24,7 +24,7 @@ enum ab8500_version {
24 AB8500_VERSION_AB8500 = 0x0, 24 AB8500_VERSION_AB8500 = 0x0,
25 AB8500_VERSION_AB8505 = 0x1, 25 AB8500_VERSION_AB8505 = 0x1,
26 AB8500_VERSION_AB9540 = 0x2, 26 AB8500_VERSION_AB9540 = 0x2,
27 AB8500_VERSION_AB8540 = 0x3, 27 AB8500_VERSION_AB8540 = 0x4,
28 AB8500_VERSION_UNDEFINED, 28 AB8500_VERSION_UNDEFINED,
29}; 29};
30 30
@@ -32,6 +32,7 @@ enum ab8500_version {
32#define AB8500_CUTEARLY 0x00 32#define AB8500_CUTEARLY 0x00
33#define AB8500_CUT1P0 0x10 33#define AB8500_CUT1P0 0x10
34#define AB8500_CUT1P1 0x11 34#define AB8500_CUT1P1 0x11
35#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */
35#define AB8500_CUT2P0 0x20 36#define AB8500_CUT2P0 0x20
36#define AB8500_CUT3P0 0x30 37#define AB8500_CUT3P0 0x30
37#define AB8500_CUT3P3 0x33 38#define AB8500_CUT3P3 0x33
@@ -39,6 +40,7 @@ enum ab8500_version {
39/* 40/*
40 * AB8500 bank addresses 41 * AB8500 bank addresses
41 */ 42 */
43#define AB8500_M_FSM_RANK 0x0
42#define AB8500_SYS_CTRL1_BLOCK 0x1 44#define AB8500_SYS_CTRL1_BLOCK 0x1
43#define AB8500_SYS_CTRL2_BLOCK 0x2 45#define AB8500_SYS_CTRL2_BLOCK 0x2
44#define AB8500_REGU_CTRL1 0x3 46#define AB8500_REGU_CTRL1 0x3
@@ -58,6 +60,7 @@ enum ab8500_version {
58#define AB8500_DEVELOPMENT 0x11 60#define AB8500_DEVELOPMENT 0x11
59#define AB8500_DEBUG 0x12 61#define AB8500_DEBUG 0x12
60#define AB8500_PROD_TEST 0x13 62#define AB8500_PROD_TEST 0x13
63#define AB8500_STE_TEST 0x14
61#define AB8500_OTP_EMUL 0x15 64#define AB8500_OTP_EMUL 0x15
62 65
63/* 66/*
@@ -65,11 +68,11 @@ enum ab8500_version {
65 * Values used to index into array ab8500_irq_regoffset[] defined in 68 * Values used to index into array ab8500_irq_regoffset[] defined in
66 * drivers/mdf/ab8500-core.c 69 * drivers/mdf/ab8500-core.c
67 */ 70 */
68/* Definitions for AB8500 and AB9540 */ 71/* Definitions for AB8500, AB9540 and AB8540 */
69/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ 72/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
70#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */ 73#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
71#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */ 74#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */
72#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */ 75#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */
73#define AB8500_INT_TEMP_WARM 3 76#define AB8500_INT_TEMP_WARM 3
74#define AB8500_INT_PON_KEY2DB_F 4 77#define AB8500_INT_PON_KEY2DB_F 4
75#define AB8500_INT_PON_KEY2DB_R 5 78#define AB8500_INT_PON_KEY2DB_R 5
@@ -77,18 +80,19 @@ enum ab8500_version {
77#define AB8500_INT_PON_KEY1DB_R 7 80#define AB8500_INT_PON_KEY1DB_R 7
78/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ 81/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
79#define AB8500_INT_BATT_OVV 8 82#define AB8500_INT_BATT_OVV 8
80#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */ 83#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */
81#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */ 84#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */
82#define AB8500_INT_VBUS_DET_F 14 85#define AB8500_INT_VBUS_DET_F 14
83#define AB8500_INT_VBUS_DET_R 15 86#define AB8500_INT_VBUS_DET_R 15
84/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ 87/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
85#define AB8500_INT_VBUS_CH_DROP_END 16 88#define AB8500_INT_VBUS_CH_DROP_END 16
86#define AB8500_INT_RTC_60S 17 89#define AB8500_INT_RTC_60S 17
87#define AB8500_INT_RTC_ALARM 18 90#define AB8500_INT_RTC_ALARM 18
91#define AB8540_INT_BIF_INT 19
88#define AB8500_INT_BAT_CTRL_INDB 20 92#define AB8500_INT_BAT_CTRL_INDB 20
89#define AB8500_INT_CH_WD_EXP 21 93#define AB8500_INT_CH_WD_EXP 21
90#define AB8500_INT_VBUS_OVV 22 94#define AB8500_INT_VBUS_OVV 22
91#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */ 95#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */
92/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ 96/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
93#define AB8500_INT_CCN_CONV_ACC 24 97#define AB8500_INT_CCN_CONV_ACC 24
94#define AB8500_INT_INT_AUD 25 98#define AB8500_INT_INT_AUD 25
@@ -99,7 +103,7 @@ enum ab8500_version {
99#define AB8500_INT_BUP_CHG_NOT_OK 30 103#define AB8500_INT_BUP_CHG_NOT_OK 30
100#define AB8500_INT_BUP_CHG_OK 31 104#define AB8500_INT_BUP_CHG_OK 31
101/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ 105/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
102#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */ 106#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */
103#define AB8500_INT_ACC_DETECT_1DB_F 33 107#define AB8500_INT_ACC_DETECT_1DB_F 33
104#define AB8500_INT_ACC_DETECT_1DB_R 34 108#define AB8500_INT_ACC_DETECT_1DB_R 34
105#define AB8500_INT_ACC_DETECT_22DB_F 35 109#define AB8500_INT_ACC_DETECT_22DB_F 35
@@ -108,23 +112,23 @@ enum ab8500_version {
108#define AB8500_INT_ACC_DETECT_21DB_R 38 112#define AB8500_INT_ACC_DETECT_21DB_R 38
109#define AB8500_INT_GP_SW_ADC_CONV_END 39 113#define AB8500_INT_GP_SW_ADC_CONV_END 39
110/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ 114/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
111#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */ 115#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */
112#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */ 116#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */
113#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */ 117#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */
114#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */ 118#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */
115#define AB8500_INT_GPIO10R 44 119#define AB8500_INT_GPIO10R 44 /* not 8540 */
116#define AB8500_INT_GPIO11R 45 120#define AB8500_INT_GPIO11R 45 /* not 8540 */
117#define AB8500_INT_GPIO12R 46 /* not 8505 */ 121#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */
118#define AB8500_INT_GPIO13R 47 122#define AB8500_INT_GPIO13R 47 /* not 8540 */
119/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ 123/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
120#define AB8500_INT_GPIO24R 48 /* not 8505 */ 124#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */
121#define AB8500_INT_GPIO25R 49 /* not 8505 */ 125#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */
122#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */ 126#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */
123#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */ 127#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */
124#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */ 128#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */
125#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */ 129#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */
126#define AB8500_INT_GPIO40R 54 130#define AB8500_INT_GPIO40R 54 /* not 8540 */
127#define AB8500_INT_GPIO41R 55 131#define AB8500_INT_GPIO41R 55 /* not 8540 */
128/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ 132/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
129#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */ 133#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
130#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */ 134#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
@@ -135,14 +139,14 @@ enum ab8500_version {
135#define AB8500_INT_GPIO12F 62 /* not 8505 */ 139#define AB8500_INT_GPIO12F 62 /* not 8505 */
136#define AB8500_INT_GPIO13F 63 140#define AB8500_INT_GPIO13F 63
137/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ 141/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
138#define AB8500_INT_GPIO24F 64 /* not 8505 */ 142#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */
139#define AB8500_INT_GPIO25F 65 /* not 8505 */ 143#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */
140#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */ 144#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */
141#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */ 145#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */
142#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */ 146#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */
143#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */ 147#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */
144#define AB8500_INT_GPIO40F 70 148#define AB8500_INT_GPIO40F 70 /* not 8540 */
145#define AB8500_INT_GPIO41F 71 149#define AB8500_INT_GPIO41F 71 /* not 8540 */
146/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ 150/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
147#define AB8500_INT_ADP_SOURCE_ERROR 72 151#define AB8500_INT_ADP_SOURCE_ERROR 72
148#define AB8500_INT_ADP_SINK_ERROR 73 152#define AB8500_INT_ADP_SINK_ERROR 73
@@ -160,42 +164,44 @@ enum ab8500_version {
160#define AB8500_INT_SRP_DETECT 88 164#define AB8500_INT_SRP_DETECT 88
161#define AB8500_INT_USB_CHARGER_NOT_OKR 89 165#define AB8500_INT_USB_CHARGER_NOT_OKR 89
162#define AB8500_INT_ID_WAKEUP_R 90 166#define AB8500_INT_ID_WAKEUP_R 90
167#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */
163#define AB8500_INT_ID_DET_R1R 92 168#define AB8500_INT_ID_DET_R1R 92
164#define AB8500_INT_ID_DET_R2R 93 169#define AB8500_INT_ID_DET_R2R 93
165#define AB8500_INT_ID_DET_R3R 94 170#define AB8500_INT_ID_DET_R3R 94
166#define AB8500_INT_ID_DET_R4R 95 171#define AB8500_INT_ID_DET_R4R 95
167/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ 172/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
168#define AB8500_INT_ID_WAKEUP_F 96 173#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */
169#define AB8500_INT_ID_DET_R1F 98 174#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */
170#define AB8500_INT_ID_DET_R2F 99 175#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */
171#define AB8500_INT_ID_DET_R3F 100 176#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */
172#define AB8500_INT_ID_DET_R4F 101 177#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */
173#define AB8500_INT_CHAUTORESTARTAFTSEC 102 178#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */
179#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */
174#define AB8500_INT_CHSTOPBYSEC 103 180#define AB8500_INT_CHSTOPBYSEC 103
175/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ 181/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
176#define AB8500_INT_USB_CH_TH_PROT_F 104 182#define AB8500_INT_USB_CH_TH_PROT_F 104
177#define AB8500_INT_USB_CH_TH_PROT_R 105 183#define AB8500_INT_USB_CH_TH_PROT_R 105
178#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */ 184#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
179#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */ 185#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
180#define AB8500_INT_CHCURLIMNOHSCHIRP 109 186#define AB8500_INT_CHCURLIMNOHSCHIRP 109
181#define AB8500_INT_CHCURLIMHSCHIRP 110 187#define AB8500_INT_CHCURLIMHSCHIRP 110
182#define AB8500_INT_XTAL32K_KO 111 188#define AB8500_INT_XTAL32K_KO 111
183 189
184/* Definitions for AB9540 */ 190/* Definitions for AB9540 / AB8505 */
185/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ 191/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
186#define AB9540_INT_GPIO50R 113 192#define AB9540_INT_GPIO50R 113 /* not 8540 */
187#define AB9540_INT_GPIO51R 114 /* not 8505 */ 193#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */
188#define AB9540_INT_GPIO52R 115 194#define AB9540_INT_GPIO52R 115 /* not 8540 */
189#define AB9540_INT_GPIO53R 116 195#define AB9540_INT_GPIO53R 116 /* not 8540 */
190#define AB9540_INT_GPIO54R 117 /* not 8505 */ 196#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */
191#define AB9540_INT_IEXT_CH_RF_BFN_R 118 197#define AB9540_INT_IEXT_CH_RF_BFN_R 118
192#define AB9540_INT_IEXT_CH_RF_BFN_F 119
193/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ 198/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
194#define AB9540_INT_GPIO50F 121 199#define AB9540_INT_GPIO50F 121 /* not 8540 */
195#define AB9540_INT_GPIO51F 122 /* not 8505 */ 200#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */
196#define AB9540_INT_GPIO52F 123 201#define AB9540_INT_GPIO52F 123 /* not 8540 */
197#define AB9540_INT_GPIO53F 124 202#define AB9540_INT_GPIO53F 124 /* not 8540 */
198#define AB9540_INT_GPIO54F 125 /* not 8505 */ 203#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */
204#define AB9540_INT_IEXT_CH_RF_BFN_F 126
199/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ 205/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
200#define AB8505_INT_KEYSTUCK 128 206#define AB8505_INT_KEYSTUCK 128
201#define AB8505_INT_IKR 129 207#define AB8505_INT_IKR 129
@@ -204,6 +210,87 @@ enum ab8500_version {
204#define AB8505_INT_KEYDEGLITCH 132 210#define AB8505_INT_KEYDEGLITCH 132
205#define AB8505_INT_MODPWRSTATUSF 134 211#define AB8505_INT_MODPWRSTATUSF 134
206#define AB8505_INT_MODPWRSTATUSR 135 212#define AB8505_INT_MODPWRSTATUSR 135
213/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */
214#define AB8500_INT_HOOK_DET_NEG_F 138
215#define AB8500_INT_HOOK_DET_NEG_R 139
216#define AB8500_INT_HOOK_DET_POS_F 140
217#define AB8500_INT_HOOK_DET_POS_R 141
218#define AB8500_INT_PLUG_DET_COMP_F 142
219#define AB8500_INT_PLUG_DET_COMP_R 143
220/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */
221#define AB8505_INT_COLL 144
222#define AB8505_INT_RESERR 145
223#define AB8505_INT_FRAERR 146
224#define AB8505_INT_COMERR 147
225#define AB8505_INT_SPDSET 148
226#define AB8505_INT_DSENT 149
227#define AB8505_INT_DREC 150
228#define AB8505_INT_ACC_INT 151
229/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */
230#define AB8505_INT_NOPINT 152
231/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */
232#define AB8540_INT_IDPLUGDETCOMPF 160
233#define AB8540_INT_IDPLUGDETCOMPR 161
234#define AB8540_INT_FMDETCOMPLOF 162
235#define AB8540_INT_FMDETCOMPLOR 163
236#define AB8540_INT_FMDETCOMPHIF 164
237#define AB8540_INT_FMDETCOMPHIR 165
238#define AB8540_INT_ID5VDETCOMPF 166
239#define AB8540_INT_ID5VDETCOMPR 167
240/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */
241#define AB8540_INT_GPIO43F 168
242#define AB8540_INT_GPIO43R 169
243#define AB8540_INT_GPIO44F 170
244#define AB8540_INT_GPIO44R 171
245#define AB8540_INT_KEYPOSDETCOMPF 172
246#define AB8540_INT_KEYPOSDETCOMPR 173
247#define AB8540_INT_KEYNEGDETCOMPF 174
248#define AB8540_INT_KEYNEGDETCOMPR 175
249/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */
250#define AB8540_INT_GPIO1VBATF 176
251#define AB8540_INT_GPIO1VBATR 177
252#define AB8540_INT_GPIO2VBATF 178
253#define AB8540_INT_GPIO2VBATR 179
254#define AB8540_INT_GPIO3VBATF 180
255#define AB8540_INT_GPIO3VBATR 181
256#define AB8540_INT_GPIO4VBATF 182
257#define AB8540_INT_GPIO4VBATR 183
258/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */
259#define AB8540_INT_SYSCLKREQ2F 184
260#define AB8540_INT_SYSCLKREQ2R 185
261#define AB8540_INT_SYSCLKREQ3F 186
262#define AB8540_INT_SYSCLKREQ3R 187
263#define AB8540_INT_SYSCLKREQ4F 188
264#define AB8540_INT_SYSCLKREQ4R 189
265#define AB8540_INT_SYSCLKREQ5F 190
266#define AB8540_INT_SYSCLKREQ5R 191
267/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */
268#define AB8540_INT_PWMOUT1F 192
269#define AB8540_INT_PWMOUT1R 193
270#define AB8540_INT_PWMCTRL0F 194
271#define AB8540_INT_PWMCTRL0R 195
272#define AB8540_INT_PWMCTRL1F 196
273#define AB8540_INT_PWMCTRL1R 197
274#define AB8540_INT_SYSCLKREQ6F 198
275#define AB8540_INT_SYSCLKREQ6R 199
276/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */
277#define AB8540_INT_PWMEXTVIBRA1F 200
278#define AB8540_INT_PWMEXTVIBRA1R 201
279#define AB8540_INT_PWMEXTVIBRA2F 202
280#define AB8540_INT_PWMEXTVIBRA2R 203
281#define AB8540_INT_PWMOUT2F 204
282#define AB8540_INT_PWMOUT2R 205
283#define AB8540_INT_PWMOUT3F 206
284#define AB8540_INT_PWMOUT3R 207
285/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */
286#define AB8540_INT_ADDATA2F 208
287#define AB8540_INT_ADDATA2R 209
288#define AB8540_INT_DADATA2F 210
289#define AB8540_INT_DADATA2R 211
290#define AB8540_INT_FSYNC2F 212
291#define AB8540_INT_FSYNC2R 213
292#define AB8540_INT_BITCLK2F 214
293#define AB8540_INT_BITCLK2R 215
207 294
208/* 295/*
209 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the 296 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
@@ -213,13 +300,24 @@ enum ab8500_version {
213 * which is larger. 300 * which is larger.
214 */ 301 */
215#define AB8500_NR_IRQS 112 302#define AB8500_NR_IRQS 112
216#define AB8505_NR_IRQS 136 303#define AB8505_NR_IRQS 153
217#define AB9540_NR_IRQS 136 304#define AB9540_NR_IRQS 153
305#define AB8540_NR_IRQS 216
218/* This is set to the roof of any AB8500 chip variant IRQ counts */ 306/* This is set to the roof of any AB8500 chip variant IRQ counts */
219#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS 307#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS
220 308
221#define AB8500_NUM_IRQ_REGS 14 309#define AB8500_NUM_IRQ_REGS 14
222#define AB9540_NUM_IRQ_REGS 17 310#define AB9540_NUM_IRQ_REGS 20
311#define AB8540_NUM_IRQ_REGS 27
312
313/* Turn On Status Event */
314#define AB8500_POR_ON_VBAT 0x01
315#define AB8500_POW_KEY_1_ON 0x02
316#define AB8500_POW_KEY_2_ON 0x04
317#define AB8500_RTC_ALARM 0x08
318#define AB8500_MAIN_CH_DET 0x10
319#define AB8500_VBUS_DET 0x20
320#define AB8500_USB_ID_DET 0x40
223 321
224/** 322/**
225 * struct ab8500 - ab8500 internal structure 323 * struct ab8500 - ab8500 internal structure
@@ -287,7 +385,7 @@ struct ab8500_platform_data {
287 struct ab8500_regulator_reg_init *regulator_reg_init; 385 struct ab8500_regulator_reg_init *regulator_reg_init;
288 int num_regulator; 386 int num_regulator;
289 struct regulator_init_data *regulator; 387 struct regulator_init_data *regulator;
290 struct ab8500_gpio_platform_data *gpio; 388 struct abx500_gpio_platform_data *gpio;
291 struct ab8500_codec_platform_data *codec; 389 struct ab8500_codec_platform_data *codec;
292}; 390};
293 391
@@ -335,10 +433,79 @@ static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
335 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0)); 433 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
336} 434}
337 435
436static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
437{
438 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
439}
440
338/* exclude also ab8505, ab9540... */ 441/* exclude also ab8505, ab9540... */
339static inline int is_ab8500_2p0(struct ab8500 *ab) 442static inline int is_ab8500_2p0(struct ab8500 *ab)
340{ 443{
341 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); 444 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
342} 445}
343 446
447static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
448{
449 return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
450}
451
452static inline int is_ab8505_2p0(struct ab8500 *ab)
453{
454 return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
455}
456
457static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
458{
459 return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
460}
461
462static inline int is_ab9540_2p0(struct ab8500 *ab)
463{
464 return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
465}
466
467/*
468 * Be careful, the marketing name for this chip is 2.1
469 * but the value read from the chip is 3.0 (0x30)
470 */
471static inline int is_ab9540_3p0(struct ab8500 *ab)
472{
473 return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
474}
475
476static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
477{
478 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
479}
480
481static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
482{
483 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
484}
485
486static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
487{
488 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
489}
490
491static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
492{
493 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
494}
495
496static inline int is_ab8540_2p0(struct ab8500 *ab)
497{
498 return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
499}
500
501static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
502{
503 return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
504}
505
506static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
507{
508 return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
509}
510
344#endif /* MFD_AB8500_H */ 511#endif /* MFD_AB8500_H */
diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h
new file mode 100644
index 000000000000..6e5f8a985ea7
--- /dev/null
+++ b/include/linux/pinctrl/devinfo.h
@@ -0,0 +1,45 @@
1/*
2 * Per-device information from the pin control system.
3 * This is the stuff that get included into the device
4 * core.
5 *
6 * Copyright (C) 2012 ST-Ericsson SA
7 * Written on behalf of Linaro for ST-Ericsson
8 * This interface is used in the core to keep track of pins.
9 *
10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 *
12 * License terms: GNU General Public License (GPL) version 2
13 */
14
15#ifndef PINCTRL_DEVINFO_H
16#define PINCTRL_DEVINFO_H
17
18#ifdef CONFIG_PINCTRL
19
20/* The device core acts as a consumer toward pinctrl */
21#include <linux/pinctrl/consumer.h>
22
23/**
24 * struct dev_pin_info - pin state container for devices
25 * @p: pinctrl handle for the containing device
26 * @default_state: the default state for the handle, if found
27 */
28struct dev_pin_info {
29 struct pinctrl *p;
30 struct pinctrl_state *default_state;
31};
32
33extern int pinctrl_bind_pins(struct device *dev);
34
35#else
36
37/* Stubs if we're not using pinctrl */
38
39static inline int pinctrl_bind_pins(struct device *dev)
40{
41 return 0;
42}
43
44#endif /* CONFIG_PINCTRL */
45#endif /* PINCTRL_DEVINFO_H */
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index 47a1bdd88878..72474e18f1e0 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -46,7 +46,11 @@
46 * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source 46 * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
47 * (open emitter). Sending this config will enabale open drain mode, the 47 * (open emitter). Sending this config will enabale open drain mode, the
48 * argument is ignored. 48 * argument is ignored.
49 * @PIN_CONFIG_INPUT_SCHMITT_DISABLE: disable schmitt-trigger mode on the pin. 49 * @PIN_CONFIG_DRIVE_STRENGTH: the pin will output the current passed as
50 * argument. The argument is in mA.
51 * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
52 * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
53 * schmitt-trigger mode is disabled.
50 * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in 54 * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
51 * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis, 55 * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
52 * the threshold value is given on a custom format as argument when 56 * the threshold value is given on a custom format as argument when
@@ -58,10 +62,15 @@
58 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power 62 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
59 * supplies, the argument to this parameter (on a custom format) tells 63 * supplies, the argument to this parameter (on a custom format) tells
60 * the driver which alternative power source to use. 64 * the driver which alternative power source to use.
65 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
66 * this parameter (on a custom format) tells the driver which alternative
67 * slew rate to use.
61 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power 68 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
62 * operation, if several modes of operation are supported these can be 69 * operation, if several modes of operation are supported these can be
63 * passed in the argument on a custom form, else just use argument 1 70 * passed in the argument on a custom form, else just use argument 1
64 * to indicate low power mode, argument 0 turns low power mode off. 71 * to indicate low power mode, argument 0 turns low power mode off.
72 * @PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
73 * 1 to indicate high level, argument 0 to indicate low level.
65 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if 74 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
66 * you need to pass in custom configurations to the pin controller, use 75 * you need to pass in custom configurations to the pin controller, use
67 * PIN_CONFIG_END+1 as the base offset. 76 * PIN_CONFIG_END+1 as the base offset.
@@ -74,11 +83,14 @@ enum pin_config_param {
74 PIN_CONFIG_DRIVE_PUSH_PULL, 83 PIN_CONFIG_DRIVE_PUSH_PULL,
75 PIN_CONFIG_DRIVE_OPEN_DRAIN, 84 PIN_CONFIG_DRIVE_OPEN_DRAIN,
76 PIN_CONFIG_DRIVE_OPEN_SOURCE, 85 PIN_CONFIG_DRIVE_OPEN_SOURCE,
77 PIN_CONFIG_INPUT_SCHMITT_DISABLE, 86 PIN_CONFIG_DRIVE_STRENGTH,
87 PIN_CONFIG_INPUT_SCHMITT_ENABLE,
78 PIN_CONFIG_INPUT_SCHMITT, 88 PIN_CONFIG_INPUT_SCHMITT,
79 PIN_CONFIG_INPUT_DEBOUNCE, 89 PIN_CONFIG_INPUT_DEBOUNCE,
80 PIN_CONFIG_POWER_SOURCE, 90 PIN_CONFIG_POWER_SOURCE,
91 PIN_CONFIG_SLEW_RATE,
81 PIN_CONFIG_LOW_POWER_MODE, 92 PIN_CONFIG_LOW_POWER_MODE,
93 PIN_CONFIG_OUTPUT,
82 PIN_CONFIG_END = 0x7FFF, 94 PIN_CONFIG_END = 0x7FFF,
83}; 95};
84 96
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 04d6700d99af..778804df293f 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -154,6 +154,7 @@ struct pinctrl_dev *of_pinctrl_get(struct device_node *np)
154#endif /* CONFIG_OF */ 154#endif /* CONFIG_OF */
155 155
156extern const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev); 156extern const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev);
157extern const char *pinctrl_dev_get_devname(struct pinctrl_dev *pctldev);
157extern void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev); 158extern void *pinctrl_dev_get_drvdata(struct pinctrl_dev *pctldev);
158#else 159#else
159 160
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 11:35:23 -0500