3 files changed, 47 insertions, 15 deletions

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c09577ddc3c5..0f34ec58bac3 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -690,13 +690,13 @@ endmenu
 
 
 menu "Blackfin Kernel Optimizations"
-        depends on !SMP
 
 comment "Memory Optimizations"
 
 config I_ENTRY_L1
         bool "Locate interrupt entry code in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
           into L1 instruction memory. (less latency)
@@ -704,6 +704,7 @@ config I_ENTRY_L1
 config EXCPT_IRQ_SYSC_L1
         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the entire ASM lowlevel exception and interrupt entry code
           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
@@ -712,6 +713,7 @@ config EXCPT_IRQ_SYSC_L1
 config DO_IRQ_L1
         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the frequently called do_irq dispatcher function is linked
           into L1 instruction memory. (less latency)
@@ -719,6 +721,7 @@ config DO_IRQ_L1
 config CORE_TIMER_IRQ_L1
         bool "Locate frequently called timer_interrupt() function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the frequently called timer_interrupt() function is linked
           into L1 instruction memory. (less latency)
@@ -726,6 +729,7 @@ config CORE_TIMER_IRQ_L1
 config IDLE_L1
         bool "Locate frequently idle function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the frequently called idle function is linked
           into L1 instruction memory. (less latency)
@@ -733,6 +737,7 @@ config IDLE_L1
 config SCHEDULE_L1
         bool "Locate kernel schedule function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the frequently called kernel schedule is linked
           into L1 instruction memory. (less latency)
@@ -740,6 +745,7 @@ config SCHEDULE_L1
 config ARITHMETIC_OPS_L1
         bool "Locate kernel owned arithmetic functions in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, arithmetic functions are linked
           into L1 instruction memory. (less latency)
@@ -747,6 +753,7 @@ config ARITHMETIC_OPS_L1
 config ACCESS_OK_L1
         bool "Locate access_ok function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the access_ok function is linked
           into L1 instruction memory. (less latency)
@@ -754,6 +761,7 @@ config ACCESS_OK_L1
 config MEMSET_L1
         bool "Locate memset function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the memset function is linked
           into L1 instruction memory. (less latency)
@@ -761,6 +769,7 @@ config MEMSET_L1
 config MEMCPY_L1
         bool "Locate memcpy function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the memcpy function is linked
           into L1 instruction memory. (less latency)
@@ -768,6 +777,7 @@ config MEMCPY_L1
 config STRCMP_L1
         bool "locate strcmp function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the strcmp function is linked
           into L1 instruction memory (less latency).
@@ -775,6 +785,7 @@ config STRCMP_L1
 config STRNCMP_L1
         bool "locate strncmp function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the strncmp function is linked
           into L1 instruction memory (less latency).
@@ -782,6 +793,7 @@ config STRNCMP_L1
 config STRCPY_L1
         bool "locate strcpy function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the strcpy function is linked
           into L1 instruction memory (less latency).
@@ -789,6 +801,7 @@ config STRCPY_L1
 config STRNCPY_L1
         bool "locate strncpy function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, the strncpy function is linked
           into L1 instruction memory (less latency).
@@ -796,6 +809,7 @@ config STRNCPY_L1
 config SYS_BFIN_SPINLOCK_L1
         bool "Locate sys_bfin_spinlock function in L1 Memory"
         default y
+        depends on !SMP
         help
           If enabled, sys_bfin_spinlock function is linked
           into L1 instruction memory. (less latency)
@@ -803,6 +817,7 @@ config SYS_BFIN_SPINLOCK_L1
 config IP_CHECKSUM_L1
         bool "Locate IP Checksum function in L1 Memory"
         default n
+        depends on !SMP
         help
           If enabled, the IP Checksum function is linked
           into L1 instruction memory. (less latency)
@@ -811,7 +826,7 @@ config CACHELINE_ALIGNED_L1
         bool "Locate cacheline_aligned data to L1 Data Memory"
         default y if !BF54x
         default n if BF54x
-        depends on !BF531
+        depends on !SMP && !BF531
         help
           If enabled, cacheline_aligned data is linked
           into L1 data memory. (less latency)
@@ -819,7 +834,7 @@ config CACHELINE_ALIGNED_L1
 config SYSCALL_TAB_L1
         bool "Locate Syscall Table L1 Data Memory"
         default n
-        depends on !BF531
+        depends on !SMP && !BF531
         help
           If enabled, the Syscall LUT is linked
           into L1 data memory. (less latency)
@@ -827,16 +842,17 @@ config SYSCALL_TAB_L1
 config CPLB_SWITCH_TAB_L1
         bool "Locate CPLB Switch Tables L1 Data Memory"
         default n
-        depends on !BF531
+        depends on !SMP && !BF531
         help
           If enabled, the CPLB Switch Tables are linked
           into L1 data memory. (less latency)
 
-config CACHE_FLUSH_L1
-        bool "Locate cache flush funcs in L1 Inst Memory"
+config ICACHE_FLUSH_L1
+        bool "Locate icache flush funcs in L1 Inst Memory"
         default y
+        depends on !SMP
         help
-          If enabled, the Blackfin cache flushing functions are linked
+          If enabled, the Blackfin icache flushing functions are linked
           into L1 instruction memory.
 
           Note that this might be required to address anomalies, but
@@ -844,9 +860,18 @@ config CACHE_FLUSH_L1
           If you are using a processor affected by an anomaly, the build
           system will double check for you and prevent it.
 
+config DCACHE_FLUSH_L1
+        bool "Locate dcache flush funcs in L1 Inst Memory"
+        default y
+        depends on !SMP
+        help
+          If enabled, the Blackfin dcache flushing functions are linked
+          into L1 instruction memory.
+
 config APP_STACK_L1
         bool "Support locating application stack in L1 Scratch Memory"
         default y
+        depends on !SMP
         help
           If enabled the application stack can be located in L1
           scratch memory (less latency).
@@ -856,7 +881,7 @@ config APP_STACK_L1
 config EXCEPTION_L1_SCRATCH
         bool "Locate exception stack in L1 Scratch Memory"
         default n
-        depends on !APP_STACK_L1
+        depends on !SMP && !APP_STACK_L1
         help
           Whenever an exception occurs, use the L1 Scratch memory for
           stack storage.  You cannot place the stacks of FLAT binaries
@@ -868,6 +893,7 @@ comment "Speed Optimizations"
 config BFIN_INS_LOWOVERHEAD
         bool "ins[bwl] low overhead, higher interrupt latency"
         default y
+        depends on !SMP
         help
           Reads on the Blackfin are speculative. In Blackfin terms, this means
           they can be interrupted at any time (even after they have been issued
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index bceb98126c21..d8643fdd0fcf 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -61,6 +61,6 @@
 # error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
 #endif
 
-#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1)
+#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
 # error You need IFLUSH in L1 inst while Anomaly 05000491 applies
 #endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index ab4a925a443e..85aadeb76658 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -11,12 +11,6 @@
 #include <asm/cache.h>
 #include <asm/page.h>
 
-#ifdef CONFIG_CACHE_FLUSH_L1
-.section .l1.text
-#else
-.text
-#endif
-
 /* 05000443 - IFLUSH cannot be last instruction in hardware loop */
 #if ANOMALY_05000443
 # define BROK_FLUSH_INST "IFLUSH"
@@ -68,11 +62,23 @@
         RTS;
 .endm
 
+#ifdef CONFIG_ICACHE_FLUSH_L1
+.section .l1.text
+#else
+.text
+#endif
+
 /* Invalidate all instruction cache lines assocoiated with this memory area */
 ENTRY(_blackfin_icache_flush_range)
         do_flush IFLUSH
 ENDPROC(_blackfin_icache_flush_range)
 
+#ifdef CONFIG_DCACHE_FLUSH_L1
+.section .l1.text
+#else
+.text
+#endif
+
 /* Throw away all D-cached data in specified region without any obligation to
  * write them back.  Since the Blackfin ISA does not have an "invalidate"
  * instruction, we use flush/invalidate.  Perhaps as a speed optimization we