diff options
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_boot.c | 63 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_cmd.c | 19 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_event.c | 8 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_main.c | 12 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_ps.c | 4 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_rx.c | 10 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_spi.c | 85 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_spi.h | 36 | ||||
-rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_tx.c | 10 |
9 files changed, 107 insertions, 140 deletions
diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.c b/drivers/net/wireless/wl12xx/wl1271_boot.c index b58657750716..a27601dc9c0d 100644 --- a/drivers/net/wireless/wl12xx/wl1271_boot.c +++ b/drivers/net/wireless/wl12xx/wl1271_boot.c | |||
@@ -93,19 +93,19 @@ static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag) | |||
93 | u32 cpu_ctrl; | 93 | u32 cpu_ctrl; |
94 | 94 | ||
95 | /* 10.5.0 run the firmware (I) */ | 95 | /* 10.5.0 run the firmware (I) */ |
96 | cpu_ctrl = wl1271_reg_read32(wl, ACX_REG_ECPU_CONTROL); | 96 | cpu_ctrl = wl1271_spi_read32(wl, ACX_REG_ECPU_CONTROL); |
97 | 97 | ||
98 | /* 10.5.1 run the firmware (II) */ | 98 | /* 10.5.1 run the firmware (II) */ |
99 | cpu_ctrl |= flag; | 99 | cpu_ctrl |= flag; |
100 | wl1271_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); | 100 | wl1271_spi_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); |
101 | } | 101 | } |
102 | 102 | ||
103 | static void wl1271_boot_fw_version(struct wl1271 *wl) | 103 | static void wl1271_boot_fw_version(struct wl1271 *wl) |
104 | { | 104 | { |
105 | struct wl1271_static_data static_data; | 105 | struct wl1271_static_data static_data; |
106 | 106 | ||
107 | wl1271_spi_mem_read(wl, wl->cmd_box_addr, | 107 | wl1271_spi_read(wl, wl->cmd_box_addr, |
108 | &static_data, sizeof(static_data)); | 108 | &static_data, sizeof(static_data), false); |
109 | 109 | ||
110 | strncpy(wl->chip.fw_ver, static_data.fw_version, | 110 | strncpy(wl->chip.fw_ver, static_data.fw_version, |
111 | sizeof(wl->chip.fw_ver)); | 111 | sizeof(wl->chip.fw_ver)); |
@@ -164,7 +164,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, | |||
164 | memcpy(chunk, p, CHUNK_SIZE); | 164 | memcpy(chunk, p, CHUNK_SIZE); |
165 | wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", | 165 | wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", |
166 | p, addr); | 166 | p, addr); |
167 | wl1271_spi_mem_write(wl, addr, chunk, CHUNK_SIZE); | 167 | wl1271_spi_write(wl, addr, chunk, CHUNK_SIZE, false); |
168 | 168 | ||
169 | chunk_num++; | 169 | chunk_num++; |
170 | } | 170 | } |
@@ -175,7 +175,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, | |||
175 | memcpy(chunk, p, fw_data_len % CHUNK_SIZE); | 175 | memcpy(chunk, p, fw_data_len % CHUNK_SIZE); |
176 | wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", | 176 | wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", |
177 | fw_data_len % CHUNK_SIZE, p, addr); | 177 | fw_data_len % CHUNK_SIZE, p, addr); |
178 | wl1271_spi_mem_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE); | 178 | wl1271_spi_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false); |
179 | 179 | ||
180 | kfree(chunk); | 180 | kfree(chunk); |
181 | return 0; | 181 | return 0; |
@@ -262,7 +262,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) | |||
262 | wl1271_debug(DEBUG_BOOT, | 262 | wl1271_debug(DEBUG_BOOT, |
263 | "nvs burst write 0x%x: 0x%x", | 263 | "nvs burst write 0x%x: 0x%x", |
264 | dest_addr, val); | 264 | dest_addr, val); |
265 | wl1271_reg_write32(wl, dest_addr, val); | 265 | wl1271_spi_write32(wl, dest_addr, val); |
266 | 266 | ||
267 | nvs_ptr += 4; | 267 | nvs_ptr += 4; |
268 | dest_addr += 4; | 268 | dest_addr += 4; |
@@ -289,7 +289,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) | |||
289 | /* FIXME: In wl1271, we upload everything at once. | 289 | /* FIXME: In wl1271, we upload everything at once. |
290 | No endianness handling needed here?! The ref driver doesn't do | 290 | No endianness handling needed here?! The ref driver doesn't do |
291 | anything about it at this point */ | 291 | anything about it at this point */ |
292 | wl1271_spi_mem_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len); | 292 | wl1271_spi_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false); |
293 | 293 | ||
294 | kfree(nvs_aligned); | 294 | kfree(nvs_aligned); |
295 | return 0; | 295 | return 0; |
@@ -298,9 +298,9 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) | |||
298 | static void wl1271_boot_enable_interrupts(struct wl1271 *wl) | 298 | static void wl1271_boot_enable_interrupts(struct wl1271 *wl) |
299 | { | 299 | { |
300 | enable_irq(wl->irq); | 300 | enable_irq(wl->irq); |
301 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, | 301 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, |
302 | WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); | 302 | WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); |
303 | wl1271_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL); | 303 | wl1271_spi_write32(wl, HI_CFG, HI_CFG_DEF_VAL); |
304 | } | 304 | } |
305 | 305 | ||
306 | static int wl1271_boot_soft_reset(struct wl1271 *wl) | 306 | static int wl1271_boot_soft_reset(struct wl1271 *wl) |
@@ -309,12 +309,13 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl) | |||
309 | u32 boot_data; | 309 | u32 boot_data; |
310 | 310 | ||
311 | /* perform soft reset */ | 311 | /* perform soft reset */ |
312 | wl1271_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT); | 312 | wl1271_spi_write32(wl, ACX_REG_SLV_SOFT_RESET, |
313 | ACX_SLV_SOFT_RESET_BIT); | ||
313 | 314 | ||
314 | /* SOFT_RESET is self clearing */ | 315 | /* SOFT_RESET is self clearing */ |
315 | timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); | 316 | timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); |
316 | while (1) { | 317 | while (1) { |
317 | boot_data = wl1271_reg_read32(wl, ACX_REG_SLV_SOFT_RESET); | 318 | boot_data = wl1271_spi_read32(wl, ACX_REG_SLV_SOFT_RESET); |
318 | wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); | 319 | wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); |
319 | if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) | 320 | if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) |
320 | break; | 321 | break; |
@@ -330,10 +331,10 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl) | |||
330 | } | 331 | } |
331 | 332 | ||
332 | /* disable Rx/Tx */ | 333 | /* disable Rx/Tx */ |
333 | wl1271_reg_write32(wl, ENABLE, 0x0); | 334 | wl1271_spi_write32(wl, ENABLE, 0x0); |
334 | 335 | ||
335 | /* disable auto calibration on start*/ | 336 | /* disable auto calibration on start*/ |
336 | wl1271_reg_write32(wl, SPARE_A2, 0xffff); | 337 | wl1271_spi_write32(wl, SPARE_A2, 0xffff); |
337 | 338 | ||
338 | return 0; | 339 | return 0; |
339 | } | 340 | } |
@@ -345,7 +346,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) | |||
345 | 346 | ||
346 | wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); | 347 | wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); |
347 | 348 | ||
348 | chip_id = wl1271_reg_read32(wl, CHIP_ID_B); | 349 | chip_id = wl1271_spi_read32(wl, CHIP_ID_B); |
349 | 350 | ||
350 | wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); | 351 | wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); |
351 | 352 | ||
@@ -358,7 +359,8 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) | |||
358 | loop = 0; | 359 | loop = 0; |
359 | while (loop++ < INIT_LOOP) { | 360 | while (loop++ < INIT_LOOP) { |
360 | udelay(INIT_LOOP_DELAY); | 361 | udelay(INIT_LOOP_DELAY); |
361 | interrupt = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); | 362 | interrupt = wl1271_spi_read32(wl, |
363 | ACX_REG_INTERRUPT_NO_CLEAR); | ||
362 | 364 | ||
363 | if (interrupt == 0xffffffff) { | 365 | if (interrupt == 0xffffffff) { |
364 | wl1271_error("error reading hardware complete " | 366 | wl1271_error("error reading hardware complete " |
@@ -367,7 +369,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) | |||
367 | } | 369 | } |
368 | /* check that ACX_INTR_INIT_COMPLETE is enabled */ | 370 | /* check that ACX_INTR_INIT_COMPLETE is enabled */ |
369 | else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) { | 371 | else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) { |
370 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK, | 372 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK, |
371 | WL1271_ACX_INTR_INIT_COMPLETE); | 373 | WL1271_ACX_INTR_INIT_COMPLETE); |
372 | break; | 374 | break; |
373 | } | 375 | } |
@@ -380,10 +382,10 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) | |||
380 | } | 382 | } |
381 | 383 | ||
382 | /* get hardware config command mail box */ | 384 | /* get hardware config command mail box */ |
383 | wl->cmd_box_addr = wl1271_reg_read32(wl, REG_COMMAND_MAILBOX_PTR); | 385 | wl->cmd_box_addr = wl1271_spi_read32(wl, REG_COMMAND_MAILBOX_PTR); |
384 | 386 | ||
385 | /* get hardware config event mail box */ | 387 | /* get hardware config event mail box */ |
386 | wl->event_box_addr = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR); | 388 | wl->event_box_addr = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR); |
387 | 389 | ||
388 | /* set the working partition to its "running" mode offset */ | 390 | /* set the working partition to its "running" mode offset */ |
389 | wl1271_set_partition(wl, &part_table[PART_WORK]); | 391 | wl1271_set_partition(wl, &part_table[PART_WORK]); |
@@ -458,9 +460,9 @@ int wl1271_boot(struct wl1271 *wl) | |||
458 | wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); | 460 | wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); |
459 | } | 461 | } |
460 | 462 | ||
461 | wl1271_reg_write32(wl, PLL_PARAMETERS, clk); | 463 | wl1271_spi_write32(wl, PLL_PARAMETERS, clk); |
462 | 464 | ||
463 | pause = wl1271_reg_read32(wl, PLL_PARAMETERS); | 465 | pause = wl1271_spi_read32(wl, PLL_PARAMETERS); |
464 | 466 | ||
465 | wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); | 467 | wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); |
466 | 468 | ||
@@ -469,10 +471,10 @@ int wl1271_boot(struct wl1271 *wl) | |||
469 | * 0x3ff (magic number ). How does | 471 | * 0x3ff (magic number ). How does |
470 | * this work?! */ | 472 | * this work?! */ |
471 | pause |= WU_COUNTER_PAUSE_VAL; | 473 | pause |= WU_COUNTER_PAUSE_VAL; |
472 | wl1271_reg_write32(wl, WU_COUNTER_PAUSE, pause); | 474 | wl1271_spi_write32(wl, WU_COUNTER_PAUSE, pause); |
473 | 475 | ||
474 | /* Continue the ELP wake up sequence */ | 476 | /* Continue the ELP wake up sequence */ |
475 | wl1271_reg_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); | 477 | wl1271_spi_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); |
476 | udelay(500); | 478 | udelay(500); |
477 | 479 | ||
478 | wl1271_set_partition(wl, &part_table[PART_DRPW]); | 480 | wl1271_set_partition(wl, &part_table[PART_DRPW]); |
@@ -482,18 +484,18 @@ int wl1271_boot(struct wl1271 *wl) | |||
482 | before taking DRPw out of reset */ | 484 | before taking DRPw out of reset */ |
483 | 485 | ||
484 | wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START); | 486 | wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START); |
485 | clk = wl1271_reg_read32(wl, DRPW_SCRATCH_START); | 487 | clk = wl1271_spi_read32(wl, DRPW_SCRATCH_START); |
486 | 488 | ||
487 | wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); | 489 | wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); |
488 | 490 | ||
489 | /* 2 */ | 491 | /* 2 */ |
490 | clk |= (REF_CLOCK << 1) << 4; | 492 | clk |= (REF_CLOCK << 1) << 4; |
491 | wl1271_reg_write32(wl, DRPW_SCRATCH_START, clk); | 493 | wl1271_spi_write32(wl, DRPW_SCRATCH_START, clk); |
492 | 494 | ||
493 | wl1271_set_partition(wl, &part_table[PART_WORK]); | 495 | wl1271_set_partition(wl, &part_table[PART_WORK]); |
494 | 496 | ||
495 | /* Disable interrupts */ | 497 | /* Disable interrupts */ |
496 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); | 498 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); |
497 | 499 | ||
498 | ret = wl1271_boot_soft_reset(wl); | 500 | ret = wl1271_boot_soft_reset(wl); |
499 | if (ret < 0) | 501 | if (ret < 0) |
@@ -508,21 +510,22 @@ int wl1271_boot(struct wl1271 *wl) | |||
508 | * ACX_EEPROMLESS_IND_REG */ | 510 | * ACX_EEPROMLESS_IND_REG */ |
509 | wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); | 511 | wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); |
510 | 512 | ||
511 | wl1271_reg_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG); | 513 | wl1271_spi_write32(wl, ACX_EEPROMLESS_IND_REG, |
514 | ACX_EEPROMLESS_IND_REG); | ||
512 | 515 | ||
513 | tmp = wl1271_reg_read32(wl, CHIP_ID_B); | 516 | tmp = wl1271_spi_read32(wl, CHIP_ID_B); |
514 | 517 | ||
515 | wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); | 518 | wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); |
516 | 519 | ||
517 | /* 6. read the EEPROM parameters */ | 520 | /* 6. read the EEPROM parameters */ |
518 | tmp = wl1271_reg_read32(wl, SCR_PAD2); | 521 | tmp = wl1271_spi_read32(wl, SCR_PAD2); |
519 | 522 | ||
520 | ret = wl1271_boot_write_irq_polarity(wl); | 523 | ret = wl1271_boot_write_irq_polarity(wl); |
521 | if (ret < 0) | 524 | if (ret < 0) |
522 | goto out; | 525 | goto out; |
523 | 526 | ||
524 | /* FIXME: Need to check whether this is really what we want */ | 527 | /* FIXME: Need to check whether this is really what we want */ |
525 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, | 528 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, |
526 | WL1271_ACX_ALL_EVENTS_VECTOR); | 529 | WL1271_ACX_ALL_EVENTS_VECTOR); |
527 | 530 | ||
528 | /* WL1271: The reference driver skips steps 7 to 10 (jumps directly | 531 | /* WL1271: The reference driver skips steps 7 to 10 (jumps directly |
diff --git a/drivers/net/wireless/wl12xx/wl1271_cmd.c b/drivers/net/wireless/wl12xx/wl1271_cmd.c index ef92834e0e8f..f727744dcff7 100644 --- a/drivers/net/wireless/wl12xx/wl1271_cmd.c +++ b/drivers/net/wireless/wl12xx/wl1271_cmd.c | |||
@@ -55,13 +55,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len) | |||
55 | 55 | ||
56 | WARN_ON(len % 4 != 0); | 56 | WARN_ON(len % 4 != 0); |
57 | 57 | ||
58 | wl1271_spi_mem_write(wl, wl->cmd_box_addr, buf, len); | 58 | wl1271_spi_write(wl, wl->cmd_box_addr, buf, len, false); |
59 | 59 | ||
60 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD); | 60 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD); |
61 | 61 | ||
62 | timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT); | 62 | timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT); |
63 | 63 | ||
64 | intr = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); | 64 | intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); |
65 | while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) { | 65 | while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) { |
66 | if (time_after(jiffies, timeout)) { | 66 | if (time_after(jiffies, timeout)) { |
67 | wl1271_error("command complete timeout"); | 67 | wl1271_error("command complete timeout"); |
@@ -71,10 +71,10 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len) | |||
71 | 71 | ||
72 | msleep(1); | 72 | msleep(1); |
73 | 73 | ||
74 | intr = wl1271_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); | 74 | intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); |
75 | } | 75 | } |
76 | 76 | ||
77 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_ACK, | 77 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK, |
78 | WL1271_ACX_INTR_CMD_COMPLETE); | 78 | WL1271_ACX_INTR_CMD_COMPLETE); |
79 | 79 | ||
80 | out: | 80 | out: |
@@ -302,7 +302,7 @@ int wl1271_cmd_test(struct wl1271 *wl, void *buf, size_t buf_len, u8 answer) | |||
302 | * The answer would be a wl1271_command, where the | 302 | * The answer would be a wl1271_command, where the |
303 | * parameter array contains the actual answer. | 303 | * parameter array contains the actual answer. |
304 | */ | 304 | */ |
305 | wl1271_spi_mem_read(wl, wl->cmd_box_addr, buf, buf_len); | 305 | wl1271_spi_read(wl, wl->cmd_box_addr, buf, buf_len, false); |
306 | 306 | ||
307 | cmd_answer = buf; | 307 | cmd_answer = buf; |
308 | 308 | ||
@@ -341,7 +341,7 @@ int wl1271_cmd_interrogate(struct wl1271 *wl, u16 id, void *buf, size_t len) | |||
341 | } | 341 | } |
342 | 342 | ||
343 | /* the interrogate command got in, we can read the answer */ | 343 | /* the interrogate command got in, we can read the answer */ |
344 | wl1271_spi_mem_read(wl, wl->cmd_box_addr, buf, len); | 344 | wl1271_spi_read(wl, wl->cmd_box_addr, buf, len, false); |
345 | 345 | ||
346 | acx = buf; | 346 | acx = buf; |
347 | if (acx->cmd.status != CMD_STATUS_SUCCESS) | 347 | if (acx->cmd.status != CMD_STATUS_SUCCESS) |
@@ -496,7 +496,7 @@ int wl1271_cmd_read_memory(struct wl1271 *wl, u32 addr, void *answer, | |||
496 | } | 496 | } |
497 | 497 | ||
498 | /* the read command got in, we can now read the answer */ | 498 | /* the read command got in, we can now read the answer */ |
499 | wl1271_spi_mem_read(wl, wl->cmd_box_addr, cmd, sizeof(*cmd)); | 499 | wl1271_spi_read(wl, wl->cmd_box_addr, cmd, sizeof(*cmd), false); |
500 | 500 | ||
501 | if (cmd->header.status != CMD_STATUS_SUCCESS) | 501 | if (cmd->header.status != CMD_STATUS_SUCCESS) |
502 | wl1271_error("error in read command result: %d", | 502 | wl1271_error("error in read command result: %d", |
@@ -591,7 +591,8 @@ int wl1271_cmd_scan(struct wl1271 *wl, u8 *ssid, size_t len, | |||
591 | goto out; | 591 | goto out; |
592 | } | 592 | } |
593 | 593 | ||
594 | wl1271_spi_mem_read(wl, wl->cmd_box_addr, params, sizeof(*params)); | 594 | wl1271_spi_read(wl, wl->cmd_box_addr, params, sizeof(*params), |
595 | false); | ||
595 | 596 | ||
596 | if (params->header.status != CMD_STATUS_SUCCESS) { | 597 | if (params->header.status != CMD_STATUS_SUCCESS) { |
597 | wl1271_error("Scan command error: %d", | 598 | wl1271_error("Scan command error: %d", |
diff --git a/drivers/net/wireless/wl12xx/wl1271_event.c b/drivers/net/wireless/wl12xx/wl1271_event.c index f32927650af4..4189e97ca805 100644 --- a/drivers/net/wireless/wl12xx/wl1271_event.c +++ b/drivers/net/wireless/wl12xx/wl1271_event.c | |||
@@ -98,7 +98,7 @@ int wl1271_event_unmask(struct wl1271 *wl) | |||
98 | 98 | ||
99 | void wl1271_event_mbox_config(struct wl1271 *wl) | 99 | void wl1271_event_mbox_config(struct wl1271 *wl) |
100 | { | 100 | { |
101 | wl->mbox_ptr[0] = wl1271_reg_read32(wl, REG_EVENT_MAILBOX_PTR); | 101 | wl->mbox_ptr[0] = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR); |
102 | wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox); | 102 | wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox); |
103 | 103 | ||
104 | wl1271_debug(DEBUG_EVENT, "MBOX ptrs: 0x%x 0x%x", | 104 | wl1271_debug(DEBUG_EVENT, "MBOX ptrs: 0x%x 0x%x", |
@@ -116,8 +116,8 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num) | |||
116 | return -EINVAL; | 116 | return -EINVAL; |
117 | 117 | ||
118 | /* first we read the mbox descriptor */ | 118 | /* first we read the mbox descriptor */ |
119 | wl1271_spi_mem_read(wl, wl->mbox_ptr[mbox_num], &mbox, | 119 | wl1271_spi_read(wl, wl->mbox_ptr[mbox_num], &mbox, |
120 | sizeof(struct event_mailbox)); | 120 | sizeof(struct event_mailbox), false); |
121 | 121 | ||
122 | /* process the descriptor */ | 122 | /* process the descriptor */ |
123 | ret = wl1271_event_process(wl, &mbox); | 123 | ret = wl1271_event_process(wl, &mbox); |
@@ -125,7 +125,7 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num) | |||
125 | return ret; | 125 | return ret; |
126 | 126 | ||
127 | /* then we let the firmware know it can go on...*/ | 127 | /* then we let the firmware know it can go on...*/ |
128 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK); | 128 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK); |
129 | 129 | ||
130 | return 0; | 130 | return 0; |
131 | } | 131 | } |
diff --git a/drivers/net/wireless/wl12xx/wl1271_main.c b/drivers/net/wireless/wl12xx/wl1271_main.c index 8ac9bc1b9445..5ef0bd53af66 100644 --- a/drivers/net/wireless/wl12xx/wl1271_main.c +++ b/drivers/net/wireless/wl12xx/wl1271_main.c | |||
@@ -82,8 +82,8 @@ static void wl1271_fw_status(struct wl1271 *wl, | |||
82 | u32 total = 0; | 82 | u32 total = 0; |
83 | int i; | 83 | int i; |
84 | 84 | ||
85 | wl1271_spi_reg_read(wl, FW_STATUS_ADDR, status, | 85 | wl1271_spi_read(wl, FW_STATUS_ADDR, status, |
86 | sizeof(*status), false); | 86 | sizeof(*status), false); |
87 | 87 | ||
88 | wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, " | 88 | wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, " |
89 | "drv_rx_counter = %d, tx_results_counter = %d)", | 89 | "drv_rx_counter = %d, tx_results_counter = %d)", |
@@ -126,7 +126,7 @@ static void wl1271_irq_work(struct work_struct *work) | |||
126 | if (ret < 0) | 126 | if (ret < 0) |
127 | goto out; | 127 | goto out; |
128 | 128 | ||
129 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); | 129 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); |
130 | 130 | ||
131 | wl1271_fw_status(wl, wl->fw_status); | 131 | wl1271_fw_status(wl, wl->fw_status); |
132 | intr = wl->fw_status->intr; | 132 | intr = wl->fw_status->intr; |
@@ -168,7 +168,7 @@ static void wl1271_irq_work(struct work_struct *work) | |||
168 | } | 168 | } |
169 | 169 | ||
170 | out_sleep: | 170 | out_sleep: |
171 | wl1271_reg_write32(wl, ACX_REG_INTERRUPT_MASK, | 171 | wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, |
172 | WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); | 172 | WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); |
173 | wl1271_ps_elp_sleep(wl); | 173 | wl1271_ps_elp_sleep(wl); |
174 | 174 | ||
@@ -279,7 +279,7 @@ static void wl1271_fw_wakeup(struct wl1271 *wl) | |||
279 | u32 elp_reg; | 279 | u32 elp_reg; |
280 | 280 | ||
281 | elp_reg = ELPCTRL_WAKE_UP; | 281 | elp_reg = ELPCTRL_WAKE_UP; |
282 | wl1271_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, elp_reg); | 282 | wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, elp_reg); |
283 | } | 283 | } |
284 | 284 | ||
285 | static int wl1271_setup(struct wl1271 *wl) | 285 | static int wl1271_setup(struct wl1271 *wl) |
@@ -322,7 +322,7 @@ static int wl1271_chip_wakeup(struct wl1271 *wl) | |||
322 | /* whal_FwCtrl_BootSm() */ | 322 | /* whal_FwCtrl_BootSm() */ |
323 | 323 | ||
324 | /* 0. read chip id from CHIP_ID */ | 324 | /* 0. read chip id from CHIP_ID */ |
325 | wl->chip.id = wl1271_reg_read32(wl, CHIP_ID_B); | 325 | wl->chip.id = wl1271_spi_read32(wl, CHIP_ID_B); |
326 | 326 | ||
327 | /* 1. check if chip id is valid */ | 327 | /* 1. check if chip id is valid */ |
328 | 328 | ||
diff --git a/drivers/net/wireless/wl12xx/wl1271_ps.c b/drivers/net/wireless/wl12xx/wl1271_ps.c index fb821c988661..bb8745d9bd64 100644 --- a/drivers/net/wireless/wl12xx/wl1271_ps.c +++ b/drivers/net/wireless/wl12xx/wl1271_ps.c | |||
@@ -43,7 +43,7 @@ void wl1271_elp_work(struct work_struct *work) | |||
43 | goto out; | 43 | goto out; |
44 | 44 | ||
45 | wl1271_debug(DEBUG_PSM, "chip to elp"); | 45 | wl1271_debug(DEBUG_PSM, "chip to elp"); |
46 | wl1271_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, ELPCTRL_SLEEP); | 46 | wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, ELPCTRL_SLEEP); |
47 | wl->elp = true; | 47 | wl->elp = true; |
48 | 48 | ||
49 | out: | 49 | out: |
@@ -86,7 +86,7 @@ int wl1271_ps_elp_wakeup(struct wl1271 *wl, bool chip_awake) | |||
86 | wl->elp_compl = &compl; | 86 | wl->elp_compl = &compl; |
87 | spin_unlock_irqrestore(&wl->wl_lock, flags); | 87 | spin_unlock_irqrestore(&wl->wl_lock, flags); |
88 | 88 | ||
89 | wl1271_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, ELPCTRL_WAKE_UP); | 89 | wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, ELPCTRL_WAKE_UP); |
90 | 90 | ||
91 | if (!pending) { | 91 | if (!pending) { |
92 | ret = wait_for_completion_timeout( | 92 | ret = wait_for_completion_timeout( |
diff --git a/drivers/net/wireless/wl12xx/wl1271_rx.c b/drivers/net/wireless/wl12xx/wl1271_rx.c index 1d9865371f17..7979b69ec52d 100644 --- a/drivers/net/wireless/wl12xx/wl1271_rx.c +++ b/drivers/net/wireless/wl12xx/wl1271_rx.c | |||
@@ -132,7 +132,7 @@ static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length) | |||
132 | } | 132 | } |
133 | 133 | ||
134 | buf = skb_put(skb, length); | 134 | buf = skb_put(skb, length); |
135 | wl1271_spi_reg_read(wl, WL1271_SLV_MEM_DATA, buf, length, true); | 135 | wl1271_spi_read(wl, WL1271_SLV_MEM_DATA, buf, length, true); |
136 | 136 | ||
137 | /* the data read starts with the descriptor */ | 137 | /* the data read starts with the descriptor */ |
138 | desc = (struct wl1271_rx_descriptor *) buf; | 138 | desc = (struct wl1271_rx_descriptor *) buf; |
@@ -176,9 +176,9 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status) | |||
176 | wl->rx_mem_pool_addr.addr + 4; | 176 | wl->rx_mem_pool_addr.addr + 4; |
177 | 177 | ||
178 | /* Choose the block we want to read */ | 178 | /* Choose the block we want to read */ |
179 | wl1271_spi_reg_write(wl, WL1271_SLV_REG_DATA, | 179 | wl1271_spi_write(wl, WL1271_SLV_REG_DATA, |
180 | &wl->rx_mem_pool_addr, | 180 | &wl->rx_mem_pool_addr, |
181 | sizeof(wl->rx_mem_pool_addr), false); | 181 | sizeof(wl->rx_mem_pool_addr), false); |
182 | 182 | ||
183 | wl1271_rx_handle_data(wl, buf_size); | 183 | wl1271_rx_handle_data(wl, buf_size); |
184 | 184 | ||
@@ -186,5 +186,5 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status) | |||
186 | drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK; | 186 | drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK; |
187 | } | 187 | } |
188 | 188 | ||
189 | wl1271_reg_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter); | 189 | wl1271_spi_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter); |
190 | } | 190 | } |
diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.c b/drivers/net/wireless/wl12xx/wl1271_spi.c index 7a7890b77b89..4800fdfd2373 100644 --- a/drivers/net/wireless/wl12xx/wl1271_spi.c +++ b/drivers/net/wireless/wl12xx/wl1271_spi.c | |||
@@ -183,13 +183,13 @@ int wl1271_set_partition(struct wl1271 *wl, | |||
183 | p->mem3.start, p->mem3.size); | 183 | p->mem3.start, p->mem3.size); |
184 | 184 | ||
185 | /* write partition info to the chipset */ | 185 | /* write partition info to the chipset */ |
186 | wl1271_write32(wl, HW_PART0_START_ADDR, p->mem.start); | 186 | wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start); |
187 | wl1271_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size); | 187 | wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size); |
188 | wl1271_write32(wl, HW_PART1_START_ADDR, p->reg.start); | 188 | wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start); |
189 | wl1271_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size); | 189 | wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size); |
190 | wl1271_write32(wl, HW_PART2_START_ADDR, p->mem2.start); | 190 | wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start); |
191 | wl1271_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size); | 191 | wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size); |
192 | wl1271_write32(wl, HW_PART3_START_ADDR, p->mem3.start); | 192 | wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start); |
193 | 193 | ||
194 | return 0; | 194 | return 0; |
195 | } | 195 | } |
@@ -257,8 +257,8 @@ void wl1271_spi_read_busy(struct wl1271 *wl, void *buf, size_t len) | |||
257 | wl1271_error("SPI read busy-word timeout!\n"); | 257 | wl1271_error("SPI read busy-word timeout!\n"); |
258 | } | 258 | } |
259 | 259 | ||
260 | void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, | 260 | void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf, |
261 | size_t len, bool fixed) | 261 | size_t len, bool fixed) |
262 | { | 262 | { |
263 | struct spi_transfer t[3]; | 263 | struct spi_transfer t[3]; |
264 | struct spi_message m; | 264 | struct spi_message m; |
@@ -302,8 +302,8 @@ void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, | |||
302 | wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, len); | 302 | wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, len); |
303 | } | 303 | } |
304 | 304 | ||
305 | void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, | 305 | void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf, |
306 | size_t len, bool fixed) | 306 | size_t len, bool fixed) |
307 | { | 307 | { |
308 | struct spi_transfer t[2]; | 308 | struct spi_transfer t[2]; |
309 | struct spi_message m; | 309 | struct spi_message m; |
@@ -336,77 +336,47 @@ void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, | |||
336 | wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, len); | 336 | wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, len); |
337 | } | 337 | } |
338 | 338 | ||
339 | void wl1271_spi_mem_read(struct wl1271 *wl, int addr, void *buf, | 339 | void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len, |
340 | size_t len) | 340 | bool fixed) |
341 | { | 341 | { |
342 | int physical; | 342 | int physical; |
343 | 343 | ||
344 | physical = wl1271_translate_addr(wl, addr); | 344 | physical = wl1271_translate_addr(wl, addr); |
345 | 345 | ||
346 | wl1271_spi_read(wl, physical, buf, len, false); | 346 | wl1271_spi_raw_read(wl, physical, buf, len, fixed); |
347 | } | 347 | } |
348 | 348 | ||
349 | void wl1271_spi_mem_write(struct wl1271 *wl, int addr, void *buf, | 349 | void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len, |
350 | size_t len) | 350 | bool fixed) |
351 | { | 351 | { |
352 | int physical; | 352 | int physical; |
353 | 353 | ||
354 | physical = wl1271_translate_addr(wl, addr); | 354 | physical = wl1271_translate_addr(wl, addr); |
355 | 355 | ||
356 | wl1271_spi_write(wl, physical, buf, len, false); | 356 | wl1271_spi_raw_write(wl, physical, buf, len, fixed); |
357 | } | 357 | } |
358 | 358 | ||
359 | void wl1271_spi_reg_read(struct wl1271 *wl, int addr, void *buf, size_t len, | 359 | u32 wl1271_spi_read32(struct wl1271 *wl, int addr) |
360 | bool fixed) | ||
361 | { | 360 | { |
362 | int physical; | 361 | return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr)); |
363 | |||
364 | physical = wl1271_translate_addr(wl, addr); | ||
365 | |||
366 | wl1271_spi_read(wl, physical, buf, len, fixed); | ||
367 | } | ||
368 | |||
369 | void wl1271_spi_reg_write(struct wl1271 *wl, int addr, void *buf, size_t len, | ||
370 | bool fixed) | ||
371 | { | ||
372 | int physical; | ||
373 | |||
374 | physical = wl1271_translate_addr(wl, addr); | ||
375 | |||
376 | wl1271_spi_write(wl, physical, buf, len, fixed); | ||
377 | } | 362 | } |
378 | 363 | ||
379 | u32 wl1271_mem_read32(struct wl1271 *wl, int addr) | 364 | void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val) |
380 | { | 365 | { |
381 | return wl1271_read32(wl, wl1271_translate_addr(wl, addr)); | 366 | wl1271_raw_write32(wl, wl1271_translate_addr(wl, addr), val); |
382 | } | ||
383 | |||
384 | void wl1271_mem_write32(struct wl1271 *wl, int addr, u32 val) | ||
385 | { | ||
386 | wl1271_write32(wl, wl1271_translate_addr(wl, addr), val); | ||
387 | } | ||
388 | |||
389 | u32 wl1271_reg_read32(struct wl1271 *wl, int addr) | ||
390 | { | ||
391 | return wl1271_read32(wl, wl1271_translate_addr(wl, addr)); | ||
392 | } | ||
393 | |||
394 | void wl1271_reg_write32(struct wl1271 *wl, int addr, u32 val) | ||
395 | { | ||
396 | wl1271_write32(wl, wl1271_translate_addr(wl, addr), val); | ||
397 | } | 367 | } |
398 | 368 | ||
399 | void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val) | 369 | void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val) |
400 | { | 370 | { |
401 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ | 371 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ |
402 | addr = (addr >> 1) + 0x30000; | 372 | addr = (addr >> 1) + 0x30000; |
403 | wl1271_reg_write32(wl, OCP_POR_CTR, addr); | 373 | wl1271_spi_write32(wl, OCP_POR_CTR, addr); |
404 | 374 | ||
405 | /* write value to OCP_POR_WDATA */ | 375 | /* write value to OCP_POR_WDATA */ |
406 | wl1271_reg_write32(wl, OCP_DATA_WRITE, val); | 376 | wl1271_spi_write32(wl, OCP_DATA_WRITE, val); |
407 | 377 | ||
408 | /* write 1 to OCP_CMD */ | 378 | /* write 1 to OCP_CMD */ |
409 | wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_WRITE); | 379 | wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_WRITE); |
410 | } | 380 | } |
411 | 381 | ||
412 | u16 wl1271_top_reg_read(struct wl1271 *wl, int addr) | 382 | u16 wl1271_top_reg_read(struct wl1271 *wl, int addr) |
@@ -416,14 +386,14 @@ u16 wl1271_top_reg_read(struct wl1271 *wl, int addr) | |||
416 | 386 | ||
417 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ | 387 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ |
418 | addr = (addr >> 1) + 0x30000; | 388 | addr = (addr >> 1) + 0x30000; |
419 | wl1271_reg_write32(wl, OCP_POR_CTR, addr); | 389 | wl1271_spi_write32(wl, OCP_POR_CTR, addr); |
420 | 390 | ||
421 | /* write 2 to OCP_CMD */ | 391 | /* write 2 to OCP_CMD */ |
422 | wl1271_reg_write32(wl, OCP_CMD, OCP_CMD_READ); | 392 | wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_READ); |
423 | 393 | ||
424 | /* poll for data ready */ | 394 | /* poll for data ready */ |
425 | do { | 395 | do { |
426 | val = wl1271_reg_read32(wl, OCP_DATA_READ); | 396 | val = wl1271_spi_read32(wl, OCP_DATA_READ); |
427 | timeout--; | 397 | timeout--; |
428 | } while (!(val & OCP_READY_MASK) && timeout); | 398 | } while (!(val & OCP_READY_MASK) && timeout); |
429 | 399 | ||
@@ -440,4 +410,3 @@ u16 wl1271_top_reg_read(struct wl1271 *wl, int addr) | |||
440 | return 0xffff; | 410 | return 0xffff; |
441 | } | 411 | } |
442 | } | 412 | } |
443 | |||
diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.h b/drivers/net/wireless/wl12xx/wl1271_spi.h index 4f1608e99c29..cb7df1c56314 100644 --- a/drivers/net/wireless/wl12xx/wl1271_spi.h +++ b/drivers/net/wireless/wl12xx/wl1271_spi.h | |||
@@ -85,24 +85,18 @@ | |||
85 | #define OCP_STATUS_RESP_ERROR 0x30000 | 85 | #define OCP_STATUS_RESP_ERROR 0x30000 |
86 | 86 | ||
87 | /* Raw target IO, address is not translated */ | 87 | /* Raw target IO, address is not translated */ |
88 | void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, | 88 | void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf, |
89 | size_t len, bool fixed); | 89 | size_t len, bool fixed); |
90 | void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, | 90 | void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf, |
91 | size_t len, bool fixed); | 91 | size_t len, bool fixed); |
92 | 92 | ||
93 | /* Memory target IO, address is tranlated to partition 0 */ | 93 | /* Translated target IO */ |
94 | void wl1271_spi_mem_read(struct wl1271 *wl, int addr, void *buf, size_t len); | 94 | void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len, |
95 | void wl1271_spi_mem_write(struct wl1271 *wl, int addr, void *buf, size_t len); | 95 | bool fixed); |
96 | u32 wl1271_mem_read32(struct wl1271 *wl, int addr); | 96 | void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len, |
97 | void wl1271_mem_write32(struct wl1271 *wl, int addr, u32 val); | 97 | bool fixed); |
98 | 98 | u32 wl1271_spi_read32(struct wl1271 *wl, int addr); | |
99 | /* Registers IO */ | 99 | void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val); |
100 | void wl1271_spi_reg_read(struct wl1271 *wl, int addr, void *buf, size_t len, | ||
101 | bool fixed); | ||
102 | void wl1271_spi_reg_write(struct wl1271 *wl, int addr, void *buf, size_t len, | ||
103 | bool fixed); | ||
104 | u32 wl1271_reg_read32(struct wl1271 *wl, int addr); | ||
105 | void wl1271_reg_write32(struct wl1271 *wl, int addr, u32 val); | ||
106 | 100 | ||
107 | /* Top Register IO */ | 101 | /* Top Register IO */ |
108 | void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val); | 102 | void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val); |
@@ -114,19 +108,19 @@ void wl1271_spi_init(struct wl1271 *wl); | |||
114 | int wl1271_set_partition(struct wl1271 *wl, | 108 | int wl1271_set_partition(struct wl1271 *wl, |
115 | struct wl1271_partition_set *p); | 109 | struct wl1271_partition_set *p); |
116 | 110 | ||
117 | static inline u32 wl1271_read32(struct wl1271 *wl, int addr) | 111 | static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr) |
118 | { | 112 | { |
119 | wl1271_spi_read(wl, addr, &wl->buffer_32, | 113 | wl1271_spi_raw_read(wl, addr, &wl->buffer_32, |
120 | sizeof(wl->buffer_32), false); | 114 | sizeof(wl->buffer_32), false); |
121 | 115 | ||
122 | return wl->buffer_32; | 116 | return wl->buffer_32; |
123 | } | 117 | } |
124 | 118 | ||
125 | static inline void wl1271_write32(struct wl1271 *wl, int addr, u32 val) | 119 | static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val) |
126 | { | 120 | { |
127 | wl->buffer_32 = val; | 121 | wl->buffer_32 = val; |
128 | wl1271_spi_write(wl, addr, &wl->buffer_32, | 122 | wl1271_spi_raw_write(wl, addr, &wl->buffer_32, |
129 | sizeof(wl->buffer_32), false); | 123 | sizeof(wl->buffer_32), false); |
130 | } | 124 | } |
131 | 125 | ||
132 | #endif /* __WL1271_SPI_H__ */ | 126 | #endif /* __WL1271_SPI_H__ */ |
diff --git a/drivers/net/wireless/wl12xx/wl1271_tx.c b/drivers/net/wireless/wl12xx/wl1271_tx.c index 56a7f36380b7..4560458a6d60 100644 --- a/drivers/net/wireless/wl12xx/wl1271_tx.c +++ b/drivers/net/wireless/wl12xx/wl1271_tx.c | |||
@@ -154,11 +154,11 @@ static int wl1271_tx_send_packet(struct wl1271 *wl, struct sk_buff *skb, | |||
154 | len = WL1271_TX_ALIGN(skb->len); | 154 | len = WL1271_TX_ALIGN(skb->len); |
155 | 155 | ||
156 | /* perform a fixed address block write with the packet */ | 156 | /* perform a fixed address block write with the packet */ |
157 | wl1271_spi_reg_write(wl, WL1271_SLV_MEM_DATA, skb->data, len, true); | 157 | wl1271_spi_write(wl, WL1271_SLV_MEM_DATA, skb->data, len, true); |
158 | 158 | ||
159 | /* write packet new counter into the write access register */ | 159 | /* write packet new counter into the write access register */ |
160 | wl->tx_packets_count++; | 160 | wl->tx_packets_count++; |
161 | wl1271_reg_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count); | 161 | wl1271_spi_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count); |
162 | 162 | ||
163 | desc = (struct wl1271_tx_hw_descr *) skb->data; | 163 | desc = (struct wl1271_tx_hw_descr *) skb->data; |
164 | wl1271_debug(DEBUG_TX, "tx id %u skb 0x%p payload %u (%u words)", | 164 | wl1271_debug(DEBUG_TX, "tx id %u skb 0x%p payload %u (%u words)", |
@@ -331,8 +331,8 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count) | |||
331 | wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count); | 331 | wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count); |
332 | 332 | ||
333 | /* read the tx results from the chipset */ | 333 | /* read the tx results from the chipset */ |
334 | wl1271_spi_mem_read(wl, memmap->tx_result, | 334 | wl1271_spi_read(wl, memmap->tx_result, |
335 | wl->tx_res_if, sizeof(*wl->tx_res_if)); | 335 | wl->tx_res_if, sizeof(*wl->tx_res_if), false); |
336 | 336 | ||
337 | /* verify that the result buffer is not getting overrun */ | 337 | /* verify that the result buffer is not getting overrun */ |
338 | if (count > TX_HW_RESULT_QUEUE_LEN) { | 338 | if (count > TX_HW_RESULT_QUEUE_LEN) { |
@@ -353,7 +353,7 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count) | |||
353 | } | 353 | } |
354 | 354 | ||
355 | /* write host counter to chipset (to ack) */ | 355 | /* write host counter to chipset (to ack) */ |
356 | wl1271_mem_write32(wl, memmap->tx_result + | 356 | wl1271_spi_write32(wl, memmap->tx_result + |
357 | offsetof(struct wl1271_tx_hw_res_if, | 357 | offsetof(struct wl1271_tx_hw_res_if, |
358 | tx_result_host_counter), | 358 | tx_result_host_counter), |
359 | wl->tx_res_if->tx_result_fw_counter); | 359 | wl->tx_res_if->tx_result_fw_counter); |