diff options
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/80003es2lan.c | 18 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/82571.c | 30 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/ich8lan.c | 176 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/mac.c | 15 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/manage.c | 32 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/netdev.c | 12 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/nvm.c | 22 | ||||
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/phy.c | 210 |
8 files changed, 212 insertions, 303 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c index 05a79cbb1ca8..bc960fed8bf6 100644 --- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c +++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c | |||
@@ -714,22 +714,19 @@ static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |||
714 | 714 | ||
715 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | 715 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); |
716 | if (ret_val) | 716 | if (ret_val) |
717 | goto out; | 717 | return ret_val; |
718 | 718 | ||
719 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | 719 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; |
720 | 720 | ||
721 | if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) { | 721 | if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) |
722 | ret_val = -E1000_ERR_PHY; | 722 | return -E1000_ERR_PHY; |
723 | goto out; | ||
724 | } | ||
725 | 723 | ||
726 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; | 724 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; |
727 | phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; | 725 | phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; |
728 | 726 | ||
729 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | 727 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
730 | 728 | ||
731 | out: | 729 | return 0; |
732 | return ret_val; | ||
733 | } | 730 | } |
734 | 731 | ||
735 | /** | 732 | /** |
@@ -1348,12 +1345,9 @@ static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) | |||
1348 | */ | 1345 | */ |
1349 | ret_val = e1000_check_alt_mac_addr_generic(hw); | 1346 | ret_val = e1000_check_alt_mac_addr_generic(hw); |
1350 | if (ret_val) | 1347 | if (ret_val) |
1351 | goto out; | 1348 | return ret_val; |
1352 | |||
1353 | ret_val = e1000_read_mac_addr_generic(hw); | ||
1354 | 1349 | ||
1355 | out: | 1350 | return e1000_read_mac_addr_generic(hw); |
1356 | return ret_val; | ||
1357 | } | 1351 | } |
1358 | 1352 | ||
1359 | /** | 1353 | /** |
diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c index 05e9a2911168..b6b7bc4c33aa 100644 --- a/drivers/net/ethernet/intel/e1000e/82571.c +++ b/drivers/net/ethernet/intel/e1000e/82571.c | |||
@@ -564,7 +564,6 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |||
564 | static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) | 564 | static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) |
565 | { | 565 | { |
566 | u32 extcnf_ctrl; | 566 | u32 extcnf_ctrl; |
567 | s32 ret_val = 0; | ||
568 | s32 i = 0; | 567 | s32 i = 0; |
569 | 568 | ||
570 | extcnf_ctrl = er32(EXTCNF_CTRL); | 569 | extcnf_ctrl = er32(EXTCNF_CTRL); |
@@ -586,12 +585,10 @@ static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) | |||
586 | /* Release semaphores */ | 585 | /* Release semaphores */ |
587 | e1000_put_hw_semaphore_82573(hw); | 586 | e1000_put_hw_semaphore_82573(hw); |
588 | e_dbg("Driver can't access the PHY\n"); | 587 | e_dbg("Driver can't access the PHY\n"); |
589 | ret_val = -E1000_ERR_PHY; | 588 | return -E1000_ERR_PHY; |
590 | goto out; | ||
591 | } | 589 | } |
592 | 590 | ||
593 | out: | 591 | return 0; |
594 | return ret_val; | ||
595 | } | 592 | } |
596 | 593 | ||
597 | /** | 594 | /** |
@@ -1409,7 +1406,6 @@ bool e1000_check_phy_82574(struct e1000_hw *hw) | |||
1409 | { | 1406 | { |
1410 | u16 status_1kbt = 0; | 1407 | u16 status_1kbt = 0; |
1411 | u16 receive_errors = 0; | 1408 | u16 receive_errors = 0; |
1412 | bool phy_hung = false; | ||
1413 | s32 ret_val = 0; | 1409 | s32 ret_val = 0; |
1414 | 1410 | ||
1415 | /* | 1411 | /* |
@@ -1417,19 +1413,18 @@ bool e1000_check_phy_82574(struct e1000_hw *hw) | |||
1417 | * read the Base1000T status register If both are max then PHY is hung. | 1413 | * read the Base1000T status register If both are max then PHY is hung. |
1418 | */ | 1414 | */ |
1419 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); | 1415 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); |
1420 | |||
1421 | if (ret_val) | 1416 | if (ret_val) |
1422 | goto out; | 1417 | return false; |
1423 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { | 1418 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { |
1424 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); | 1419 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); |
1425 | if (ret_val) | 1420 | if (ret_val) |
1426 | goto out; | 1421 | return false; |
1427 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == | 1422 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == |
1428 | E1000_IDLE_ERROR_COUNT_MASK) | 1423 | E1000_IDLE_ERROR_COUNT_MASK) |
1429 | phy_hung = true; | 1424 | return true; |
1430 | } | 1425 | } |
1431 | out: | 1426 | |
1432 | return phy_hung; | 1427 | return false; |
1433 | } | 1428 | } |
1434 | 1429 | ||
1435 | /** | 1430 | /** |
@@ -1831,9 +1826,9 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |||
1831 | **/ | 1826 | **/ |
1832 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | 1827 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) |
1833 | { | 1828 | { |
1834 | s32 ret_val = 0; | ||
1835 | |||
1836 | if (hw->mac.type == e1000_82571) { | 1829 | if (hw->mac.type == e1000_82571) { |
1830 | s32 ret_val = 0; | ||
1831 | |||
1837 | /* | 1832 | /* |
1838 | * If there's an alternate MAC address place it in RAR0 | 1833 | * If there's an alternate MAC address place it in RAR0 |
1839 | * so that it will override the Si installed default perm | 1834 | * so that it will override the Si installed default perm |
@@ -1841,13 +1836,10 @@ static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |||
1841 | */ | 1836 | */ |
1842 | ret_val = e1000_check_alt_mac_addr_generic(hw); | 1837 | ret_val = e1000_check_alt_mac_addr_generic(hw); |
1843 | if (ret_val) | 1838 | if (ret_val) |
1844 | goto out; | 1839 | return ret_val; |
1845 | } | 1840 | } |
1846 | 1841 | ||
1847 | ret_val = e1000_read_mac_addr_generic(hw); | 1842 | return e1000_read_mac_addr_generic(hw); |
1848 | |||
1849 | out: | ||
1850 | return ret_val; | ||
1851 | } | 1843 | } |
1852 | 1844 | ||
1853 | /** | 1845 | /** |
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c index c4d65b841f35..f3282dc5588e 100644 --- a/drivers/net/ethernet/intel/e1000e/ich8lan.c +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c | |||
@@ -351,7 +351,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |||
351 | */ | 351 | */ |
352 | ret_val = e1000e_phy_hw_reset_generic(hw); | 352 | ret_val = e1000e_phy_hw_reset_generic(hw); |
353 | if (ret_val) | 353 | if (ret_val) |
354 | goto out; | 354 | return ret_val; |
355 | 355 | ||
356 | /* Ungate automatic PHY configuration on non-managed 82579 */ | 356 | /* Ungate automatic PHY configuration on non-managed 82579 */ |
357 | if ((hw->mac.type == e1000_pch2lan) && | 357 | if ((hw->mac.type == e1000_pch2lan) && |
@@ -366,7 +366,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |||
366 | default: | 366 | default: |
367 | ret_val = e1000e_get_phy_id(hw); | 367 | ret_val = e1000e_get_phy_id(hw); |
368 | if (ret_val) | 368 | if (ret_val) |
369 | goto out; | 369 | return ret_val; |
370 | if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) | 370 | if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) |
371 | break; | 371 | break; |
372 | /* fall-through */ | 372 | /* fall-through */ |
@@ -377,10 +377,10 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |||
377 | */ | 377 | */ |
378 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | 378 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
379 | if (ret_val) | 379 | if (ret_val) |
380 | goto out; | 380 | return ret_val; |
381 | ret_val = e1000e_get_phy_id(hw); | 381 | ret_val = e1000e_get_phy_id(hw); |
382 | if (ret_val) | 382 | if (ret_val) |
383 | goto out; | 383 | return ret_val; |
384 | break; | 384 | break; |
385 | } | 385 | } |
386 | phy->type = e1000e_get_phy_type_from_id(phy->id); | 386 | phy->type = e1000e_get_phy_type_from_id(phy->id); |
@@ -406,7 +406,6 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |||
406 | break; | 406 | break; |
407 | } | 407 | } |
408 | 408 | ||
409 | out: | ||
410 | return ret_val; | 409 | return ret_val; |
411 | } | 410 | } |
412 | 411 | ||
@@ -635,20 +634,18 @@ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) | |||
635 | u16 phy_reg; | 634 | u16 phy_reg; |
636 | 635 | ||
637 | if (hw->phy.type != e1000_phy_82579) | 636 | if (hw->phy.type != e1000_phy_82579) |
638 | goto out; | 637 | return 0; |
639 | 638 | ||
640 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); | 639 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
641 | if (ret_val) | 640 | if (ret_val) |
642 | goto out; | 641 | return ret_val; |
643 | 642 | ||
644 | if (hw->dev_spec.ich8lan.eee_disable) | 643 | if (hw->dev_spec.ich8lan.eee_disable) |
645 | phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; | 644 | phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; |
646 | else | 645 | else |
647 | phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; | 646 | phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; |
648 | 647 | ||
649 | ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); | 648 | return e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
650 | out: | ||
651 | return ret_val; | ||
652 | } | 649 | } |
653 | 650 | ||
654 | /** | 651 | /** |
@@ -672,10 +669,8 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |||
672 | * get_link_status flag is set upon receiving a Link Status | 669 | * get_link_status flag is set upon receiving a Link Status |
673 | * Change or Rx Sequence Error interrupt. | 670 | * Change or Rx Sequence Error interrupt. |
674 | */ | 671 | */ |
675 | if (!mac->get_link_status) { | 672 | if (!mac->get_link_status) |
676 | ret_val = 0; | 673 | return 0; |
677 | goto out; | ||
678 | } | ||
679 | 674 | ||
680 | /* | 675 | /* |
681 | * First we want to see if the MII Status Register reports | 676 | * First we want to see if the MII Status Register reports |
@@ -684,16 +679,16 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |||
684 | */ | 679 | */ |
685 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | 680 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
686 | if (ret_val) | 681 | if (ret_val) |
687 | goto out; | 682 | return ret_val; |
688 | 683 | ||
689 | if (hw->mac.type == e1000_pchlan) { | 684 | if (hw->mac.type == e1000_pchlan) { |
690 | ret_val = e1000_k1_gig_workaround_hv(hw, link); | 685 | ret_val = e1000_k1_gig_workaround_hv(hw, link); |
691 | if (ret_val) | 686 | if (ret_val) |
692 | goto out; | 687 | return ret_val; |
693 | } | 688 | } |
694 | 689 | ||
695 | if (!link) | 690 | if (!link) |
696 | goto out; /* No link detected */ | 691 | return 0; /* No link detected */ |
697 | 692 | ||
698 | mac->get_link_status = false; | 693 | mac->get_link_status = false; |
699 | 694 | ||
@@ -701,13 +696,13 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |||
701 | case e1000_pch2lan: | 696 | case e1000_pch2lan: |
702 | ret_val = e1000_k1_workaround_lv(hw); | 697 | ret_val = e1000_k1_workaround_lv(hw); |
703 | if (ret_val) | 698 | if (ret_val) |
704 | goto out; | 699 | return ret_val; |
705 | /* fall-thru */ | 700 | /* fall-thru */ |
706 | case e1000_pchlan: | 701 | case e1000_pchlan: |
707 | if (hw->phy.type == e1000_phy_82578) { | 702 | if (hw->phy.type == e1000_phy_82578) { |
708 | ret_val = e1000_link_stall_workaround_hv(hw); | 703 | ret_val = e1000_link_stall_workaround_hv(hw); |
709 | if (ret_val) | 704 | if (ret_val) |
710 | goto out; | 705 | return ret_val; |
711 | } | 706 | } |
712 | 707 | ||
713 | /* | 708 | /* |
@@ -737,16 +732,14 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |||
737 | /* Enable/Disable EEE after link up */ | 732 | /* Enable/Disable EEE after link up */ |
738 | ret_val = e1000_set_eee_pchlan(hw); | 733 | ret_val = e1000_set_eee_pchlan(hw); |
739 | if (ret_val) | 734 | if (ret_val) |
740 | goto out; | 735 | return ret_val; |
741 | 736 | ||
742 | /* | 737 | /* |
743 | * If we are forcing speed/duplex, then we simply return since | 738 | * If we are forcing speed/duplex, then we simply return since |
744 | * we have already determined whether we have link or not. | 739 | * we have already determined whether we have link or not. |
745 | */ | 740 | */ |
746 | if (!mac->autoneg) { | 741 | if (!mac->autoneg) |
747 | ret_val = -E1000_ERR_CONFIG; | 742 | return -E1000_ERR_CONFIG; |
748 | goto out; | ||
749 | } | ||
750 | 743 | ||
751 | /* | 744 | /* |
752 | * Auto-Neg is enabled. Auto Speed Detection takes care | 745 | * Auto-Neg is enabled. Auto Speed Detection takes care |
@@ -765,7 +758,6 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |||
765 | if (ret_val) | 758 | if (ret_val) |
766 | e_dbg("Error configuring flow control\n"); | 759 | e_dbg("Error configuring flow control\n"); |
767 | 760 | ||
768 | out: | ||
769 | return ret_val; | 761 | return ret_val; |
770 | } | 762 | } |
771 | 763 | ||
@@ -1008,15 +1000,13 @@ static s32 e1000_write_smbus_addr(struct e1000_hw *hw) | |||
1008 | 1000 | ||
1009 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); | 1001 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); |
1010 | if (ret_val) | 1002 | if (ret_val) |
1011 | goto out; | 1003 | return ret_val; |
1012 | 1004 | ||
1013 | phy_data &= ~HV_SMB_ADDR_MASK; | 1005 | phy_data &= ~HV_SMB_ADDR_MASK; |
1014 | phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); | 1006 | phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); |
1015 | phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; | 1007 | phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; |
1016 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); | ||
1017 | 1008 | ||
1018 | out: | 1009 | return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); |
1019 | return ret_val; | ||
1020 | } | 1010 | } |
1021 | 1011 | ||
1022 | /** | 1012 | /** |
@@ -1159,12 +1149,12 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) | |||
1159 | bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; | 1149 | bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; |
1160 | 1150 | ||
1161 | if (hw->mac.type != e1000_pchlan) | 1151 | if (hw->mac.type != e1000_pchlan) |
1162 | goto out; | 1152 | return 0; |
1163 | 1153 | ||
1164 | /* Wrap the whole flow with the sw flag */ | 1154 | /* Wrap the whole flow with the sw flag */ |
1165 | ret_val = hw->phy.ops.acquire(hw); | 1155 | ret_val = hw->phy.ops.acquire(hw); |
1166 | if (ret_val) | 1156 | if (ret_val) |
1167 | goto out; | 1157 | return ret_val; |
1168 | 1158 | ||
1169 | /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ | 1159 | /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ |
1170 | if (link) { | 1160 | if (link) { |
@@ -1218,7 +1208,7 @@ static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) | |||
1218 | 1208 | ||
1219 | release: | 1209 | release: |
1220 | hw->phy.ops.release(hw); | 1210 | hw->phy.ops.release(hw); |
1221 | out: | 1211 | |
1222 | return ret_val; | 1212 | return ret_val; |
1223 | } | 1213 | } |
1224 | 1214 | ||
@@ -1244,7 +1234,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) | |||
1244 | E1000_KMRNCTRLSTA_K1_CONFIG, | 1234 | E1000_KMRNCTRLSTA_K1_CONFIG, |
1245 | &kmrn_reg); | 1235 | &kmrn_reg); |
1246 | if (ret_val) | 1236 | if (ret_val) |
1247 | goto out; | 1237 | return ret_val; |
1248 | 1238 | ||
1249 | if (k1_enable) | 1239 | if (k1_enable) |
1250 | kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; | 1240 | kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; |
@@ -1255,7 +1245,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) | |||
1255 | E1000_KMRNCTRLSTA_K1_CONFIG, | 1245 | E1000_KMRNCTRLSTA_K1_CONFIG, |
1256 | kmrn_reg); | 1246 | kmrn_reg); |
1257 | if (ret_val) | 1247 | if (ret_val) |
1258 | goto out; | 1248 | return ret_val; |
1259 | 1249 | ||
1260 | udelay(20); | 1250 | udelay(20); |
1261 | ctrl_ext = er32(CTRL_EXT); | 1251 | ctrl_ext = er32(CTRL_EXT); |
@@ -1273,8 +1263,7 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) | |||
1273 | e1e_flush(); | 1263 | e1e_flush(); |
1274 | udelay(20); | 1264 | udelay(20); |
1275 | 1265 | ||
1276 | out: | 1266 | return 0; |
1277 | return ret_val; | ||
1278 | } | 1267 | } |
1279 | 1268 | ||
1280 | /** | 1269 | /** |
@@ -1376,13 +1365,13 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |||
1376 | u16 phy_data; | 1365 | u16 phy_data; |
1377 | 1366 | ||
1378 | if (hw->mac.type != e1000_pchlan) | 1367 | if (hw->mac.type != e1000_pchlan) |
1379 | return ret_val; | 1368 | return 0; |
1380 | 1369 | ||
1381 | /* Set MDIO slow mode before any other MDIO access */ | 1370 | /* Set MDIO slow mode before any other MDIO access */ |
1382 | if (hw->phy.type == e1000_phy_82577) { | 1371 | if (hw->phy.type == e1000_phy_82577) { |
1383 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | 1372 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
1384 | if (ret_val) | 1373 | if (ret_val) |
1385 | goto out; | 1374 | return ret_val; |
1386 | } | 1375 | } |
1387 | 1376 | ||
1388 | if (((hw->phy.type == e1000_phy_82577) && | 1377 | if (((hw->phy.type == e1000_phy_82577) && |
@@ -1419,7 +1408,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |||
1419 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); | 1408 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); |
1420 | hw->phy.ops.release(hw); | 1409 | hw->phy.ops.release(hw); |
1421 | if (ret_val) | 1410 | if (ret_val) |
1422 | goto out; | 1411 | return ret_val; |
1423 | 1412 | ||
1424 | /* | 1413 | /* |
1425 | * Configure the K1 Si workaround during phy reset assuming there is | 1414 | * Configure the K1 Si workaround during phy reset assuming there is |
@@ -1427,12 +1416,12 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |||
1427 | */ | 1416 | */ |
1428 | ret_val = e1000_k1_gig_workaround_hv(hw, true); | 1417 | ret_val = e1000_k1_gig_workaround_hv(hw, true); |
1429 | if (ret_val) | 1418 | if (ret_val) |
1430 | goto out; | 1419 | return ret_val; |
1431 | 1420 | ||
1432 | /* Workaround for link disconnects on a busy hub in half duplex */ | 1421 | /* Workaround for link disconnects on a busy hub in half duplex */ |
1433 | ret_val = hw->phy.ops.acquire(hw); | 1422 | ret_val = hw->phy.ops.acquire(hw); |
1434 | if (ret_val) | 1423 | if (ret_val) |
1435 | goto out; | 1424 | return ret_val; |
1436 | ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); | 1425 | ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data); |
1437 | if (ret_val) | 1426 | if (ret_val) |
1438 | goto release; | 1427 | goto release; |
@@ -1440,7 +1429,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |||
1440 | phy_data & 0x00FF); | 1429 | phy_data & 0x00FF); |
1441 | release: | 1430 | release: |
1442 | hw->phy.ops.release(hw); | 1431 | hw->phy.ops.release(hw); |
1443 | out: | 1432 | |
1444 | return ret_val; | 1433 | return ret_val; |
1445 | } | 1434 | } |
1446 | 1435 | ||
@@ -1497,13 +1486,13 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) | |||
1497 | u16 i; | 1486 | u16 i; |
1498 | 1487 | ||
1499 | if (hw->mac.type != e1000_pch2lan) | 1488 | if (hw->mac.type != e1000_pch2lan) |
1500 | goto out; | 1489 | return 0; |
1501 | 1490 | ||
1502 | /* disable Rx path while enabling/disabling workaround */ | 1491 | /* disable Rx path while enabling/disabling workaround */ |
1503 | e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); | 1492 | e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); |
1504 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); | 1493 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); |
1505 | if (ret_val) | 1494 | if (ret_val) |
1506 | goto out; | 1495 | return ret_val; |
1507 | 1496 | ||
1508 | if (enable) { | 1497 | if (enable) { |
1509 | /* | 1498 | /* |
@@ -1545,24 +1534,24 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) | |||
1545 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | 1534 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
1546 | &data); | 1535 | &data); |
1547 | if (ret_val) | 1536 | if (ret_val) |
1548 | goto out; | 1537 | return ret_val; |
1549 | ret_val = e1000e_write_kmrn_reg(hw, | 1538 | ret_val = e1000e_write_kmrn_reg(hw, |
1550 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | 1539 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
1551 | data | (1 << 0)); | 1540 | data | (1 << 0)); |
1552 | if (ret_val) | 1541 | if (ret_val) |
1553 | goto out; | 1542 | return ret_val; |
1554 | ret_val = e1000e_read_kmrn_reg(hw, | 1543 | ret_val = e1000e_read_kmrn_reg(hw, |
1555 | E1000_KMRNCTRLSTA_HD_CTRL, | 1544 | E1000_KMRNCTRLSTA_HD_CTRL, |
1556 | &data); | 1545 | &data); |
1557 | if (ret_val) | 1546 | if (ret_val) |
1558 | goto out; | 1547 | return ret_val; |
1559 | data &= ~(0xF << 8); | 1548 | data &= ~(0xF << 8); |
1560 | data |= (0xB << 8); | 1549 | data |= (0xB << 8); |
1561 | ret_val = e1000e_write_kmrn_reg(hw, | 1550 | ret_val = e1000e_write_kmrn_reg(hw, |
1562 | E1000_KMRNCTRLSTA_HD_CTRL, | 1551 | E1000_KMRNCTRLSTA_HD_CTRL, |
1563 | data); | 1552 | data); |
1564 | if (ret_val) | 1553 | if (ret_val) |
1565 | goto out; | 1554 | return ret_val; |
1566 | 1555 | ||
1567 | /* Enable jumbo frame workaround in the PHY */ | 1556 | /* Enable jumbo frame workaround in the PHY */ |
1568 | e1e_rphy(hw, PHY_REG(769, 23), &data); | 1557 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
@@ -1570,25 +1559,25 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) | |||
1570 | data |= (0x37 << 5); | 1559 | data |= (0x37 << 5); |
1571 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); | 1560 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
1572 | if (ret_val) | 1561 | if (ret_val) |
1573 | goto out; | 1562 | return ret_val; |
1574 | e1e_rphy(hw, PHY_REG(769, 16), &data); | 1563 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
1575 | data &= ~(1 << 13); | 1564 | data &= ~(1 << 13); |
1576 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); | 1565 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
1577 | if (ret_val) | 1566 | if (ret_val) |
1578 | goto out; | 1567 | return ret_val; |
1579 | e1e_rphy(hw, PHY_REG(776, 20), &data); | 1568 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
1580 | data &= ~(0x3FF << 2); | 1569 | data &= ~(0x3FF << 2); |
1581 | data |= (0x1A << 2); | 1570 | data |= (0x1A << 2); |
1582 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); | 1571 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
1583 | if (ret_val) | 1572 | if (ret_val) |
1584 | goto out; | 1573 | return ret_val; |
1585 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); | 1574 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); |
1586 | if (ret_val) | 1575 | if (ret_val) |
1587 | goto out; | 1576 | return ret_val; |
1588 | e1e_rphy(hw, HV_PM_CTRL, &data); | 1577 | e1e_rphy(hw, HV_PM_CTRL, &data); |
1589 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); | 1578 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); |
1590 | if (ret_val) | 1579 | if (ret_val) |
1591 | goto out; | 1580 | return ret_val; |
1592 | } else { | 1581 | } else { |
1593 | /* Write MAC register values back to h/w defaults */ | 1582 | /* Write MAC register values back to h/w defaults */ |
1594 | mac_reg = er32(FFLT_DBG); | 1583 | mac_reg = er32(FFLT_DBG); |
@@ -1603,56 +1592,53 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) | |||
1603 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | 1592 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
1604 | &data); | 1593 | &data); |
1605 | if (ret_val) | 1594 | if (ret_val) |
1606 | goto out; | 1595 | return ret_val; |
1607 | ret_val = e1000e_write_kmrn_reg(hw, | 1596 | ret_val = e1000e_write_kmrn_reg(hw, |
1608 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | 1597 | E1000_KMRNCTRLSTA_CTRL_OFFSET, |
1609 | data & ~(1 << 0)); | 1598 | data & ~(1 << 0)); |
1610 | if (ret_val) | 1599 | if (ret_val) |
1611 | goto out; | 1600 | return ret_val; |
1612 | ret_val = e1000e_read_kmrn_reg(hw, | 1601 | ret_val = e1000e_read_kmrn_reg(hw, |
1613 | E1000_KMRNCTRLSTA_HD_CTRL, | 1602 | E1000_KMRNCTRLSTA_HD_CTRL, |
1614 | &data); | 1603 | &data); |
1615 | if (ret_val) | 1604 | if (ret_val) |
1616 | goto out; | 1605 | return ret_val; |
1617 | data &= ~(0xF << 8); | 1606 | data &= ~(0xF << 8); |
1618 | data |= (0xB << 8); | 1607 | data |= (0xB << 8); |
1619 | ret_val = e1000e_write_kmrn_reg(hw, | 1608 | ret_val = e1000e_write_kmrn_reg(hw, |
1620 | E1000_KMRNCTRLSTA_HD_CTRL, | 1609 | E1000_KMRNCTRLSTA_HD_CTRL, |
1621 | data); | 1610 | data); |
1622 | if (ret_val) | 1611 | if (ret_val) |
1623 | goto out; | 1612 | return ret_val; |
1624 | 1613 | ||
1625 | /* Write PHY register values back to h/w defaults */ | 1614 | /* Write PHY register values back to h/w defaults */ |
1626 | e1e_rphy(hw, PHY_REG(769, 23), &data); | 1615 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
1627 | data &= ~(0x7F << 5); | 1616 | data &= ~(0x7F << 5); |
1628 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); | 1617 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); |
1629 | if (ret_val) | 1618 | if (ret_val) |
1630 | goto out; | 1619 | return ret_val; |
1631 | e1e_rphy(hw, PHY_REG(769, 16), &data); | 1620 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
1632 | data |= (1 << 13); | 1621 | data |= (1 << 13); |
1633 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); | 1622 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
1634 | if (ret_val) | 1623 | if (ret_val) |
1635 | goto out; | 1624 | return ret_val; |
1636 | e1e_rphy(hw, PHY_REG(776, 20), &data); | 1625 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
1637 | data &= ~(0x3FF << 2); | 1626 | data &= ~(0x3FF << 2); |
1638 | data |= (0x8 << 2); | 1627 | data |= (0x8 << 2); |
1639 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); | 1628 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); |
1640 | if (ret_val) | 1629 | if (ret_val) |
1641 | goto out; | 1630 | return ret_val; |
1642 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); | 1631 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); |
1643 | if (ret_val) | 1632 | if (ret_val) |
1644 | goto out; | 1633 | return ret_val; |
1645 | e1e_rphy(hw, HV_PM_CTRL, &data); | 1634 | e1e_rphy(hw, HV_PM_CTRL, &data); |
1646 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); | 1635 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); |
1647 | if (ret_val) | 1636 | if (ret_val) |
1648 | goto out; | 1637 | return ret_val; |
1649 | } | 1638 | } |
1650 | 1639 | ||
1651 | /* re-enable Rx path after enabling/disabling workaround */ | 1640 | /* re-enable Rx path after enabling/disabling workaround */ |
1652 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); | 1641 | return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); |
1653 | |||
1654 | out: | ||
1655 | return ret_val; | ||
1656 | } | 1642 | } |
1657 | 1643 | ||
1658 | /** | 1644 | /** |
@@ -1664,14 +1650,14 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |||
1664 | s32 ret_val = 0; | 1650 | s32 ret_val = 0; |
1665 | 1651 | ||
1666 | if (hw->mac.type != e1000_pch2lan) | 1652 | if (hw->mac.type != e1000_pch2lan) |
1667 | goto out; | 1653 | return 0; |
1668 | 1654 | ||
1669 | /* Set MDIO slow mode before any other MDIO access */ | 1655 | /* Set MDIO slow mode before any other MDIO access */ |
1670 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | 1656 | ret_val = e1000_set_mdio_slow_mode_hv(hw); |
1671 | 1657 | ||
1672 | ret_val = hw->phy.ops.acquire(hw); | 1658 | ret_val = hw->phy.ops.acquire(hw); |
1673 | if (ret_val) | 1659 | if (ret_val) |
1674 | goto out; | 1660 | return ret_val; |
1675 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, | 1661 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, |
1676 | I82579_MSE_THRESHOLD); | 1662 | I82579_MSE_THRESHOLD); |
1677 | if (ret_val) | 1663 | if (ret_val) |
@@ -1689,7 +1675,6 @@ static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |||
1689 | release: | 1675 | release: |
1690 | hw->phy.ops.release(hw); | 1676 | hw->phy.ops.release(hw); |
1691 | 1677 | ||
1692 | out: | ||
1693 | return ret_val; | 1678 | return ret_val; |
1694 | } | 1679 | } |
1695 | 1680 | ||
@@ -1707,12 +1692,12 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) | |||
1707 | u16 phy_reg; | 1692 | u16 phy_reg; |
1708 | 1693 | ||
1709 | if (hw->mac.type != e1000_pch2lan) | 1694 | if (hw->mac.type != e1000_pch2lan) |
1710 | goto out; | 1695 | return 0; |
1711 | 1696 | ||
1712 | /* Set K1 beacon duration based on 1Gbps speed or otherwise */ | 1697 | /* Set K1 beacon duration based on 1Gbps speed or otherwise */ |
1713 | ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); | 1698 | ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); |
1714 | if (ret_val) | 1699 | if (ret_val) |
1715 | goto out; | 1700 | return ret_val; |
1716 | 1701 | ||
1717 | if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) | 1702 | if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) |
1718 | == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { | 1703 | == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { |
@@ -1721,7 +1706,7 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) | |||
1721 | 1706 | ||
1722 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); | 1707 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
1723 | if (ret_val) | 1708 | if (ret_val) |
1724 | goto out; | 1709 | return ret_val; |
1725 | 1710 | ||
1726 | if (status_reg & HV_M_STATUS_SPEED_1000) { | 1711 | if (status_reg & HV_M_STATUS_SPEED_1000) { |
1727 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; | 1712 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; |
@@ -1734,7 +1719,6 @@ static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) | |||
1734 | ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); | 1719 | ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
1735 | } | 1720 | } |
1736 | 1721 | ||
1737 | out: | ||
1738 | return ret_val; | 1722 | return ret_val; |
1739 | } | 1723 | } |
1740 | 1724 | ||
@@ -1805,7 +1789,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) | |||
1805 | u16 reg; | 1789 | u16 reg; |
1806 | 1790 | ||
1807 | if (e1000_check_reset_block(hw)) | 1791 | if (e1000_check_reset_block(hw)) |
1808 | goto out; | 1792 | return 0; |
1809 | 1793 | ||
1810 | /* Allow time for h/w to get to quiescent state after reset */ | 1794 | /* Allow time for h/w to get to quiescent state after reset */ |
1811 | usleep_range(10000, 20000); | 1795 | usleep_range(10000, 20000); |
@@ -1815,12 +1799,12 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) | |||
1815 | case e1000_pchlan: | 1799 | case e1000_pchlan: |
1816 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); | 1800 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); |
1817 | if (ret_val) | 1801 | if (ret_val) |
1818 | goto out; | 1802 | return ret_val; |
1819 | break; | 1803 | break; |
1820 | case e1000_pch2lan: | 1804 | case e1000_pch2lan: |
1821 | ret_val = e1000_lv_phy_workarounds_ich8lan(hw); | 1805 | ret_val = e1000_lv_phy_workarounds_ich8lan(hw); |
1822 | if (ret_val) | 1806 | if (ret_val) |
1823 | goto out; | 1807 | return ret_val; |
1824 | break; | 1808 | break; |
1825 | default: | 1809 | default: |
1826 | break; | 1810 | break; |
@@ -1836,7 +1820,7 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) | |||
1836 | /* Configure the LCD with the extended configuration region in NVM */ | 1820 | /* Configure the LCD with the extended configuration region in NVM */ |
1837 | ret_val = e1000_sw_lcd_config_ich8lan(hw); | 1821 | ret_val = e1000_sw_lcd_config_ich8lan(hw); |
1838 | if (ret_val) | 1822 | if (ret_val) |
1839 | goto out; | 1823 | return ret_val; |
1840 | 1824 | ||
1841 | /* Configure the LCD with the OEM bits in NVM */ | 1825 | /* Configure the LCD with the OEM bits in NVM */ |
1842 | ret_val = e1000_oem_bits_config_ich8lan(hw, true); | 1826 | ret_val = e1000_oem_bits_config_ich8lan(hw, true); |
@@ -1851,18 +1835,16 @@ static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) | |||
1851 | /* Set EEE LPI Update Timer to 200usec */ | 1835 | /* Set EEE LPI Update Timer to 200usec */ |
1852 | ret_val = hw->phy.ops.acquire(hw); | 1836 | ret_val = hw->phy.ops.acquire(hw); |
1853 | if (ret_val) | 1837 | if (ret_val) |
1854 | goto out; | 1838 | return ret_val; |
1855 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, | 1839 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, |
1856 | I82579_LPI_UPDATE_TIMER); | 1840 | I82579_LPI_UPDATE_TIMER); |
1857 | if (ret_val) | 1841 | if (!ret_val) |
1858 | goto release; | 1842 | ret_val = hw->phy.ops.write_reg_locked(hw, |
1859 | ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, | 1843 | I82579_EMI_DATA, |
1860 | 0x1387); | 1844 | 0x1387); |
1861 | release: | ||
1862 | hw->phy.ops.release(hw); | 1845 | hw->phy.ops.release(hw); |
1863 | } | 1846 | } |
1864 | 1847 | ||
1865 | out: | ||
1866 | return ret_val; | 1848 | return ret_val; |
1867 | } | 1849 | } |
1868 | 1850 | ||
@@ -1885,12 +1867,9 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |||
1885 | 1867 | ||
1886 | ret_val = e1000e_phy_hw_reset_generic(hw); | 1868 | ret_val = e1000e_phy_hw_reset_generic(hw); |
1887 | if (ret_val) | 1869 | if (ret_val) |
1888 | goto out; | 1870 | return ret_val; |
1889 | |||
1890 | ret_val = e1000_post_phy_reset_ich8lan(hw); | ||
1891 | 1871 | ||
1892 | out: | 1872 | return e1000_post_phy_reset_ich8lan(hw); |
1893 | return ret_val; | ||
1894 | } | 1873 | } |
1895 | 1874 | ||
1896 | /** | 1875 | /** |
@@ -1911,7 +1890,7 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) | |||
1911 | 1890 | ||
1912 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); | 1891 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); |
1913 | if (ret_val) | 1892 | if (ret_val) |
1914 | goto out; | 1893 | return ret_val; |
1915 | 1894 | ||
1916 | if (active) | 1895 | if (active) |
1917 | oem_reg |= HV_OEM_BITS_LPLU; | 1896 | oem_reg |= HV_OEM_BITS_LPLU; |
@@ -1921,10 +1900,7 @@ static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) | |||
1921 | if (!e1000_check_reset_block(hw)) | 1900 | if (!e1000_check_reset_block(hw)) |
1922 | oem_reg |= HV_OEM_BITS_RESTART_AN; | 1901 | oem_reg |= HV_OEM_BITS_RESTART_AN; |
1923 | 1902 | ||
1924 | ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg); | 1903 | return e1e_wphy(hw, HV_OEM_BITS, oem_reg); |
1925 | |||
1926 | out: | ||
1927 | return ret_val; | ||
1928 | } | 1904 | } |
1929 | 1905 | ||
1930 | /** | 1906 | /** |
@@ -3001,7 +2977,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) | |||
3001 | /* Get default ID LED modes */ | 2977 | /* Get default ID LED modes */ |
3002 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); | 2978 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); |
3003 | if (ret_val) | 2979 | if (ret_val) |
3004 | goto out; | 2980 | return ret_val; |
3005 | 2981 | ||
3006 | mac->ledctl_default = er32(LEDCTL); | 2982 | mac->ledctl_default = er32(LEDCTL); |
3007 | mac->ledctl_mode1 = mac->ledctl_default; | 2983 | mac->ledctl_mode1 = mac->ledctl_default; |
@@ -3046,8 +3022,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) | |||
3046 | } | 3022 | } |
3047 | } | 3023 | } |
3048 | 3024 | ||
3049 | out: | 3025 | return 0; |
3050 | return ret_val; | ||
3051 | } | 3026 | } |
3052 | 3027 | ||
3053 | /** | 3028 | /** |
@@ -3162,11 +3137,11 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
3162 | if (ctrl & E1000_CTRL_PHY_RST) { | 3137 | if (ctrl & E1000_CTRL_PHY_RST) { |
3163 | ret_val = hw->phy.ops.get_cfg_done(hw); | 3138 | ret_val = hw->phy.ops.get_cfg_done(hw); |
3164 | if (ret_val) | 3139 | if (ret_val) |
3165 | goto out; | 3140 | return ret_val; |
3166 | 3141 | ||
3167 | ret_val = e1000_post_phy_reset_ich8lan(hw); | 3142 | ret_val = e1000_post_phy_reset_ich8lan(hw); |
3168 | if (ret_val) | 3143 | if (ret_val) |
3169 | goto out; | 3144 | return ret_val; |
3170 | } | 3145 | } |
3171 | 3146 | ||
3172 | /* | 3147 | /* |
@@ -3184,8 +3159,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
3184 | kab |= E1000_KABGTXD_BGSQLBIAS; | 3159 | kab |= E1000_KABGTXD_BGSQLBIAS; |
3185 | ew32(KABGTXD, kab); | 3160 | ew32(KABGTXD, kab); |
3186 | 3161 | ||
3187 | out: | 3162 | return 0; |
3188 | return ret_val; | ||
3189 | } | 3163 | } |
3190 | 3164 | ||
3191 | /** | 3165 | /** |
diff --git a/drivers/net/ethernet/intel/e1000e/mac.c b/drivers/net/ethernet/intel/e1000e/mac.c index 943b9090fda0..17991e63083d 100644 --- a/drivers/net/ethernet/intel/e1000e/mac.c +++ b/drivers/net/ethernet/intel/e1000e/mac.c | |||
@@ -172,23 +172,23 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) | |||
172 | 172 | ||
173 | ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); | 173 | ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); |
174 | if (ret_val) | 174 | if (ret_val) |
175 | goto out; | 175 | return ret_val; |
176 | 176 | ||
177 | /* not supported on 82573 */ | 177 | /* not supported on 82573 */ |
178 | if (hw->mac.type == e1000_82573) | 178 | if (hw->mac.type == e1000_82573) |
179 | goto out; | 179 | return 0; |
180 | 180 | ||
181 | ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, | 181 | ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, |
182 | &nvm_alt_mac_addr_offset); | 182 | &nvm_alt_mac_addr_offset); |
183 | if (ret_val) { | 183 | if (ret_val) { |
184 | e_dbg("NVM Read Error\n"); | 184 | e_dbg("NVM Read Error\n"); |
185 | goto out; | 185 | return ret_val; |
186 | } | 186 | } |
187 | 187 | ||
188 | if ((nvm_alt_mac_addr_offset == 0xFFFF) || | 188 | if ((nvm_alt_mac_addr_offset == 0xFFFF) || |
189 | (nvm_alt_mac_addr_offset == 0x0000)) | 189 | (nvm_alt_mac_addr_offset == 0x0000)) |
190 | /* There is no Alternate MAC Address */ | 190 | /* There is no Alternate MAC Address */ |
191 | goto out; | 191 | return 0; |
192 | 192 | ||
193 | if (hw->bus.func == E1000_FUNC_1) | 193 | if (hw->bus.func == E1000_FUNC_1) |
194 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; | 194 | nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; |
@@ -197,7 +197,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) | |||
197 | ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); | 197 | ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); |
198 | if (ret_val) { | 198 | if (ret_val) { |
199 | e_dbg("NVM Read Error\n"); | 199 | e_dbg("NVM Read Error\n"); |
200 | goto out; | 200 | return ret_val; |
201 | } | 201 | } |
202 | 202 | ||
203 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); | 203 | alt_mac_addr[i] = (u8)(nvm_data & 0xFF); |
@@ -207,7 +207,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) | |||
207 | /* if multicast bit is set, the alternate address will not be used */ | 207 | /* if multicast bit is set, the alternate address will not be used */ |
208 | if (is_multicast_ether_addr(alt_mac_addr)) { | 208 | if (is_multicast_ether_addr(alt_mac_addr)) { |
209 | e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); | 209 | e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); |
210 | goto out; | 210 | return 0; |
211 | } | 211 | } |
212 | 212 | ||
213 | /* | 213 | /* |
@@ -217,8 +217,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) | |||
217 | */ | 217 | */ |
218 | e1000e_rar_set(hw, alt_mac_addr, 0); | 218 | e1000e_rar_set(hw, alt_mac_addr, 0); |
219 | 219 | ||
220 | out: | 220 | return 0; |
221 | return ret_val; | ||
222 | } | 221 | } |
223 | 222 | ||
224 | /** | 223 | /** |
diff --git a/drivers/net/ethernet/intel/e1000e/manage.c b/drivers/net/ethernet/intel/e1000e/manage.c index c54caf6e5801..0d24b13ce763 100644 --- a/drivers/net/ethernet/intel/e1000e/manage.c +++ b/drivers/net/ethernet/intel/e1000e/manage.c | |||
@@ -140,7 +140,7 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |||
140 | /* No manageability, no filtering */ | 140 | /* No manageability, no filtering */ |
141 | if (!e1000e_check_mng_mode(hw)) { | 141 | if (!e1000e_check_mng_mode(hw)) { |
142 | hw->mac.tx_pkt_filtering = false; | 142 | hw->mac.tx_pkt_filtering = false; |
143 | goto out; | 143 | return hw->mac.tx_pkt_filtering; |
144 | } | 144 | } |
145 | 145 | ||
146 | /* | 146 | /* |
@@ -150,7 +150,7 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |||
150 | ret_val = e1000_mng_enable_host_if(hw); | 150 | ret_val = e1000_mng_enable_host_if(hw); |
151 | if (ret_val) { | 151 | if (ret_val) { |
152 | hw->mac.tx_pkt_filtering = false; | 152 | hw->mac.tx_pkt_filtering = false; |
153 | goto out; | 153 | return hw->mac.tx_pkt_filtering; |
154 | } | 154 | } |
155 | 155 | ||
156 | /* Read in the header. Length and offset are in dwords. */ | 156 | /* Read in the header. Length and offset are in dwords. */ |
@@ -170,16 +170,13 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw) | |||
170 | */ | 170 | */ |
171 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { | 171 | if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) { |
172 | hw->mac.tx_pkt_filtering = true; | 172 | hw->mac.tx_pkt_filtering = true; |
173 | goto out; | 173 | return hw->mac.tx_pkt_filtering; |
174 | } | 174 | } |
175 | 175 | ||
176 | /* Cookie area is valid, make the final check for filtering. */ | 176 | /* Cookie area is valid, make the final check for filtering. */ |
177 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) { | 177 | if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) |
178 | hw->mac.tx_pkt_filtering = false; | 178 | hw->mac.tx_pkt_filtering = false; |
179 | goto out; | ||
180 | } | ||
181 | 179 | ||
182 | out: | ||
183 | return hw->mac.tx_pkt_filtering; | 180 | return hw->mac.tx_pkt_filtering; |
184 | } | 181 | } |
185 | 182 | ||
@@ -336,12 +333,11 @@ bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) | |||
336 | { | 333 | { |
337 | u32 manc; | 334 | u32 manc; |
338 | u32 fwsm, factps; | 335 | u32 fwsm, factps; |
339 | bool ret_val = false; | ||
340 | 336 | ||
341 | manc = er32(MANC); | 337 | manc = er32(MANC); |
342 | 338 | ||
343 | if (!(manc & E1000_MANC_RCV_TCO_EN)) | 339 | if (!(manc & E1000_MANC_RCV_TCO_EN)) |
344 | goto out; | 340 | return false; |
345 | 341 | ||
346 | if (hw->mac.has_fwsm) { | 342 | if (hw->mac.has_fwsm) { |
347 | fwsm = er32(FWSM); | 343 | fwsm = er32(FWSM); |
@@ -349,10 +345,8 @@ bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) | |||
349 | 345 | ||
350 | if (!(factps & E1000_FACTPS_MNGCG) && | 346 | if (!(factps & E1000_FACTPS_MNGCG) && |
351 | ((fwsm & E1000_FWSM_MODE_MASK) == | 347 | ((fwsm & E1000_FWSM_MODE_MASK) == |
352 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) { | 348 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) |
353 | ret_val = true; | 349 | return true; |
354 | goto out; | ||
355 | } | ||
356 | } else if ((hw->mac.type == e1000_82574) || | 350 | } else if ((hw->mac.type == e1000_82574) || |
357 | (hw->mac.type == e1000_82583)) { | 351 | (hw->mac.type == e1000_82583)) { |
358 | u16 data; | 352 | u16 data; |
@@ -362,16 +356,12 @@ bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw) | |||
362 | 356 | ||
363 | if (!(factps & E1000_FACTPS_MNGCG) && | 357 | if (!(factps & E1000_FACTPS_MNGCG) && |
364 | ((data & E1000_NVM_INIT_CTRL2_MNGM) == | 358 | ((data & E1000_NVM_INIT_CTRL2_MNGM) == |
365 | (e1000_mng_mode_pt << 13))) { | 359 | (e1000_mng_mode_pt << 13))) |
366 | ret_val = true; | 360 | return true; |
367 | goto out; | ||
368 | } | ||
369 | } else if ((manc & E1000_MANC_SMBUS_EN) && | 361 | } else if ((manc & E1000_MANC_SMBUS_EN) && |
370 | !(manc & E1000_MANC_ASF_EN)) { | 362 | !(manc & E1000_MANC_ASF_EN)) { |
371 | ret_val = true; | 363 | return true; |
372 | goto out; | ||
373 | } | 364 | } |
374 | 365 | ||
375 | out: | 366 | return false; |
376 | return ret_val; | ||
377 | } | 367 | } |
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c index c11b40b81acf..c079b9b0810d 100644 --- a/drivers/net/ethernet/intel/e1000e/netdev.c +++ b/drivers/net/ethernet/intel/e1000e/netdev.c | |||
@@ -1985,7 +1985,7 @@ static int e1000_request_msix(struct e1000_adapter *adapter) | |||
1985 | e1000_intr_msix_rx, 0, adapter->rx_ring->name, | 1985 | e1000_intr_msix_rx, 0, adapter->rx_ring->name, |
1986 | netdev); | 1986 | netdev); |
1987 | if (err) | 1987 | if (err) |
1988 | goto out; | 1988 | return err; |
1989 | adapter->rx_ring->itr_register = adapter->hw.hw_addr + | 1989 | adapter->rx_ring->itr_register = adapter->hw.hw_addr + |
1990 | E1000_EITR_82574(vector); | 1990 | E1000_EITR_82574(vector); |
1991 | adapter->rx_ring->itr_val = adapter->itr; | 1991 | adapter->rx_ring->itr_val = adapter->itr; |
@@ -2001,7 +2001,7 @@ static int e1000_request_msix(struct e1000_adapter *adapter) | |||
2001 | e1000_intr_msix_tx, 0, adapter->tx_ring->name, | 2001 | e1000_intr_msix_tx, 0, adapter->tx_ring->name, |
2002 | netdev); | 2002 | netdev); |
2003 | if (err) | 2003 | if (err) |
2004 | goto out; | 2004 | return err; |
2005 | adapter->tx_ring->itr_register = adapter->hw.hw_addr + | 2005 | adapter->tx_ring->itr_register = adapter->hw.hw_addr + |
2006 | E1000_EITR_82574(vector); | 2006 | E1000_EITR_82574(vector); |
2007 | adapter->tx_ring->itr_val = adapter->itr; | 2007 | adapter->tx_ring->itr_val = adapter->itr; |
@@ -2010,12 +2010,11 @@ static int e1000_request_msix(struct e1000_adapter *adapter) | |||
2010 | err = request_irq(adapter->msix_entries[vector].vector, | 2010 | err = request_irq(adapter->msix_entries[vector].vector, |
2011 | e1000_msix_other, 0, netdev->name, netdev); | 2011 | e1000_msix_other, 0, netdev->name, netdev); |
2012 | if (err) | 2012 | if (err) |
2013 | goto out; | 2013 | return err; |
2014 | 2014 | ||
2015 | e1000_configure_msix(adapter); | 2015 | e1000_configure_msix(adapter); |
2016 | |||
2016 | return 0; | 2017 | return 0; |
2017 | out: | ||
2018 | return err; | ||
2019 | } | 2018 | } |
2020 | 2019 | ||
2021 | /** | 2020 | /** |
@@ -2367,7 +2366,7 @@ static unsigned int e1000_update_itr(struct e1000_adapter *adapter, | |||
2367 | unsigned int retval = itr_setting; | 2366 | unsigned int retval = itr_setting; |
2368 | 2367 | ||
2369 | if (packets == 0) | 2368 | if (packets == 0) |
2370 | goto update_itr_done; | 2369 | return itr_setting; |
2371 | 2370 | ||
2372 | switch (itr_setting) { | 2371 | switch (itr_setting) { |
2373 | case lowest_latency: | 2372 | case lowest_latency: |
@@ -2402,7 +2401,6 @@ static unsigned int e1000_update_itr(struct e1000_adapter *adapter, | |||
2402 | break; | 2401 | break; |
2403 | } | 2402 | } |
2404 | 2403 | ||
2405 | update_itr_done: | ||
2406 | return retval; | 2404 | return retval; |
2407 | } | 2405 | } |
2408 | 2406 | ||
diff --git a/drivers/net/ethernet/intel/e1000e/nvm.c b/drivers/net/ethernet/intel/e1000e/nvm.c index 1b50db59fb0d..24b7930b7500 100644 --- a/drivers/net/ethernet/intel/e1000e/nvm.c +++ b/drivers/net/ethernet/intel/e1000e/nvm.c | |||
@@ -446,20 +446,19 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, | |||
446 | 446 | ||
447 | if (pba_num == NULL) { | 447 | if (pba_num == NULL) { |
448 | e_dbg("PBA string buffer was null\n"); | 448 | e_dbg("PBA string buffer was null\n"); |
449 | ret_val = E1000_ERR_INVALID_ARGUMENT; | 449 | return -E1000_ERR_INVALID_ARGUMENT; |
450 | goto out; | ||
451 | } | 450 | } |
452 | 451 | ||
453 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); | 452 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); |
454 | if (ret_val) { | 453 | if (ret_val) { |
455 | e_dbg("NVM Read Error\n"); | 454 | e_dbg("NVM Read Error\n"); |
456 | goto out; | 455 | return ret_val; |
457 | } | 456 | } |
458 | 457 | ||
459 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); | 458 | ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr); |
460 | if (ret_val) { | 459 | if (ret_val) { |
461 | e_dbg("NVM Read Error\n"); | 460 | e_dbg("NVM Read Error\n"); |
462 | goto out; | 461 | return ret_val; |
463 | } | 462 | } |
464 | 463 | ||
465 | /* | 464 | /* |
@@ -499,25 +498,23 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, | |||
499 | pba_num[offset] += 'A' - 0xA; | 498 | pba_num[offset] += 'A' - 0xA; |
500 | } | 499 | } |
501 | 500 | ||
502 | goto out; | 501 | return 0; |
503 | } | 502 | } |
504 | 503 | ||
505 | ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); | 504 | ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length); |
506 | if (ret_val) { | 505 | if (ret_val) { |
507 | e_dbg("NVM Read Error\n"); | 506 | e_dbg("NVM Read Error\n"); |
508 | goto out; | 507 | return ret_val; |
509 | } | 508 | } |
510 | 509 | ||
511 | if (length == 0xFFFF || length == 0) { | 510 | if (length == 0xFFFF || length == 0) { |
512 | e_dbg("NVM PBA number section invalid length\n"); | 511 | e_dbg("NVM PBA number section invalid length\n"); |
513 | ret_val = E1000_ERR_NVM_PBA_SECTION; | 512 | return -E1000_ERR_NVM_PBA_SECTION; |
514 | goto out; | ||
515 | } | 513 | } |
516 | /* check if pba_num buffer is big enough */ | 514 | /* check if pba_num buffer is big enough */ |
517 | if (pba_num_size < (((u32)length * 2) - 1)) { | 515 | if (pba_num_size < (((u32)length * 2) - 1)) { |
518 | e_dbg("PBA string buffer too small\n"); | 516 | e_dbg("PBA string buffer too small\n"); |
519 | ret_val = E1000_ERR_NO_SPACE; | 517 | return -E1000_ERR_NO_SPACE; |
520 | goto out; | ||
521 | } | 518 | } |
522 | 519 | ||
523 | /* trim pba length from start of string */ | 520 | /* trim pba length from start of string */ |
@@ -528,15 +525,14 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num, | |||
528 | ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); | 525 | ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data); |
529 | if (ret_val) { | 526 | if (ret_val) { |
530 | e_dbg("NVM Read Error\n"); | 527 | e_dbg("NVM Read Error\n"); |
531 | goto out; | 528 | return ret_val; |
532 | } | 529 | } |
533 | pba_num[offset * 2] = (u8)(nvm_data >> 8); | 530 | pba_num[offset * 2] = (u8)(nvm_data >> 8); |
534 | pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); | 531 | pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); |
535 | } | 532 | } |
536 | pba_num[offset * 2] = '\0'; | 533 | pba_num[offset * 2] = '\0'; |
537 | 534 | ||
538 | out: | 535 | return 0; |
539 | return ret_val; | ||
540 | } | 536 | } |
541 | 537 | ||
542 | /** | 538 | /** |
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c index 0e86c7e761ea..d4dbbe741246 100644 --- a/drivers/net/ethernet/intel/e1000e/phy.c +++ b/drivers/net/ethernet/intel/e1000e/phy.c | |||
@@ -133,29 +133,29 @@ s32 e1000e_get_phy_id(struct e1000_hw *hw) | |||
133 | u16 retry_count = 0; | 133 | u16 retry_count = 0; |
134 | 134 | ||
135 | if (!phy->ops.read_reg) | 135 | if (!phy->ops.read_reg) |
136 | goto out; | 136 | return 0; |
137 | 137 | ||
138 | while (retry_count < 2) { | 138 | while (retry_count < 2) { |
139 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); | 139 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
140 | if (ret_val) | 140 | if (ret_val) |
141 | goto out; | 141 | return ret_val; |
142 | 142 | ||
143 | phy->id = (u32)(phy_id << 16); | 143 | phy->id = (u32)(phy_id << 16); |
144 | udelay(20); | 144 | udelay(20); |
145 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | 145 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); |
146 | if (ret_val) | 146 | if (ret_val) |
147 | goto out; | 147 | return ret_val; |
148 | 148 | ||
149 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | 149 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
150 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | 150 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); |
151 | 151 | ||
152 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) | 152 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) |
153 | goto out; | 153 | return 0; |
154 | 154 | ||
155 | retry_count++; | 155 | retry_count++; |
156 | } | 156 | } |
157 | out: | 157 | |
158 | return ret_val; | 158 | return 0; |
159 | } | 159 | } |
160 | 160 | ||
161 | /** | 161 | /** |
@@ -383,28 +383,24 @@ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, | |||
383 | 383 | ||
384 | if (!locked) { | 384 | if (!locked) { |
385 | if (!hw->phy.ops.acquire) | 385 | if (!hw->phy.ops.acquire) |
386 | goto out; | 386 | return 0; |
387 | 387 | ||
388 | ret_val = hw->phy.ops.acquire(hw); | 388 | ret_val = hw->phy.ops.acquire(hw); |
389 | if (ret_val) | 389 | if (ret_val) |
390 | goto out; | 390 | return ret_val; |
391 | } | 391 | } |
392 | 392 | ||
393 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 393 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
394 | ret_val = e1000e_write_phy_reg_mdic(hw, | 394 | ret_val = e1000e_write_phy_reg_mdic(hw, |
395 | IGP01E1000_PHY_PAGE_SELECT, | 395 | IGP01E1000_PHY_PAGE_SELECT, |
396 | (u16)offset); | 396 | (u16)offset); |
397 | if (ret_val) | 397 | if (!ret_val) |
398 | goto release; | 398 | ret_val = e1000e_read_phy_reg_mdic(hw, |
399 | } | 399 | MAX_PHY_REG_ADDRESS & offset, |
400 | 400 | data); | |
401 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | ||
402 | data); | ||
403 | |||
404 | release: | ||
405 | if (!locked) | 401 | if (!locked) |
406 | hw->phy.ops.release(hw); | 402 | hw->phy.ops.release(hw); |
407 | out: | 403 | |
408 | return ret_val; | 404 | return ret_val; |
409 | } | 405 | } |
410 | 406 | ||
@@ -454,29 +450,24 @@ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, | |||
454 | 450 | ||
455 | if (!locked) { | 451 | if (!locked) { |
456 | if (!hw->phy.ops.acquire) | 452 | if (!hw->phy.ops.acquire) |
457 | goto out; | 453 | return 0; |
458 | 454 | ||
459 | ret_val = hw->phy.ops.acquire(hw); | 455 | ret_val = hw->phy.ops.acquire(hw); |
460 | if (ret_val) | 456 | if (ret_val) |
461 | goto out; | 457 | return ret_val; |
462 | } | 458 | } |
463 | 459 | ||
464 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 460 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
465 | ret_val = e1000e_write_phy_reg_mdic(hw, | 461 | ret_val = e1000e_write_phy_reg_mdic(hw, |
466 | IGP01E1000_PHY_PAGE_SELECT, | 462 | IGP01E1000_PHY_PAGE_SELECT, |
467 | (u16)offset); | 463 | (u16)offset); |
468 | if (ret_val) | 464 | if (!ret_val) |
469 | goto release; | 465 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & |
470 | } | 466 | offset, |
471 | 467 | data); | |
472 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | ||
473 | data); | ||
474 | |||
475 | release: | ||
476 | if (!locked) | 468 | if (!locked) |
477 | hw->phy.ops.release(hw); | 469 | hw->phy.ops.release(hw); |
478 | 470 | ||
479 | out: | ||
480 | return ret_val; | 471 | return ret_val; |
481 | } | 472 | } |
482 | 473 | ||
@@ -523,15 +514,16 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, | |||
523 | bool locked) | 514 | bool locked) |
524 | { | 515 | { |
525 | u32 kmrnctrlsta; | 516 | u32 kmrnctrlsta; |
526 | s32 ret_val = 0; | ||
527 | 517 | ||
528 | if (!locked) { | 518 | if (!locked) { |
519 | s32 ret_val = 0; | ||
520 | |||
529 | if (!hw->phy.ops.acquire) | 521 | if (!hw->phy.ops.acquire) |
530 | goto out; | 522 | return 0; |
531 | 523 | ||
532 | ret_val = hw->phy.ops.acquire(hw); | 524 | ret_val = hw->phy.ops.acquire(hw); |
533 | if (ret_val) | 525 | if (ret_val) |
534 | goto out; | 526 | return ret_val; |
535 | } | 527 | } |
536 | 528 | ||
537 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | 529 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
@@ -547,8 +539,7 @@ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, | |||
547 | if (!locked) | 539 | if (!locked) |
548 | hw->phy.ops.release(hw); | 540 | hw->phy.ops.release(hw); |
549 | 541 | ||
550 | out: | 542 | return 0; |
551 | return ret_val; | ||
552 | } | 543 | } |
553 | 544 | ||
554 | /** | 545 | /** |
@@ -596,15 +587,16 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, | |||
596 | bool locked) | 587 | bool locked) |
597 | { | 588 | { |
598 | u32 kmrnctrlsta; | 589 | u32 kmrnctrlsta; |
599 | s32 ret_val = 0; | ||
600 | 590 | ||
601 | if (!locked) { | 591 | if (!locked) { |
592 | s32 ret_val = 0; | ||
593 | |||
602 | if (!hw->phy.ops.acquire) | 594 | if (!hw->phy.ops.acquire) |
603 | goto out; | 595 | return 0; |
604 | 596 | ||
605 | ret_val = hw->phy.ops.acquire(hw); | 597 | ret_val = hw->phy.ops.acquire(hw); |
606 | if (ret_val) | 598 | if (ret_val) |
607 | goto out; | 599 | return ret_val; |
608 | } | 600 | } |
609 | 601 | ||
610 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | 602 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & |
@@ -617,8 +609,7 @@ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, | |||
617 | if (!locked) | 609 | if (!locked) |
618 | hw->phy.ops.release(hw); | 610 | hw->phy.ops.release(hw); |
619 | 611 | ||
620 | out: | 612 | return 0; |
621 | return ret_val; | ||
622 | } | 613 | } |
623 | 614 | ||
624 | /** | 615 | /** |
@@ -663,17 +654,14 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |||
663 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ | 654 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
664 | ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); | 655 | ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
665 | if (ret_val) | 656 | if (ret_val) |
666 | goto out; | 657 | return ret_val; |
667 | 658 | ||
668 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; | 659 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; |
669 | 660 | ||
670 | /* Enable downshift */ | 661 | /* Enable downshift */ |
671 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | 662 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; |
672 | 663 | ||
673 | ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); | 664 | return e1e_wphy(hw, I82577_CFG_REG, phy_data); |
674 | |||
675 | out: | ||
676 | return ret_val; | ||
677 | } | 665 | } |
678 | 666 | ||
679 | /** | 667 | /** |
@@ -1397,25 +1385,25 @@ s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) | |||
1397 | 1385 | ||
1398 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | 1386 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); |
1399 | if (ret_val) | 1387 | if (ret_val) |
1400 | goto out; | 1388 | return ret_val; |
1401 | 1389 | ||
1402 | e1000e_phy_force_speed_duplex_setup(hw, &data); | 1390 | e1000e_phy_force_speed_duplex_setup(hw, &data); |
1403 | 1391 | ||
1404 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | 1392 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); |
1405 | if (ret_val) | 1393 | if (ret_val) |
1406 | goto out; | 1394 | return ret_val; |
1407 | 1395 | ||
1408 | /* Disable MDI-X support for 10/100 */ | 1396 | /* Disable MDI-X support for 10/100 */ |
1409 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | 1397 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
1410 | if (ret_val) | 1398 | if (ret_val) |
1411 | goto out; | 1399 | return ret_val; |
1412 | 1400 | ||
1413 | data &= ~IFE_PMC_AUTO_MDIX; | 1401 | data &= ~IFE_PMC_AUTO_MDIX; |
1414 | data &= ~IFE_PMC_FORCE_MDIX; | 1402 | data &= ~IFE_PMC_FORCE_MDIX; |
1415 | 1403 | ||
1416 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | 1404 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); |
1417 | if (ret_val) | 1405 | if (ret_val) |
1418 | goto out; | 1406 | return ret_val; |
1419 | 1407 | ||
1420 | e_dbg("IFE PMC: %X\n", data); | 1408 | e_dbg("IFE PMC: %X\n", data); |
1421 | 1409 | ||
@@ -1429,7 +1417,7 @@ s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) | |||
1429 | 100000, | 1417 | 100000, |
1430 | &link); | 1418 | &link); |
1431 | if (ret_val) | 1419 | if (ret_val) |
1432 | goto out; | 1420 | return ret_val; |
1433 | 1421 | ||
1434 | if (!link) | 1422 | if (!link) |
1435 | e_dbg("Link taking longer than expected.\n"); | 1423 | e_dbg("Link taking longer than expected.\n"); |
@@ -1440,11 +1428,10 @@ s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) | |||
1440 | 100000, | 1428 | 100000, |
1441 | &link); | 1429 | &link); |
1442 | if (ret_val) | 1430 | if (ret_val) |
1443 | goto out; | 1431 | return ret_val; |
1444 | } | 1432 | } |
1445 | 1433 | ||
1446 | out: | 1434 | return 0; |
1447 | return ret_val; | ||
1448 | } | 1435 | } |
1449 | 1436 | ||
1450 | /** | 1437 | /** |
@@ -1829,22 +1816,20 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |||
1829 | 1816 | ||
1830 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | 1817 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
1831 | if (ret_val) | 1818 | if (ret_val) |
1832 | goto out; | 1819 | return ret_val; |
1833 | 1820 | ||
1834 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | 1821 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
1835 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | 1822 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
1836 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { | 1823 | |
1837 | ret_val = -E1000_ERR_PHY; | 1824 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) |
1838 | goto out; | 1825 | return -E1000_ERR_PHY; |
1839 | } | ||
1840 | 1826 | ||
1841 | phy->min_cable_length = e1000_m88_cable_length_table[index]; | 1827 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
1842 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; | 1828 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
1843 | 1829 | ||
1844 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | 1830 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; |
1845 | 1831 | ||
1846 | out: | 1832 | return 0; |
1847 | return ret_val; | ||
1848 | } | 1833 | } |
1849 | 1834 | ||
1850 | /** | 1835 | /** |
@@ -2069,24 +2054,23 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw) | |||
2069 | 2054 | ||
2070 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | 2055 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
2071 | if (ret_val) | 2056 | if (ret_val) |
2072 | goto out; | 2057 | return ret_val; |
2073 | 2058 | ||
2074 | if (!link) { | 2059 | if (!link) { |
2075 | e_dbg("Phy info is only valid if link is up\n"); | 2060 | e_dbg("Phy info is only valid if link is up\n"); |
2076 | ret_val = -E1000_ERR_CONFIG; | 2061 | return -E1000_ERR_CONFIG; |
2077 | goto out; | ||
2078 | } | 2062 | } |
2079 | 2063 | ||
2080 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | 2064 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); |
2081 | if (ret_val) | 2065 | if (ret_val) |
2082 | goto out; | 2066 | return ret_val; |
2083 | phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) | 2067 | phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) |
2084 | ? false : true; | 2068 | ? false : true; |
2085 | 2069 | ||
2086 | if (phy->polarity_correction) { | 2070 | if (phy->polarity_correction) { |
2087 | ret_val = e1000_check_polarity_ife(hw); | 2071 | ret_val = e1000_check_polarity_ife(hw); |
2088 | if (ret_val) | 2072 | if (ret_val) |
2089 | goto out; | 2073 | return ret_val; |
2090 | } else { | 2074 | } else { |
2091 | /* Polarity is forced */ | 2075 | /* Polarity is forced */ |
2092 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | 2076 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) |
@@ -2096,7 +2080,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw) | |||
2096 | 2080 | ||
2097 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | 2081 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); |
2098 | if (ret_val) | 2082 | if (ret_val) |
2099 | goto out; | 2083 | return ret_val; |
2100 | 2084 | ||
2101 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; | 2085 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; |
2102 | 2086 | ||
@@ -2105,8 +2089,7 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw) | |||
2105 | phy->local_rx = e1000_1000t_rx_status_undefined; | 2089 | phy->local_rx = e1000_1000t_rx_status_undefined; |
2106 | phy->remote_rx = e1000_1000t_rx_status_undefined; | 2090 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
2107 | 2091 | ||
2108 | out: | 2092 | return 0; |
2109 | return ret_val; | ||
2110 | } | 2093 | } |
2111 | 2094 | ||
2112 | /** | 2095 | /** |
@@ -2365,7 +2348,6 @@ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) | |||
2365 | **/ | 2348 | **/ |
2366 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) | 2349 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) |
2367 | { | 2350 | { |
2368 | s32 ret_val = -E1000_ERR_PHY_TYPE; | ||
2369 | u32 phy_addr = 0; | 2351 | u32 phy_addr = 0; |
2370 | u32 i; | 2352 | u32 i; |
2371 | enum e1000_phy_type phy_type = e1000_phy_unknown; | 2353 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
@@ -2384,17 +2366,15 @@ s32 e1000e_determine_phy_address(struct e1000_hw *hw) | |||
2384 | * If phy_type is valid, break - we found our | 2366 | * If phy_type is valid, break - we found our |
2385 | * PHY address | 2367 | * PHY address |
2386 | */ | 2368 | */ |
2387 | if (phy_type != e1000_phy_unknown) { | 2369 | if (phy_type != e1000_phy_unknown) |
2388 | ret_val = 0; | 2370 | return 0; |
2389 | goto out; | 2371 | |
2390 | } | ||
2391 | usleep_range(1000, 2000); | 2372 | usleep_range(1000, 2000); |
2392 | i++; | 2373 | i++; |
2393 | } while (i < 10); | 2374 | } while (i < 10); |
2394 | } | 2375 | } |
2395 | 2376 | ||
2396 | out: | 2377 | return -E1000_ERR_PHY_TYPE; |
2397 | return ret_val; | ||
2398 | } | 2378 | } |
2399 | 2379 | ||
2400 | /** | 2380 | /** |
@@ -2638,14 +2618,14 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) | |||
2638 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | 2618 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
2639 | if (ret_val) { | 2619 | if (ret_val) { |
2640 | e_dbg("Could not set Port Control page\n"); | 2620 | e_dbg("Could not set Port Control page\n"); |
2641 | goto out; | 2621 | return ret_val; |
2642 | } | 2622 | } |
2643 | 2623 | ||
2644 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | 2624 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
2645 | if (ret_val) { | 2625 | if (ret_val) { |
2646 | e_dbg("Could not read PHY register %d.%d\n", | 2626 | e_dbg("Could not read PHY register %d.%d\n", |
2647 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | 2627 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
2648 | goto out; | 2628 | return ret_val; |
2649 | } | 2629 | } |
2650 | 2630 | ||
2651 | /* | 2631 | /* |
@@ -2660,15 +2640,14 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) | |||
2660 | if (ret_val) { | 2640 | if (ret_val) { |
2661 | e_dbg("Could not write PHY register %d.%d\n", | 2641 | e_dbg("Could not write PHY register %d.%d\n", |
2662 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | 2642 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
2663 | goto out; | 2643 | return ret_val; |
2664 | } | 2644 | } |
2665 | 2645 | ||
2666 | /* Select Host Wakeup Registers page */ | 2646 | /* |
2667 | ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); | 2647 | * Select Host Wakeup Registers page - caller now able to write |
2668 | 2648 | * registers on the Wakeup registers page | |
2669 | /* caller now able to write registers on the Wakeup registers page */ | 2649 | */ |
2670 | out: | 2650 | return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); |
2671 | return ret_val; | ||
2672 | } | 2651 | } |
2673 | 2652 | ||
2674 | /** | 2653 | /** |
@@ -2690,7 +2669,7 @@ s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) | |||
2690 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | 2669 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); |
2691 | if (ret_val) { | 2670 | if (ret_val) { |
2692 | e_dbg("Could not set Port Control page\n"); | 2671 | e_dbg("Could not set Port Control page\n"); |
2693 | goto out; | 2672 | return ret_val; |
2694 | } | 2673 | } |
2695 | 2674 | ||
2696 | /* Restore 769.17 to its original value */ | 2675 | /* Restore 769.17 to its original value */ |
@@ -2698,7 +2677,7 @@ s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) | |||
2698 | if (ret_val) | 2677 | if (ret_val) |
2699 | e_dbg("Could not restore PHY register %d.%d\n", | 2678 | e_dbg("Could not restore PHY register %d.%d\n", |
2700 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | 2679 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); |
2701 | out: | 2680 | |
2702 | return ret_val; | 2681 | return ret_val; |
2703 | } | 2682 | } |
2704 | 2683 | ||
@@ -2746,7 +2725,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |||
2746 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); | 2725 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
2747 | if (ret_val) { | 2726 | if (ret_val) { |
2748 | e_dbg("Could not enable PHY wakeup reg access\n"); | 2727 | e_dbg("Could not enable PHY wakeup reg access\n"); |
2749 | goto out; | 2728 | return ret_val; |
2750 | } | 2729 | } |
2751 | } | 2730 | } |
2752 | 2731 | ||
@@ -2756,7 +2735,7 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |||
2756 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); | 2735 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
2757 | if (ret_val) { | 2736 | if (ret_val) { |
2758 | e_dbg("Could not write address opcode to page %d\n", page); | 2737 | e_dbg("Could not write address opcode to page %d\n", page); |
2759 | goto out; | 2738 | return ret_val; |
2760 | } | 2739 | } |
2761 | 2740 | ||
2762 | if (read) { | 2741 | if (read) { |
@@ -2771,13 +2750,12 @@ static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |||
2771 | 2750 | ||
2772 | if (ret_val) { | 2751 | if (ret_val) { |
2773 | e_dbg("Could not access PHY reg %d.%d\n", page, reg); | 2752 | e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
2774 | goto out; | 2753 | return ret_val; |
2775 | } | 2754 | } |
2776 | 2755 | ||
2777 | if (!page_set) | 2756 | if (!page_set) |
2778 | ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); | 2757 | ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); |
2779 | 2758 | ||
2780 | out: | ||
2781 | return ret_val; | 2759 | return ret_val; |
2782 | } | 2760 | } |
2783 | 2761 | ||
@@ -3133,7 +3111,7 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |||
3133 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); | 3111 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); |
3134 | if (ret_val) { | 3112 | if (ret_val) { |
3135 | e_dbg("Could not write the Address Offset port register\n"); | 3113 | e_dbg("Could not write the Address Offset port register\n"); |
3136 | goto out; | 3114 | return ret_val; |
3137 | } | 3115 | } |
3138 | 3116 | ||
3139 | /* Read or write the data value next */ | 3117 | /* Read or write the data value next */ |
@@ -3142,12 +3120,9 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |||
3142 | else | 3120 | else |
3143 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); | 3121 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); |
3144 | 3122 | ||
3145 | if (ret_val) { | 3123 | if (ret_val) |
3146 | e_dbg("Could not access the Data port register\n"); | 3124 | e_dbg("Could not access the Data port register\n"); |
3147 | goto out; | ||
3148 | } | ||
3149 | 3125 | ||
3150 | out: | ||
3151 | return ret_val; | 3126 | return ret_val; |
3152 | } | 3127 | } |
3153 | 3128 | ||
@@ -3168,17 +3143,17 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |||
3168 | u16 data; | 3143 | u16 data; |
3169 | 3144 | ||
3170 | if (hw->phy.type != e1000_phy_82578) | 3145 | if (hw->phy.type != e1000_phy_82578) |
3171 | goto out; | 3146 | return 0; |
3172 | 3147 | ||
3173 | /* Do not apply workaround if in PHY loopback bit 14 set */ | 3148 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
3174 | e1e_rphy(hw, PHY_CONTROL, &data); | 3149 | e1e_rphy(hw, PHY_CONTROL, &data); |
3175 | if (data & PHY_CONTROL_LB) | 3150 | if (data & PHY_CONTROL_LB) |
3176 | goto out; | 3151 | return 0; |
3177 | 3152 | ||
3178 | /* check if link is up and at 1Gbps */ | 3153 | /* check if link is up and at 1Gbps */ |
3179 | ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); | 3154 | ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
3180 | if (ret_val) | 3155 | if (ret_val) |
3181 | goto out; | 3156 | return ret_val; |
3182 | 3157 | ||
3183 | data &= BM_CS_STATUS_LINK_UP | | 3158 | data &= BM_CS_STATUS_LINK_UP | |
3184 | BM_CS_STATUS_RESOLVED | | 3159 | BM_CS_STATUS_RESOLVED | |
@@ -3187,7 +3162,7 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |||
3187 | if (data != (BM_CS_STATUS_LINK_UP | | 3162 | if (data != (BM_CS_STATUS_LINK_UP | |
3188 | BM_CS_STATUS_RESOLVED | | 3163 | BM_CS_STATUS_RESOLVED | |
3189 | BM_CS_STATUS_SPEED_1000)) | 3164 | BM_CS_STATUS_SPEED_1000)) |
3190 | goto out; | 3165 | return 0; |
3191 | 3166 | ||
3192 | mdelay(200); | 3167 | mdelay(200); |
3193 | 3168 | ||
@@ -3195,12 +3170,9 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |||
3195 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | | 3170 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC | |
3196 | HV_MUX_DATA_CTRL_FORCE_SPEED); | 3171 | HV_MUX_DATA_CTRL_FORCE_SPEED); |
3197 | if (ret_val) | 3172 | if (ret_val) |
3198 | goto out; | 3173 | return ret_val; |
3199 | |||
3200 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); | ||
3201 | 3174 | ||
3202 | out: | 3175 | return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
3203 | return ret_val; | ||
3204 | } | 3176 | } |
3205 | 3177 | ||
3206 | /** | 3178 | /** |
@@ -3242,13 +3214,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |||
3242 | 3214 | ||
3243 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | 3215 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); |
3244 | if (ret_val) | 3216 | if (ret_val) |
3245 | goto out; | 3217 | return ret_val; |
3246 | 3218 | ||
3247 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | 3219 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); |
3248 | 3220 | ||
3249 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | 3221 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
3250 | if (ret_val) | 3222 | if (ret_val) |
3251 | goto out; | 3223 | return ret_val; |
3252 | 3224 | ||
3253 | udelay(1); | 3225 | udelay(1); |
3254 | 3226 | ||
@@ -3260,7 +3232,7 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |||
3260 | 100000, | 3232 | 100000, |
3261 | &link); | 3233 | &link); |
3262 | if (ret_val) | 3234 | if (ret_val) |
3263 | goto out; | 3235 | return ret_val; |
3264 | 3236 | ||
3265 | if (!link) | 3237 | if (!link) |
3266 | e_dbg("Link taking longer than expected.\n"); | 3238 | e_dbg("Link taking longer than expected.\n"); |
@@ -3270,11 +3242,8 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |||
3270 | PHY_FORCE_LIMIT, | 3242 | PHY_FORCE_LIMIT, |
3271 | 100000, | 3243 | 100000, |
3272 | &link); | 3244 | &link); |
3273 | if (ret_val) | ||
3274 | goto out; | ||
3275 | } | 3245 | } |
3276 | 3246 | ||
3277 | out: | ||
3278 | return ret_val; | 3247 | return ret_val; |
3279 | } | 3248 | } |
3280 | 3249 | ||
@@ -3296,23 +3265,22 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |||
3296 | 3265 | ||
3297 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | 3266 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
3298 | if (ret_val) | 3267 | if (ret_val) |
3299 | goto out; | 3268 | return ret_val; |
3300 | 3269 | ||
3301 | if (!link) { | 3270 | if (!link) { |
3302 | e_dbg("Phy info is only valid if link is up\n"); | 3271 | e_dbg("Phy info is only valid if link is up\n"); |
3303 | ret_val = -E1000_ERR_CONFIG; | 3272 | return -E1000_ERR_CONFIG; |
3304 | goto out; | ||
3305 | } | 3273 | } |
3306 | 3274 | ||
3307 | phy->polarity_correction = true; | 3275 | phy->polarity_correction = true; |
3308 | 3276 | ||
3309 | ret_val = e1000_check_polarity_82577(hw); | 3277 | ret_val = e1000_check_polarity_82577(hw); |
3310 | if (ret_val) | 3278 | if (ret_val) |
3311 | goto out; | 3279 | return ret_val; |
3312 | 3280 | ||
3313 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); | 3281 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
3314 | if (ret_val) | 3282 | if (ret_val) |
3315 | goto out; | 3283 | return ret_val; |
3316 | 3284 | ||
3317 | phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; | 3285 | phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; |
3318 | 3286 | ||
@@ -3320,11 +3288,11 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |||
3320 | I82577_PHY_STATUS2_SPEED_1000MBPS) { | 3288 | I82577_PHY_STATUS2_SPEED_1000MBPS) { |
3321 | ret_val = hw->phy.ops.get_cable_length(hw); | 3289 | ret_val = hw->phy.ops.get_cable_length(hw); |
3322 | if (ret_val) | 3290 | if (ret_val) |
3323 | goto out; | 3291 | return ret_val; |
3324 | 3292 | ||
3325 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); | 3293 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); |
3326 | if (ret_val) | 3294 | if (ret_val) |
3327 | goto out; | 3295 | return ret_val; |
3328 | 3296 | ||
3329 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | 3297 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) |
3330 | ? e1000_1000t_rx_status_ok | 3298 | ? e1000_1000t_rx_status_ok |
@@ -3339,8 +3307,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |||
3339 | phy->remote_rx = e1000_1000t_rx_status_undefined; | 3307 | phy->remote_rx = e1000_1000t_rx_status_undefined; |
3340 | } | 3308 | } |
3341 | 3309 | ||
3342 | out: | 3310 | return 0; |
3343 | return ret_val; | ||
3344 | } | 3311 | } |
3345 | 3312 | ||
3346 | /** | 3313 | /** |
@@ -3358,7 +3325,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |||
3358 | 3325 | ||
3359 | ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); | 3326 | ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
3360 | if (ret_val) | 3327 | if (ret_val) |
3361 | goto out; | 3328 | return ret_val; |
3362 | 3329 | ||
3363 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> | 3330 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> |
3364 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; | 3331 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; |
@@ -3368,6 +3335,5 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |||
3368 | 3335 | ||
3369 | phy->cable_length = length; | 3336 | phy->cable_length = length; |
3370 | 3337 | ||
3371 | out: | 3338 | return 0; |
3372 | return ret_val; | ||
3373 | } | 3339 | } |