diff options
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge-core.c | 191 | ||||
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge-regs.h | 62 | ||||
-rw-r--r-- | drivers/media/dvb/ddbridge/ddbridge.h | 8 |
3 files changed, 144 insertions, 117 deletions
diff --git a/drivers/media/dvb/ddbridge/ddbridge-core.c b/drivers/media/dvb/ddbridge/ddbridge-core.c index ba9974bc154e..81634f137bb3 100644 --- a/drivers/media/dvb/ddbridge/ddbridge-core.c +++ b/drivers/media/dvb/ddbridge/ddbridge-core.c | |||
@@ -55,7 +55,7 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); | |||
55 | static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) | 55 | static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) |
56 | { | 56 | { |
57 | struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, | 57 | struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, |
58 | .buf = val, .len = 1 }}; | 58 | .buf = val, .len = 1 } }; |
59 | return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; | 59 | return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; |
60 | } | 60 | } |
61 | 61 | ||
@@ -64,7 +64,7 @@ static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) | |||
64 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, | 64 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, |
65 | .buf = ®, .len = 1 }, | 65 | .buf = ®, .len = 1 }, |
66 | {.addr = adr, .flags = I2C_M_RD, | 66 | {.addr = adr, .flags = I2C_M_RD, |
67 | .buf = val, .len = 1 }}; | 67 | .buf = val, .len = 1 } }; |
68 | return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; | 68 | return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; |
69 | } | 69 | } |
70 | 70 | ||
@@ -75,7 +75,7 @@ static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, | |||
75 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, | 75 | struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, |
76 | .buf = msg, .len = 2}, | 76 | .buf = msg, .len = 2}, |
77 | {.addr = adr, .flags = I2C_M_RD, | 77 | {.addr = adr, .flags = I2C_M_RD, |
78 | .buf = val, .len = 1}}; | 78 | .buf = val, .len = 1} }; |
79 | return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; | 79 | return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; |
80 | } | 80 | } |
81 | 81 | ||
@@ -89,15 +89,15 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) | |||
89 | ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); | 89 | ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); |
90 | stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); | 90 | stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); |
91 | if (stat <= 0) { | 91 | if (stat <= 0) { |
92 | printk("I2C timeout\n"); | 92 | printk(KERN_ERR "I2C timeout\n"); |
93 | { /* MSI debugging*/ | 93 | { /* MSI debugging*/ |
94 | u32 istat = ddbreadl(INTERRUPT_STATUS); | 94 | u32 istat = ddbreadl(INTERRUPT_STATUS); |
95 | printk("IRS %08x\n", istat); | 95 | printk(KERN_ERR "IRS %08x\n", istat); |
96 | ddbwritel(istat, INTERRUPT_ACK); | 96 | ddbwritel(istat, INTERRUPT_ACK); |
97 | } | 97 | } |
98 | return -EIO; | 98 | return -EIO; |
99 | } | 99 | } |
100 | val=ddbreadl(i2c->regs+I2C_COMMAND); | 100 | val = ddbreadl(i2c->regs+I2C_COMMAND); |
101 | if (val & 0x70000) | 101 | if (val & 0x70000) |
102 | return -EIO; | 102 | return -EIO; |
103 | return 0; | 103 | return 0; |
@@ -108,7 +108,7 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, | |||
108 | { | 108 | { |
109 | struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); | 109 | struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); |
110 | struct ddb *dev = i2c->dev; | 110 | struct ddb *dev = i2c->dev; |
111 | u8 addr=0; | 111 | u8 addr = 0; |
112 | 112 | ||
113 | if (num) | 113 | if (num) |
114 | addr = msg[0].addr; | 114 | addr = msg[0].addr; |
@@ -116,7 +116,7 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, | |||
116 | if (num == 2 && msg[1].flags & I2C_M_RD && | 116 | if (num == 2 && msg[1].flags & I2C_M_RD && |
117 | !(msg[0].flags & I2C_M_RD)) { | 117 | !(msg[0].flags & I2C_M_RD)) { |
118 | memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, | 118 | memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, |
119 | msg[0].buf,msg[0].len); | 119 | msg[0].buf, msg[0].len); |
120 | ddbwritel(msg[0].len|(msg[1].len << 16), | 120 | ddbwritel(msg[0].len|(msg[1].len << 16), |
121 | i2c->regs+I2C_TASKLENGTH); | 121 | i2c->regs+I2C_TASKLENGTH); |
122 | if (!ddb_i2c_cmd(i2c, addr, 1)) { | 122 | if (!ddb_i2c_cmd(i2c, addr, 1)) { |
@@ -128,7 +128,7 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, | |||
128 | } | 128 | } |
129 | 129 | ||
130 | if (num == 1 && !(msg[0].flags & I2C_M_RD)) { | 130 | if (num == 1 && !(msg[0].flags & I2C_M_RD)) { |
131 | ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf,msg[0].buf, msg[0].len); | 131 | ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); |
132 | ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); | 132 | ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); |
133 | if (!ddb_i2c_cmd(i2c, addr, 2)) | 133 | if (!ddb_i2c_cmd(i2c, addr, 2)) |
134 | return num; | 134 | return num; |
@@ -217,6 +217,7 @@ static int ddb_i2c_init(struct ddb *dev) | |||
217 | /******************************************************************************/ | 217 | /******************************************************************************/ |
218 | /******************************************************************************/ | 218 | /******************************************************************************/ |
219 | 219 | ||
220 | #if 0 | ||
220 | static void set_table(struct ddb *dev, u32 off, | 221 | static void set_table(struct ddb *dev, u32 off, |
221 | dma_addr_t *pbuf, u32 num) | 222 | dma_addr_t *pbuf, u32 num) |
222 | { | 223 | { |
@@ -230,6 +231,7 @@ static void set_table(struct ddb *dev, u32 off, | |||
230 | ddbwritel(mem >> 32, base + i * 8 + 4); | 231 | ddbwritel(mem >> 32, base + i * 8 + 4); |
231 | } | 232 | } |
232 | } | 233 | } |
234 | #endif | ||
233 | 235 | ||
234 | static void ddb_address_table(struct ddb *dev) | 236 | static void ddb_address_table(struct ddb *dev) |
235 | { | 237 | { |
@@ -401,7 +403,7 @@ static void ddb_output_start(struct ddb_output *output) | |||
401 | 403 | ||
402 | ddbwritel(1, DMA_BASE_READ); | 404 | ddbwritel(1, DMA_BASE_READ); |
403 | ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); | 405 | ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); |
404 | //ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); | 406 | /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ |
405 | ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); | 407 | ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); |
406 | output->running = 1; | 408 | output->running = 1; |
407 | spin_unlock_irq(&output->lock); | 409 | spin_unlock_irq(&output->lock); |
@@ -438,7 +440,7 @@ static u32 ddb_output_free(struct ddb_output *output) | |||
438 | return 0; | 440 | return 0; |
439 | } | 441 | } |
440 | 442 | ||
441 | static ssize_t ddb_output_write(struct ddb_output* output, | 443 | static ssize_t ddb_output_write(struct ddb_output *output, |
442 | const u8 *buf, size_t count) | 444 | const u8 *buf, size_t count) |
443 | { | 445 | { |
444 | struct ddb *dev = output->port->dev; | 446 | struct ddb *dev = output->port->dev; |
@@ -452,9 +454,9 @@ static ssize_t ddb_output_write(struct ddb_output* output, | |||
452 | len = output->dma_buf_size - output->coff; | 454 | len = output->dma_buf_size - output->coff; |
453 | if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && | 455 | if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && |
454 | (off == 0)) { | 456 | (off == 0)) { |
455 | if (len<=188) | 457 | if (len <= 188) |
456 | break; | 458 | break; |
457 | len-=188; | 459 | len -= 188; |
458 | } | 460 | } |
459 | if (output->cbuf == idx) { | 461 | if (output->cbuf == idx) { |
460 | if (off > output->coff) { | 462 | if (off > output->coff) { |
@@ -496,7 +498,7 @@ static u32 ddb_input_avail(struct ddb_input *input) | |||
496 | off = (stat & 0x7ff) << 7; | 498 | off = (stat & 0x7ff) << 7; |
497 | 499 | ||
498 | if (ctrl & 4) { | 500 | if (ctrl & 4) { |
499 | printk("IA %d %d %08x\n", idx, off, ctrl); | 501 | printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); |
500 | ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); | 502 | ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); |
501 | return 0; | 503 | return 0; |
502 | } | 504 | } |
@@ -545,7 +547,7 @@ static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) | |||
545 | int i; | 547 | int i; |
546 | 548 | ||
547 | for (i = 0; i < dev->info->port_num * 2; i++) { | 549 | for (i = 0; i < dev->info->port_num * 2; i++) { |
548 | if (dev->input[i].fe==fe) | 550 | if (dev->input[i].fe == fe) |
549 | return &dev->input[i]; | 551 | return &dev->input[i]; |
550 | } | 552 | } |
551 | return NULL; | 553 | return NULL; |
@@ -573,11 +575,11 @@ static int demod_attach_drxk(struct ddb_input *input) | |||
573 | struct i2c_adapter *i2c = &input->port->i2c->adap; | 575 | struct i2c_adapter *i2c = &input->port->i2c->adap; |
574 | struct dvb_frontend *fe; | 576 | struct dvb_frontend *fe; |
575 | 577 | ||
576 | fe=input->fe = dvb_attach(drxk_attach, | 578 | fe = input->fe = dvb_attach(drxk_attach, |
577 | i2c, 0x29 + (input->nr&1), | 579 | i2c, 0x29 + (input->nr&1), |
578 | &input->fe2); | 580 | &input->fe2); |
579 | if (!input->fe) { | 581 | if (!input->fe) { |
580 | printk("No DRXK found!\n"); | 582 | printk(KERN_ERR "No DRXK found!\n"); |
581 | return -ENODEV; | 583 | return -ENODEV; |
582 | } | 584 | } |
583 | fe->sec_priv = input; | 585 | fe->sec_priv = input; |
@@ -595,7 +597,7 @@ static int tuner_attach_tda18271(struct ddb_input *input) | |||
595 | input->fe->ops.i2c_gate_ctrl(input->fe, 1); | 597 | input->fe->ops.i2c_gate_ctrl(input->fe, 1); |
596 | fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); | 598 | fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); |
597 | if (!fe) { | 599 | if (!fe) { |
598 | printk("No TDA18271 found!\n"); | 600 | printk(KERN_ERR "No TDA18271 found!\n"); |
599 | return -ENODEV; | 601 | return -ENODEV; |
600 | } | 602 | } |
601 | if (input->fe->ops.i2c_gate_ctrl) | 603 | if (input->fe->ops.i2c_gate_ctrl) |
@@ -662,17 +664,17 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) | |||
662 | struct i2c_adapter *i2c = &input->port->i2c->adap; | 664 | struct i2c_adapter *i2c = &input->port->i2c->adap; |
663 | struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; | 665 | struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; |
664 | 666 | ||
665 | input->fe=dvb_attach(stv090x_attach, feconf, i2c, | 667 | input->fe = dvb_attach(stv090x_attach, feconf, i2c, |
666 | (input->nr & 1) ? STV090x_DEMODULATOR_1 | 668 | (input->nr & 1) ? STV090x_DEMODULATOR_1 |
667 | : STV090x_DEMODULATOR_0); | 669 | : STV090x_DEMODULATOR_0); |
668 | if (!input->fe) { | 670 | if (!input->fe) { |
669 | printk("No STV0900 found!\n"); | 671 | printk(KERN_ERR "No STV0900 found!\n"); |
670 | return -ENODEV; | 672 | return -ENODEV; |
671 | } | 673 | } |
672 | if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, | 674 | if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, |
673 | 0, (input->nr & 1) ? | 675 | 0, (input->nr & 1) ? |
674 | (0x09 - type) : (0x0b - type))) { | 676 | (0x09 - type) : (0x0b - type))) { |
675 | printk("No LNBH24 found!\n"); | 677 | printk(KERN_ERR "No LNBH24 found!\n"); |
676 | return -ENODEV; | 678 | return -ENODEV; |
677 | } | 679 | } |
678 | return 0; | 680 | return 0; |
@@ -688,10 +690,11 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) | |||
688 | 690 | ||
689 | ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); | 691 | ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); |
690 | if (!ctl) { | 692 | if (!ctl) { |
691 | printk("No STV6110X found!\n"); | 693 | printk(KERN_ERR "No STV6110X found!\n"); |
692 | return -ENODEV; | 694 | return -ENODEV; |
693 | } | 695 | } |
694 | printk("attach tuner input %d adr %02x\n", input->nr, tunerconf->addr); | 696 | printk(KERN_INFO "attach tuner input %d adr %02x\n", |
697 | input->nr, tunerconf->addr); | ||
695 | 698 | ||
696 | feconf->tuner_init = ctl->tuner_init; | 699 | feconf->tuner_init = ctl->tuner_init; |
697 | feconf->tuner_sleep = ctl->tuner_sleep; | 700 | feconf->tuner_sleep = ctl->tuner_sleep; |
@@ -813,11 +816,11 @@ static int dvb_input_attach(struct ddb_input *input) | |||
813 | struct dvb_adapter *adap = &input->adap; | 816 | struct dvb_adapter *adap = &input->adap; |
814 | struct dvb_demux *dvbdemux = &input->demux; | 817 | struct dvb_demux *dvbdemux = &input->demux; |
815 | 818 | ||
816 | ret=dvb_register_adapter(adap, "DDBridge",THIS_MODULE, | 819 | ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, |
817 | &input->port->dev->pdev->dev, | 820 | &input->port->dev->pdev->dev, |
818 | adapter_nr); | 821 | adapter_nr); |
819 | if (ret < 0) { | 822 | if (ret < 0) { |
820 | printk("ddbridge: Could not register adapter." | 823 | printk(KERN_ERR "ddbridge: Could not register adapter." |
821 | "Check if you enabled enough adapters in dvb-core!\n"); | 824 | "Check if you enabled enough adapters in dvb-core!\n"); |
822 | return ret; | 825 | return ret; |
823 | } | 826 | } |
@@ -876,7 +879,7 @@ static int dvb_input_attach(struct ddb_input *input) | |||
876 | if (input->fe2) { | 879 | if (input->fe2) { |
877 | if (dvb_register_frontend(adap, input->fe2) < 0) | 880 | if (dvb_register_frontend(adap, input->fe2) < 0) |
878 | return -ENODEV; | 881 | return -ENODEV; |
879 | input->fe2->tuner_priv=input->fe->tuner_priv; | 882 | input->fe2->tuner_priv = input->fe->tuner_priv; |
880 | memcpy(&input->fe2->ops.tuner_ops, | 883 | memcpy(&input->fe2->ops.tuner_ops, |
881 | &input->fe->ops.tuner_ops, | 884 | &input->fe->ops.tuner_ops, |
882 | sizeof(struct dvb_tuner_ops)); | 885 | sizeof(struct dvb_tuner_ops)); |
@@ -942,9 +945,11 @@ static ssize_t ts_read(struct file *file, char *buf, | |||
942 | 945 | ||
943 | static unsigned int ts_poll(struct file *file, poll_table *wait) | 946 | static unsigned int ts_poll(struct file *file, poll_table *wait) |
944 | { | 947 | { |
948 | /* | ||
945 | struct dvb_device *dvbdev = file->private_data; | 949 | struct dvb_device *dvbdev = file->private_data; |
946 | struct ddb_output *output = dvbdev->priv; | 950 | struct ddb_output *output = dvbdev->priv; |
947 | struct ddb_input *input = output->port->input[0]; | 951 | struct ddb_input *input = output->port->input[0]; |
952 | */ | ||
948 | unsigned int mask = 0; | 953 | unsigned int mask = 0; |
949 | 954 | ||
950 | #if 0 | 955 | #if 0 |
@@ -959,7 +964,7 @@ static unsigned int ts_poll(struct file *file, poll_table *wait) | |||
959 | return mask; | 964 | return mask; |
960 | } | 965 | } |
961 | 966 | ||
962 | static struct file_operations ci_fops = { | 967 | static const struct file_operations ci_fops = { |
963 | .owner = THIS_MODULE, | 968 | .owner = THIS_MODULE, |
964 | .read = ts_read, | 969 | .read = ts_read, |
965 | .write = ts_write, | 970 | .write = ts_write, |
@@ -995,7 +1000,7 @@ static void input_tasklet(unsigned long data) | |||
995 | 1000 | ||
996 | if (input->port->class == DDB_PORT_TUNER) { | 1001 | if (input->port->class == DDB_PORT_TUNER) { |
997 | if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) | 1002 | if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) |
998 | printk("Overflow input %d\n", input->nr); | 1003 | printk(KERN_ERR "Overflow input %d\n", input->nr); |
999 | while (input->cbuf != ((input->stat >> 11) & 0x1f) | 1004 | while (input->cbuf != ((input->stat >> 11) & 0x1f) |
1000 | || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { | 1005 | || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { |
1001 | dvb_dmx_swfilter_packets(&input->demux, | 1006 | dvb_dmx_swfilter_packets(&input->demux, |
@@ -1056,9 +1061,9 @@ static int ddb_ci_attach(struct ddb_port *port) | |||
1056 | ddb_output_start(port->output); | 1061 | ddb_output_start(port->output); |
1057 | dvb_ca_en50221_init(&port->output->adap, | 1062 | dvb_ca_en50221_init(&port->output->adap, |
1058 | port->en, 0, 1); | 1063 | port->en, 0, 1); |
1059 | ret=dvb_register_device(&port->output->adap, &port->output->dev, | 1064 | ret = dvb_register_device(&port->output->adap, &port->output->dev, |
1060 | &dvbdev_ci, (void *) port->output, | 1065 | &dvbdev_ci, (void *) port->output, |
1061 | DVB_DEVICE_SEC); | 1066 | DVB_DEVICE_SEC); |
1062 | return ret; | 1067 | return ret; |
1063 | } | 1068 | } |
1064 | 1069 | ||
@@ -1069,7 +1074,7 @@ static int ddb_port_attach(struct ddb_port *port) | |||
1069 | switch (port->class) { | 1074 | switch (port->class) { |
1070 | case DDB_PORT_TUNER: | 1075 | case DDB_PORT_TUNER: |
1071 | ret = dvb_input_attach(port->input[0]); | 1076 | ret = dvb_input_attach(port->input[0]); |
1072 | if (ret<0) | 1077 | if (ret < 0) |
1073 | break; | 1078 | break; |
1074 | ret = dvb_input_attach(port->input[1]); | 1079 | ret = dvb_input_attach(port->input[1]); |
1075 | break; | 1080 | break; |
@@ -1080,7 +1085,7 @@ static int ddb_port_attach(struct ddb_port *port) | |||
1080 | break; | 1085 | break; |
1081 | } | 1086 | } |
1082 | if (ret < 0) | 1087 | if (ret < 0) |
1083 | printk("port_attach on port %d failed\n", port->nr); | 1088 | printk(KERN_ERR "port_attach on port %d failed\n", port->nr); |
1084 | return ret; | 1089 | return ret; |
1085 | } | 1090 | } |
1086 | 1091 | ||
@@ -1132,7 +1137,7 @@ static void ddb_ports_detach(struct ddb *dev) | |||
1132 | static int port_has_ci(struct ddb_port *port) | 1137 | static int port_has_ci(struct ddb_port *port) |
1133 | { | 1138 | { |
1134 | u8 val; | 1139 | u8 val; |
1135 | return (i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1); | 1140 | return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; |
1136 | } | 1141 | } |
1137 | 1142 | ||
1138 | static int port_has_stv0900(struct ddb_port *port) | 1143 | static int port_has_stv0900(struct ddb_port *port) |
@@ -1188,7 +1193,8 @@ static void ddb_port_probe(struct ddb_port *port) | |||
1188 | port->type = DDB_TUNER_DVBCT_TR; | 1193 | port->type = DDB_TUNER_DVBCT_TR; |
1189 | ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); | 1194 | ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); |
1190 | } | 1195 | } |
1191 | printk("Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); | 1196 | printk(KERN_INFO "Port %d (TAB %d): %s\n", |
1197 | port->nr, port->nr+1, modname); | ||
1192 | } | 1198 | } |
1193 | 1199 | ||
1194 | static void ddb_input_init(struct ddb_port *port, int nr) | 1200 | static void ddb_input_init(struct ddb_port *port, int nr) |
@@ -1284,26 +1290,42 @@ static irqreturn_t irq_handler(int irq, void *dev_id) | |||
1284 | do { | 1290 | do { |
1285 | ddbwritel(s, INTERRUPT_ACK); | 1291 | ddbwritel(s, INTERRUPT_ACK); |
1286 | 1292 | ||
1287 | if (s & 0x00000001) irq_handle_i2c(dev, 0); | 1293 | if (s & 0x00000001) |
1288 | if (s & 0x00000002) irq_handle_i2c(dev, 1); | 1294 | irq_handle_i2c(dev, 0); |
1289 | if (s & 0x00000004) irq_handle_i2c(dev, 2); | 1295 | if (s & 0x00000002) |
1290 | if (s & 0x00000008) irq_handle_i2c(dev, 3); | 1296 | irq_handle_i2c(dev, 1); |
1291 | 1297 | if (s & 0x00000004) | |
1292 | if (s & 0x00000100) tasklet_schedule(&dev->input[0].tasklet); | 1298 | irq_handle_i2c(dev, 2); |
1293 | if (s & 0x00000200) tasklet_schedule(&dev->input[1].tasklet); | 1299 | if (s & 0x00000008) |
1294 | if (s & 0x00000400) tasklet_schedule(&dev->input[2].tasklet); | 1300 | irq_handle_i2c(dev, 3); |
1295 | if (s & 0x00000800) tasklet_schedule(&dev->input[3].tasklet); | 1301 | |
1296 | if (s & 0x00001000) tasklet_schedule(&dev->input[4].tasklet); | 1302 | if (s & 0x00000100) |
1297 | if (s & 0x00002000) tasklet_schedule(&dev->input[5].tasklet); | 1303 | tasklet_schedule(&dev->input[0].tasklet); |
1298 | if (s & 0x00004000) tasklet_schedule(&dev->input[6].tasklet); | 1304 | if (s & 0x00000200) |
1299 | if (s & 0x00008000) tasklet_schedule(&dev->input[7].tasklet); | 1305 | tasklet_schedule(&dev->input[1].tasklet); |
1300 | 1306 | if (s & 0x00000400) | |
1301 | if (s & 0x00010000) tasklet_schedule(&dev->output[0].tasklet); | 1307 | tasklet_schedule(&dev->input[2].tasklet); |
1302 | if (s & 0x00020000) tasklet_schedule(&dev->output[1].tasklet); | 1308 | if (s & 0x00000800) |
1303 | if (s & 0x00040000) tasklet_schedule(&dev->output[2].tasklet); | 1309 | tasklet_schedule(&dev->input[3].tasklet); |
1304 | if (s & 0x00080000) tasklet_schedule(&dev->output[3].tasklet); | 1310 | if (s & 0x00001000) |
1305 | 1311 | tasklet_schedule(&dev->input[4].tasklet); | |
1306 | /* if (s & 0x000f0000) printk("%08x\n", istat); */ | 1312 | if (s & 0x00002000) |
1313 | tasklet_schedule(&dev->input[5].tasklet); | ||
1314 | if (s & 0x00004000) | ||
1315 | tasklet_schedule(&dev->input[6].tasklet); | ||
1316 | if (s & 0x00008000) | ||
1317 | tasklet_schedule(&dev->input[7].tasklet); | ||
1318 | |||
1319 | if (s & 0x00010000) | ||
1320 | tasklet_schedule(&dev->output[0].tasklet); | ||
1321 | if (s & 0x00020000) | ||
1322 | tasklet_schedule(&dev->output[1].tasklet); | ||
1323 | if (s & 0x00040000) | ||
1324 | tasklet_schedule(&dev->output[2].tasklet); | ||
1325 | if (s & 0x00080000) | ||
1326 | tasklet_schedule(&dev->output[3].tasklet); | ||
1327 | |||
1328 | /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ | ||
1307 | } while ((s = ddbreadl(INTERRUPT_STATUS))); | 1329 | } while ((s = ddbreadl(INTERRUPT_STATUS))); |
1308 | 1330 | ||
1309 | return IRQ_HANDLED; | 1331 | return IRQ_HANDLED; |
@@ -1325,7 +1347,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) | |||
1325 | wbuf += 4; | 1347 | wbuf += 4; |
1326 | wlen -= 4; | 1348 | wlen -= 4; |
1327 | ddbwritel(data, SPI_DATA); | 1349 | ddbwritel(data, SPI_DATA); |
1328 | while (ddbreadl(SPI_CONTROL) & 0x0004); | 1350 | while (ddbreadl(SPI_CONTROL) & 0x0004) |
1351 | ; | ||
1329 | } | 1352 | } |
1330 | 1353 | ||
1331 | if (rlen) | 1354 | if (rlen) |
@@ -1333,7 +1356,7 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) | |||
1333 | else | 1356 | else |
1334 | ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); | 1357 | ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); |
1335 | 1358 | ||
1336 | data=0; | 1359 | data = 0; |
1337 | shift = ((4 - wlen) * 8); | 1360 | shift = ((4 - wlen) * 8); |
1338 | while (wlen) { | 1361 | while (wlen) { |
1339 | data <<= 8; | 1362 | data <<= 8; |
@@ -1344,7 +1367,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) | |||
1344 | if (shift) | 1367 | if (shift) |
1345 | data <<= shift; | 1368 | data <<= shift; |
1346 | ddbwritel(data, SPI_DATA); | 1369 | ddbwritel(data, SPI_DATA); |
1347 | while (ddbreadl(SPI_CONTROL) & 0x0004); | 1370 | while (ddbreadl(SPI_CONTROL) & 0x0004) |
1371 | ; | ||
1348 | 1372 | ||
1349 | if (!rlen) { | 1373 | if (!rlen) { |
1350 | ddbwritel(0, SPI_CONTROL); | 1374 | ddbwritel(0, SPI_CONTROL); |
@@ -1355,7 +1379,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) | |||
1355 | 1379 | ||
1356 | while (rlen > 4) { | 1380 | while (rlen > 4) { |
1357 | ddbwritel(0xffffffff, SPI_DATA); | 1381 | ddbwritel(0xffffffff, SPI_DATA); |
1358 | while (ddbreadl(SPI_CONTROL) & 0x0004); | 1382 | while (ddbreadl(SPI_CONTROL) & 0x0004) |
1383 | ; | ||
1359 | data = ddbreadl(SPI_DATA); | 1384 | data = ddbreadl(SPI_DATA); |
1360 | *(u32 *) rbuf = swab32(data); | 1385 | *(u32 *) rbuf = swab32(data); |
1361 | rbuf += 4; | 1386 | rbuf += 4; |
@@ -1363,7 +1388,8 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) | |||
1363 | } | 1388 | } |
1364 | ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); | 1389 | ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); |
1365 | ddbwritel(0xffffffff, SPI_DATA); | 1390 | ddbwritel(0xffffffff, SPI_DATA); |
1366 | while (ddbreadl(SPI_CONTROL) & 0x0004); | 1391 | while (ddbreadl(SPI_CONTROL) & 0x0004) |
1392 | ; | ||
1367 | 1393 | ||
1368 | data = ddbreadl(SPI_DATA); | 1394 | data = ddbreadl(SPI_DATA); |
1369 | ddbwritel(0, SPI_CONTROL); | 1395 | ddbwritel(0, SPI_CONTROL); |
@@ -1421,7 +1447,7 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
1421 | if (copy_from_user(&fio, parg, sizeof(fio))) | 1447 | if (copy_from_user(&fio, parg, sizeof(fio))) |
1422 | break; | 1448 | break; |
1423 | if (fio.write_len + fio.read_len > 1028) { | 1449 | if (fio.write_len + fio.read_len > 1028) { |
1424 | printk("IOBUF too small\n"); | 1450 | printk(KERN_ERR "IOBUF too small\n"); |
1425 | return -ENOMEM; | 1451 | return -ENOMEM; |
1426 | } | 1452 | } |
1427 | wbuf = &dev->iobuf[0]; | 1453 | wbuf = &dev->iobuf[0]; |
@@ -1444,7 +1470,7 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
1444 | return res; | 1470 | return res; |
1445 | } | 1471 | } |
1446 | 1472 | ||
1447 | static struct file_operations ddb_fops={ | 1473 | static const struct file_operations ddb_fops = { |
1448 | .unlocked_ioctl = ddb_ioctl, | 1474 | .unlocked_ioctl = ddb_ioctl, |
1449 | .open = ddb_open, | 1475 | .open = ddb_open, |
1450 | }; | 1476 | }; |
@@ -1458,7 +1484,8 @@ static char *ddb_devnode(struct device *device, mode_t *mode) | |||
1458 | 1484 | ||
1459 | static int ddb_class_create(void) | 1485 | static int ddb_class_create(void) |
1460 | { | 1486 | { |
1461 | if ((ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops))<0) | 1487 | ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); |
1488 | if (ddb_major < 0) | ||
1462 | return ddb_major; | 1489 | return ddb_major; |
1463 | 1490 | ||
1464 | ddb_class = class_create(THIS_MODULE, DDB_NAME); | 1491 | ddb_class = class_create(THIS_MODULE, DDB_NAME); |
@@ -1536,10 +1563,10 @@ static int __devinit ddb_probe(struct pci_dev *pdev, | |||
1536 | const struct pci_device_id *id) | 1563 | const struct pci_device_id *id) |
1537 | { | 1564 | { |
1538 | struct ddb *dev; | 1565 | struct ddb *dev; |
1539 | int stat=0; | 1566 | int stat = 0; |
1540 | int irq_flag = IRQF_SHARED; | 1567 | int irq_flag = IRQF_SHARED; |
1541 | 1568 | ||
1542 | if (pci_enable_device(pdev)<0) | 1569 | if (pci_enable_device(pdev) < 0) |
1543 | return -ENODEV; | 1570 | return -ENODEV; |
1544 | 1571 | ||
1545 | dev = vmalloc(sizeof(struct ddb)); | 1572 | dev = vmalloc(sizeof(struct ddb)); |
@@ -1550,15 +1577,15 @@ static int __devinit ddb_probe(struct pci_dev *pdev, | |||
1550 | dev->pdev = pdev; | 1577 | dev->pdev = pdev; |
1551 | pci_set_drvdata(pdev, dev); | 1578 | pci_set_drvdata(pdev, dev); |
1552 | dev->info = (struct ddb_info *) id->driver_data; | 1579 | dev->info = (struct ddb_info *) id->driver_data; |
1553 | printk("DDBridge driver detected: %s\n", dev->info->name); | 1580 | printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); |
1554 | 1581 | ||
1555 | dev->regs = ioremap(pci_resource_start(dev->pdev,0), | 1582 | dev->regs = ioremap(pci_resource_start(dev->pdev, 0), |
1556 | pci_resource_len(dev->pdev,0)); | 1583 | pci_resource_len(dev->pdev, 0)); |
1557 | if (!dev->regs) { | 1584 | if (!dev->regs) { |
1558 | stat = -ENOMEM; | 1585 | stat = -ENOMEM; |
1559 | goto fail; | 1586 | goto fail; |
1560 | } | 1587 | } |
1561 | printk("HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); | 1588 | printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); |
1562 | 1589 | ||
1563 | #ifdef CONFIG_PCI_MSI | 1590 | #ifdef CONFIG_PCI_MSI |
1564 | if (pci_msi_enabled()) | 1591 | if (pci_msi_enabled()) |
@@ -1570,9 +1597,9 @@ static int __devinit ddb_probe(struct pci_dev *pdev, | |||
1570 | dev->msi = 1; | 1597 | dev->msi = 1; |
1571 | } | 1598 | } |
1572 | #endif | 1599 | #endif |
1573 | if ((stat = request_irq(dev->pdev->irq, irq_handler, | 1600 | stat = request_irq(dev->pdev->irq, irq_handler, |
1574 | irq_flag, "DDBridge", | 1601 | irq_flag, "DDBridge", (void *) dev); |
1575 | (void *) dev))<0) | 1602 | if (stat < 0) |
1576 | goto fail1; | 1603 | goto fail1; |
1577 | ddbwritel(0, DMA_BASE_WRITE); | 1604 | ddbwritel(0, DMA_BASE_WRITE); |
1578 | ddbwritel(0, DMA_BASE_READ); | 1605 | ddbwritel(0, DMA_BASE_READ); |
@@ -1594,18 +1621,18 @@ static int __devinit ddb_probe(struct pci_dev *pdev, | |||
1594 | 1621 | ||
1595 | fail3: | 1622 | fail3: |
1596 | ddb_ports_detach(dev); | 1623 | ddb_ports_detach(dev); |
1597 | printk("fail3\n"); | 1624 | printk(KERN_ERR "fail3\n"); |
1598 | ddb_ports_release(dev); | 1625 | ddb_ports_release(dev); |
1599 | fail2: | 1626 | fail2: |
1600 | printk("fail2\n"); | 1627 | printk(KERN_ERR "fail2\n"); |
1601 | ddb_buffers_free(dev); | 1628 | ddb_buffers_free(dev); |
1602 | fail1: | 1629 | fail1: |
1603 | printk("fail1\n"); | 1630 | printk(KERN_ERR "fail1\n"); |
1604 | if (dev->msi) | 1631 | if (dev->msi) |
1605 | pci_disable_msi(dev->pdev); | 1632 | pci_disable_msi(dev->pdev); |
1606 | free_irq(dev->pdev->irq, dev); | 1633 | free_irq(dev->pdev->irq, dev); |
1607 | fail: | 1634 | fail: |
1608 | printk("fail\n"); | 1635 | printk(KERN_ERR "fail\n"); |
1609 | ddb_unmap(dev); | 1636 | ddb_unmap(dev); |
1610 | pci_set_drvdata(pdev, 0); | 1637 | pci_set_drvdata(pdev, 0); |
1611 | pci_disable_device(pdev); | 1638 | pci_disable_device(pdev); |
@@ -1641,7 +1668,7 @@ static struct ddb_info ddb_v6 = { | |||
1641 | 1668 | ||
1642 | #define DDVID 0xdd01 /* Digital Devices Vendor ID */ | 1669 | #define DDVID 0xdd01 /* Digital Devices Vendor ID */ |
1643 | 1670 | ||
1644 | #define DDB_ID(_vend, _dev, _subvend,_subdev,_driverdata) { \ | 1671 | #define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ |
1645 | .vendor = _vend, .device = _dev, \ | 1672 | .vendor = _vend, .device = _dev, \ |
1646 | .subvendor = _subvend, .subdevice = _subdev, \ | 1673 | .subvendor = _subvend, .subdevice = _subdev, \ |
1647 | .driver_data = (unsigned long)&_driverdata } | 1674 | .driver_data = (unsigned long)&_driverdata } |
@@ -1668,7 +1695,7 @@ static struct pci_driver ddb_pci_driver = { | |||
1668 | 1695 | ||
1669 | static __init int module_init_ddbridge(void) | 1696 | static __init int module_init_ddbridge(void) |
1670 | { | 1697 | { |
1671 | printk("Digital Devices PCIE bridge driver, " | 1698 | printk(KERN_INFO "Digital Devices PCIE bridge driver, " |
1672 | "Copyright (C) 2010-11 Digital Devices GmbH\n"); | 1699 | "Copyright (C) 2010-11 Digital Devices GmbH\n"); |
1673 | if (ddb_class_create()) | 1700 | if (ddb_class_create()) |
1674 | return -1; | 1701 | return -1; |
diff --git a/drivers/media/dvb/ddbridge/ddbridge-regs.h b/drivers/media/dvb/ddbridge/ddbridge-regs.h index 0130073af627..a3ccb318b500 100644 --- a/drivers/media/dvb/ddbridge/ddbridge-regs.h +++ b/drivers/media/dvb/ddbridge/ddbridge-regs.h | |||
@@ -21,26 +21,26 @@ | |||
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | 21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html |
22 | */ | 22 | */ |
23 | 23 | ||
24 | // $Id: DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred $ | 24 | /* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */ |
25 | 25 | ||
26 | // Register Definitions | 26 | /* Register Definitions */ |
27 | 27 | ||
28 | #define CUR_REGISTERMAP_VERSION 0x10000 | 28 | #define CUR_REGISTERMAP_VERSION 0x10000 |
29 | 29 | ||
30 | #define HARDWARE_VERSION 0x00 | 30 | #define HARDWARE_VERSION 0x00 |
31 | #define REGISTERMAP_VERSION 0x04 | 31 | #define REGISTERMAP_VERSION 0x04 |
32 | 32 | ||
33 | // -------------------------------------------------------------------------- | 33 | /* ------------------------------------------------------------------------- */ |
34 | // SPI Controller | 34 | /* SPI Controller */ |
35 | 35 | ||
36 | #define SPI_CONTROL 0x10 | 36 | #define SPI_CONTROL 0x10 |
37 | #define SPI_DATA 0x14 | 37 | #define SPI_DATA 0x14 |
38 | 38 | ||
39 | // -------------------------------------------------------------------------- | 39 | /* ------------------------------------------------------------------------- */ |
40 | 40 | ||
41 | // Interrupt controller | 41 | /* Interrupt controller */ |
42 | // How many MSI's are available depends on HW (Min 2 max 8) | 42 | /* How many MSI's are available depends on HW (Min 2 max 8) */ |
43 | // How many are usable also depends on Host platform | 43 | /* How many are usable also depends on Host platform */ |
44 | 44 | ||
45 | #define INTERRUPT_BASE (0x40) | 45 | #define INTERRUPT_BASE (0x40) |
46 | 46 | ||
@@ -81,15 +81,15 @@ | |||
81 | #define INTMASK_TSOUTPUT3 (0x00040000) | 81 | #define INTMASK_TSOUTPUT3 (0x00040000) |
82 | #define INTMASK_TSOUTPUT4 (0x00080000) | 82 | #define INTMASK_TSOUTPUT4 (0x00080000) |
83 | 83 | ||
84 | // -------------------------------------------------------------------------- | 84 | /* ------------------------------------------------------------------------- */ |
85 | // I2C Master Controller | 85 | /* I2C Master Controller */ |
86 | 86 | ||
87 | #define I2C_BASE (0x80) // Byte offset | 87 | #define I2C_BASE (0x80) /* Byte offset */ |
88 | 88 | ||
89 | #define I2C_COMMAND (0x00) | 89 | #define I2C_COMMAND (0x00) |
90 | #define I2C_TIMING (0x04) | 90 | #define I2C_TIMING (0x04) |
91 | #define I2C_TASKLENGTH (0x08) // High read, low write | 91 | #define I2C_TASKLENGTH (0x08) /* High read, low write */ |
92 | #define I2C_TASKADDRESS (0x0C) // High read, low write | 92 | #define I2C_TASKADDRESS (0x0C) /* High read, low write */ |
93 | 93 | ||
94 | #define I2C_MONITOR (0x1C) | 94 | #define I2C_MONITOR (0x1C) |
95 | 95 | ||
@@ -100,7 +100,7 @@ | |||
100 | 100 | ||
101 | #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) | 101 | #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) |
102 | 102 | ||
103 | #define I2C_TASKMEM_BASE (0x1000) // Byte offset | 103 | #define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ |
104 | #define I2C_TASKMEM_SIZE (0x1000) | 104 | #define I2C_TASKMEM_SIZE (0x1000) |
105 | 105 | ||
106 | #define I2C_SPEED_400 (0x04030404) | 106 | #define I2C_SPEED_400 (0x04030404) |
@@ -111,27 +111,27 @@ | |||
111 | #define I2C_SPEED_50 (0x27262727) | 111 | #define I2C_SPEED_50 (0x27262727) |
112 | 112 | ||
113 | 113 | ||
114 | // -------------------------------------------------------------------------- | 114 | /* ------------------------------------------------------------------------- */ |
115 | // DMA Controller | 115 | /* DMA Controller */ |
116 | 116 | ||
117 | #define DMA_BASE_WRITE (0x100) | 117 | #define DMA_BASE_WRITE (0x100) |
118 | #define DMA_BASE_READ (0x140) | 118 | #define DMA_BASE_READ (0x140) |
119 | 119 | ||
120 | #define DMA_CONTROL (0x00) // 64 | 120 | #define DMA_CONTROL (0x00) /* 64 */ |
121 | #define DMA_ERROR (0x04) // 65 ( only read instance ) | 121 | #define DMA_ERROR (0x04) /* 65 ( only read instance ) */ |
122 | 122 | ||
123 | #define DMA_DIAG_CONTROL (0x1C) // 71 | 123 | #define DMA_DIAG_CONTROL (0x1C) /* 71 */ |
124 | #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) // 72 | 124 | #define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */ |
125 | #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) // 73 | 125 | #define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */ |
126 | #define DMA_DIAG_TIMECOUNTER_LOW (0x28) // 74 | 126 | #define DMA_DIAG_TIMECOUNTER_LOW (0x28) /* 74 */ |
127 | #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) // 75 | 127 | #define DMA_DIAG_TIMECOUNTER_HIGH (0x2C) /* 75 */ |
128 | #define DMA_DIAG_RECHECKCOUNTER (0x30) // 76 ( Split completions on read ) | 128 | #define DMA_DIAG_RECHECKCOUNTER (0x30) /* 76 ( Split completions on read ) */ |
129 | #define DMA_DIAG_WAITTIMEOUTINIT (0x34) // 77 | 129 | #define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */ |
130 | #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) // 78 | 130 | #define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */ |
131 | #define DMA_DIAG_WAITCOUNTER (0x3C) // 79 | 131 | #define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */ |
132 | 132 | ||
133 | // -------------------------------------------------------------------------- | 133 | /* ------------------------------------------------------------------------- */ |
134 | // DMA Buffer | 134 | /* DMA Buffer */ |
135 | 135 | ||
136 | #define TS_INPUT_BASE (0x200) | 136 | #define TS_INPUT_BASE (0x200) |
137 | #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) | 137 | #define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) |
diff --git a/drivers/media/dvb/ddbridge/ddbridge.h b/drivers/media/dvb/ddbridge/ddbridge.h index c83630103561..6d14893218f4 100644 --- a/drivers/media/dvb/ddbridge/ddbridge.h +++ b/drivers/media/dvb/ddbridge/ddbridge.h | |||
@@ -177,10 +177,10 @@ struct ddb { | |||
177 | #define ddbwritel(_val, _adr) writel((_val), \ | 177 | #define ddbwritel(_val, _adr) writel((_val), \ |
178 | (char *) (dev->regs+(_adr))) | 178 | (char *) (dev->regs+(_adr))) |
179 | #define ddbreadl(_adr) readl((char *) (dev->regs+(_adr))) | 179 | #define ddbreadl(_adr) readl((char *) (dev->regs+(_adr))) |
180 | #define ddbcpyto(_adr,_src,_count) memcpy_toio((char *) \ | 180 | #define ddbcpyto(_adr, _src, _count) memcpy_toio((char *) \ |
181 | (dev->regs+(_adr)),(_src),(_count)) | 181 | (dev->regs+(_adr)), (_src), (_count)) |
182 | #define ddbcpyfrom(_dst,_adr,_count) memcpy_fromio((_dst),(char *) \ | 182 | #define ddbcpyfrom(_dst, _adr, _count) memcpy_fromio((_dst), (char *) \ |
183 | (dev->regs+(_adr)),(_count)) | 183 | (dev->regs+(_adr)), (_count)) |
184 | 184 | ||
185 | /****************************************************************************/ | 185 | /****************************************************************************/ |
186 | 186 | ||