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-rw-r--r--arch/arm/mach-shmobile/Makefile4
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S8
-rw-r--r--arch/arm/mach-shmobile/headsmp-sh73a0.S50
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h1
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c2
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c2
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c2
7 files changed, 10 insertions, 59 deletions
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 245a8736754a..d7d20579bef7 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -16,8 +16,8 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
16smp-y := platsmp.o headsmp.o 16smp-y := platsmp.o headsmp.o
17smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o 17smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
18smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o 18smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o
19smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o 19smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o
20smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o 20smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o
21 21
22# IRQ objects 22# IRQ objects
23obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 23obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 4ee287d9c508..0b9317062b2a 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -39,7 +39,8 @@ ENTRY(shmobile_secondary_vector_scu)
39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR 39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
40 and r0, r0, #3 @ mask out cpu ID 40 and r0, r0, #3 @ mask out cpu ID
41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits 41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
42 mov r1, #0xf0000000 @ SCU base address 42 ldr r1, =shmobile_scu_base
43 ldr r1, [r1] @ SCU base address
43 ldr r2, [r1, #8] @ SCU Power Status Register 44 ldr r2, [r1, #8] @ SCU Power Status Register
44 mov r3, #3 45 mov r3, #3
45 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) 46 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
@@ -48,3 +49,8 @@ ENTRY(shmobile_secondary_vector_scu)
48 ldr pc, 1f 49 ldr pc, 1f
491: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET 501: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
50ENDPROC(shmobile_secondary_vector_scu) 51ENDPROC(shmobile_secondary_vector_scu)
52
53 .text
54 .globl shmobile_scu_base
55shmobile_scu_base:
56 .space 4
diff --git a/arch/arm/mach-shmobile/headsmp-sh73a0.S b/arch/arm/mach-shmobile/headsmp-sh73a0.S
deleted file mode 100644
index bec4c0d9b713..000000000000
--- a/arch/arm/mach-shmobile/headsmp-sh73a0.S
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * SMP support for SoC sh73a0
3 *
4 * Copyright (C) 2012 Bastian Hecht
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <linux/linkage.h>
23#include <linux/init.h>
24#include <asm/memory.h>
25
26 __CPUINIT
27/*
28 * Reset vector for secondary CPUs.
29 *
30 * First we turn on L1 cache coherency for our CPU. Then we jump to
31 * shmobile_invalidate_start that invalidates the cache and hands over control
32 * to the common ARM startup code.
33 * This function will be mapped to address 0 by the SBAR register.
34 * A normal branch is out of range here so we need a long jump. We jump to
35 * the physical address as the MMU is still turned off.
36 */
37 .align 12
38ENTRY(sh73a0_secondary_vector)
39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
40 and r0, r0, #3 @ mask out cpu ID
41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
42 mov r1, #0xf0000000 @ SCU base address
43 ldr r2, [r1, #8] @ SCU Power Status Register
44 mov r3, #3
45 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
46 str r2, [r1, #8] @ write back
47
48 ldr pc, 1f
491: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
50ENDPROC(sh73a0_secondary_vector)
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 20acf000b46b..84dcaa4279b2 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -95,6 +95,7 @@ extern int shmobile_cpu_is_dead(unsigned int cpu);
95static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; } 95static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
96#endif 96#endif
97 97
98extern void __iomem *shmobile_scu_base;
98extern void shmobile_smp_init_cpus(unsigned int ncores); 99extern void shmobile_smp_init_cpus(unsigned int ncores);
99 100
100static inline void __init shmobile_init_late(void) 101static inline void __init shmobile_init_late(void)
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 136867ea1e93..bc8e071d55c6 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -32,8 +32,6 @@
32 32
33#define EMEV2_SCU_BASE 0x1e000000 33#define EMEV2_SCU_BASE 0x1e000000
34 34
35static void __iomem *shmobile_scu_base;
36
37static DEFINE_SPINLOCK(scu_lock); 35static DEFINE_SPINLOCK(scu_lock);
38 36
39static void modify_scu_cpu_psr(unsigned long set, unsigned long clr) 37static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index d92188d702ab..7fd58a3a26d8 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -33,8 +33,6 @@
33#define AVECR IOMEM(0xfe700040) 33#define AVECR IOMEM(0xfe700040)
34#define R8A7779_SCU_BASE IOMEM(0xf0000000) 34#define R8A7779_SCU_BASE IOMEM(0xf0000000)
35 35
36static void __iomem *shmobile_scu_base;
37
38static struct r8a7779_pm_ch r8a7779_ch_cpu1 = { 36static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
39 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */ 37 .chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
40 .chan_bit = 1, /* ARM1 */ 38 .chan_bit = 1, /* ARM1 */
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index de7518f745f0..2244fd074f72 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,8 +41,6 @@
41 41
42#define SH73A0_SCU_BASE IOMEM(0xf0000000) 42#define SH73A0_SCU_BASE IOMEM(0xf0000000)
43 43
44static void __iomem *shmobile_scu_base;
45
46#ifdef CONFIG_HAVE_ARM_TWD 44#ifdef CONFIG_HAVE_ARM_TWD
47static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); 45static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
48void __init sh73a0_register_twd(void) 46void __init sh73a0_register_twd(void)