5 files changed, 43 insertions, 29 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24b7796c33af..b97d62d81905 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1013,7 +1013,8 @@ void i915_gem_process_flushing_list(struct drm_device *dev,
                                     struct intel_ring_buffer *ring);
 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
                                       int write);
-int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
+int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
+                                         bool pipelined);
 int i915_gem_attach_phys_object(struct drm_device *dev,
                                 struct drm_gem_object *obj,
                                 int id,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4a0d85c78d47..85a3cf4ab481 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2597,6 +2597,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
         /* Queue the GPU write cache flushing we need. */
         old_write_domain = obj->write_domain;
         i915_gem_flush(dev, 0, obj->write_domain);
+        BUG_ON(obj->write_domain);
 
         trace_i915_gem_object_change_domain(obj,
                                             obj->read_domains,
@@ -2704,7 +2705,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
  * wait, as in modesetting process we're not supposed to be interrupted.
  */
 int
-i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
+i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
+                                     bool pipelined)
 {
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
         uint32_t old_read_domains;
@@ -2714,8 +2716,8 @@ i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
         if (obj_priv->gtt_space == NULL)
                 return -EINVAL;
 
-        ret = i915_gem_object_flush_gpu_write_domain(obj, true);
-        if (ret != 0)
+        ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined);
+        if (ret)
                 return ret;
 
         i915_gem_object_flush_cpu_write_domain(obj);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 810ed2dca4c7..a7628fdd0c4c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1417,7 +1417,9 @@ out_disable:
 }
 
 int
-intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
+intel_pin_and_fence_fb_obj(struct drm_device *dev,
+                           struct drm_gem_object *obj,
+                           bool pipelined)
 {
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
         u32 alignment;
@@ -1445,14 +1447,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
         }
 
         ret = i915_gem_object_pin(obj, alignment);
-        if (ret != 0)
+        if (ret)
                 return ret;
 
-        ret = i915_gem_object_set_to_display_plane(obj);
-        if (ret != 0) {
-                i915_gem_object_unpin(obj);
-                return ret;
-        }
+        ret = i915_gem_object_set_to_display_plane(obj, pipelined);
+        if (ret)
+                goto err_unpin;
 
         /* Install a fence for tiled scan-out. Pre-i965 always needs a
          * fence, whereas 965+ only requires a fence if using
@@ -1462,13 +1462,15 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
             obj_priv->tiling_mode != I915_TILING_NONE) {
                 ret = i915_gem_object_get_fence_reg(obj);
-                if (ret != 0) {
-                        i915_gem_object_unpin(obj);
-                        return ret;
-                }
+                if (ret)
+                        goto err_unpin;
         }
 
         return 0;
+
+err_unpin:
+        i915_gem_object_unpin(obj);
+        return ret;
 }
 
 /* Assume fb object is pinned & idle & fenced and just update base pointers */
@@ -1589,7 +1591,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         obj_priv = to_intel_bo(obj);
 
         mutex_lock(&dev->struct_mutex);
-        ret = intel_pin_and_fence_fb_obj(dev, obj);
+        ret = intel_pin_and_fence_fb_obj(dev, obj, false);
         if (ret != 0) {
                 mutex_unlock(&dev->struct_mutex);
                 return ret;
@@ -5004,7 +5006,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         struct intel_unpin_work *work;
         unsigned long flags, offset;
         int pipe = intel_crtc->pipe;
-        u32 pf, pipesrc;
+        u32 was_dirty, pf, pipesrc;
         int ret;
 
         work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -5033,7 +5035,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         obj = intel_fb->obj;
 
         mutex_lock(&dev->struct_mutex);
-        ret = intel_pin_and_fence_fb_obj(dev, obj);
+        was_dirty = obj->write_domain & I915_GEM_GPU_DOMAINS;
+        ret = intel_pin_and_fence_fb_obj(dev, obj, true);
         if (ret)
                 goto cleanup_work;
 
@@ -5051,17 +5054,24 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         atomic_inc(&obj_priv->pending_flip);
         work->pending_flip_obj = obj;
 
-        if (IS_GEN3(dev) || IS_GEN2(dev)) {
-                u32 flip_mask;
+        if (was_dirty || IS_GEN3(dev) || IS_GEN2(dev)) {
+                BEGIN_LP_RING(2);
+                if (IS_GEN3(dev) || IS_GEN2(dev)) {
+                        u32 flip_mask;
 
-                if (intel_crtc->plane)
-                        flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-                else
-                        flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
+                        /* Can't queue multiple flips, so wait for the previous
+                         * one to finish before executing the next.
+                         */
 
-                BEGIN_LP_RING(2);
-                OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
-                OUT_RING(0);
+                        if (intel_crtc->plane)
+                                flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
+                        else
+                                flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
+
+                        OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
+                } else
+                        OUT_RING(MI_NOOP);
+                OUT_RING(MI_FLUSH);
                 ADVANCE_LP_RING();
         }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5171b0523178..31f072d31e37 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -281,7 +281,8 @@ extern void ironlake_enable_drps(struct drm_device *dev);
 extern void ironlake_disable_drps(struct drm_device *dev);
 
 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
-                                      struct drm_gem_object *obj);
+                                      struct drm_gem_object *obj,
+                                      bool pipelined);
 
 extern int intel_framebuffer_init(struct drm_device *dev,
                                   struct intel_framebuffer *ifb,
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index e2d13e394a0d..8a23bf772c95 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -94,7 +94,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
         mutex_lock(&dev->struct_mutex);
 
         /* Flush everything out, we'll be doing GTT only from now on */
-        ret = intel_pin_and_fence_fb_obj(dev, fbo);
+        ret = intel_pin_and_fence_fb_obj(dev, fbo, false);
         if (ret) {
                 DRM_ERROR("failed to pin fb: %d\n", ret);
                 goto out_unref;