diff options
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_kms.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 25 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770d.h | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 27 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/sid.h | 5 |
9 files changed, 93 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index dbcb0752f083..37d81fd09555 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -109,6 +109,19 @@ void r600_fini(struct radeon_device *rdev); | |||
109 | void r600_irq_disable(struct radeon_device *rdev); | 109 | void r600_irq_disable(struct radeon_device *rdev); |
110 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); | 110 | static void r600_pcie_gen2_enable(struct radeon_device *rdev); |
111 | 111 | ||
112 | /** | ||
113 | * r600_get_xclk - get the xclk | ||
114 | * | ||
115 | * @rdev: radeon_device pointer | ||
116 | * | ||
117 | * Returns the reference clock used by the gfx engine | ||
118 | * (r6xx, IGPs, APUs). | ||
119 | */ | ||
120 | u32 r600_get_xclk(struct radeon_device *rdev) | ||
121 | { | ||
122 | return rdev->clock.spll.reference_freq; | ||
123 | } | ||
124 | |||
112 | /* get temperature in millidegrees */ | 125 | /* get temperature in millidegrees */ |
113 | int rv6xx_get_temp(struct radeon_device *rdev) | 126 | int rv6xx_get_temp(struct radeon_device *rdev) |
114 | { | 127 | { |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 59bfbd3868c9..e425b412f246 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -1179,6 +1179,8 @@ struct radeon_asic { | |||
1179 | bool (*gui_idle)(struct radeon_device *rdev); | 1179 | bool (*gui_idle)(struct radeon_device *rdev); |
1180 | /* wait for mc_idle */ | 1180 | /* wait for mc_idle */ |
1181 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | 1181 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
1182 | /* get the reference clock */ | ||
1183 | u32 (*get_xclk)(struct radeon_device *rdev); | ||
1182 | /* gart */ | 1184 | /* gart */ |
1183 | struct { | 1185 | struct { |
1184 | void (*tlb_flush)(struct radeon_device *rdev); | 1186 | void (*tlb_flush)(struct radeon_device *rdev); |
@@ -1860,6 +1862,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); | |||
1860 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) | 1862 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) |
1861 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) | 1863 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
1862 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | 1864 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
1865 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) | ||
1863 | 1866 | ||
1864 | /* Common functions */ | 1867 | /* Common functions */ |
1865 | /* AGP */ | 1868 | /* AGP */ |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 67f008febec7..e1b4a6832312 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -934,6 +934,7 @@ static struct radeon_asic r600_asic = { | |||
934 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 934 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
935 | .gui_idle = &r600_gui_idle, | 935 | .gui_idle = &r600_gui_idle, |
936 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | 936 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
937 | .get_xclk = &r600_get_xclk, | ||
937 | .gart = { | 938 | .gart = { |
938 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 939 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
939 | .set_page = &rs600_gart_set_page, | 940 | .set_page = &rs600_gart_set_page, |
@@ -1018,6 +1019,7 @@ static struct radeon_asic rs780_asic = { | |||
1018 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1019 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1019 | .gui_idle = &r600_gui_idle, | 1020 | .gui_idle = &r600_gui_idle, |
1020 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | 1021 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
1022 | .get_xclk = &r600_get_xclk, | ||
1021 | .gart = { | 1023 | .gart = { |
1022 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 1024 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1023 | .set_page = &rs600_gart_set_page, | 1025 | .set_page = &rs600_gart_set_page, |
@@ -1102,6 +1104,7 @@ static struct radeon_asic rv770_asic = { | |||
1102 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1104 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1103 | .gui_idle = &r600_gui_idle, | 1105 | .gui_idle = &r600_gui_idle, |
1104 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | 1106 | .mc_wait_for_idle = &r600_mc_wait_for_idle, |
1107 | .get_xclk = &rv770_get_xclk, | ||
1105 | .gart = { | 1108 | .gart = { |
1106 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 1109 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1107 | .set_page = &rs600_gart_set_page, | 1110 | .set_page = &rs600_gart_set_page, |
@@ -1186,6 +1189,7 @@ static struct radeon_asic evergreen_asic = { | |||
1186 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1189 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1187 | .gui_idle = &r600_gui_idle, | 1190 | .gui_idle = &r600_gui_idle, |
1188 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | 1191 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1192 | .get_xclk = &rv770_get_xclk, | ||
1189 | .gart = { | 1193 | .gart = { |
1190 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1194 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1191 | .set_page = &rs600_gart_set_page, | 1195 | .set_page = &rs600_gart_set_page, |
@@ -1270,6 +1274,7 @@ static struct radeon_asic sumo_asic = { | |||
1270 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1274 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1271 | .gui_idle = &r600_gui_idle, | 1275 | .gui_idle = &r600_gui_idle, |
1272 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | 1276 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1277 | .get_xclk = &r600_get_xclk, | ||
1273 | .gart = { | 1278 | .gart = { |
1274 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1279 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1275 | .set_page = &rs600_gart_set_page, | 1280 | .set_page = &rs600_gart_set_page, |
@@ -1354,6 +1359,7 @@ static struct radeon_asic btc_asic = { | |||
1354 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1359 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1355 | .gui_idle = &r600_gui_idle, | 1360 | .gui_idle = &r600_gui_idle, |
1356 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | 1361 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1362 | .get_xclk = &rv770_get_xclk, | ||
1357 | .gart = { | 1363 | .gart = { |
1358 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1364 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1359 | .set_page = &rs600_gart_set_page, | 1365 | .set_page = &rs600_gart_set_page, |
@@ -1438,6 +1444,7 @@ static struct radeon_asic cayman_asic = { | |||
1438 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1444 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1439 | .gui_idle = &r600_gui_idle, | 1445 | .gui_idle = &r600_gui_idle, |
1440 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | 1446 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1447 | .get_xclk = &rv770_get_xclk, | ||
1441 | .gart = { | 1448 | .gart = { |
1442 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | 1449 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
1443 | .set_page = &rs600_gart_set_page, | 1450 | .set_page = &rs600_gart_set_page, |
@@ -1565,6 +1572,7 @@ static struct radeon_asic trinity_asic = { | |||
1565 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1572 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1566 | .gui_idle = &r600_gui_idle, | 1573 | .gui_idle = &r600_gui_idle, |
1567 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | 1574 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1575 | .get_xclk = &r600_get_xclk, | ||
1568 | .gart = { | 1576 | .gart = { |
1569 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | 1577 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
1570 | .set_page = &rs600_gart_set_page, | 1578 | .set_page = &rs600_gart_set_page, |
@@ -1692,6 +1700,7 @@ static struct radeon_asic si_asic = { | |||
1692 | .ioctl_wait_idle = r600_ioctl_wait_idle, | 1700 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
1693 | .gui_idle = &r600_gui_idle, | 1701 | .gui_idle = &r600_gui_idle, |
1694 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | 1702 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, |
1703 | .get_xclk = &si_get_xclk, | ||
1695 | .gart = { | 1704 | .gart = { |
1696 | .tlb_flush = &si_pcie_gart_tlb_flush, | 1705 | .tlb_flush = &si_pcie_gart_tlb_flush, |
1697 | .set_page = &rs600_gart_set_page, | 1706 | .set_page = &rs600_gart_set_page, |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index f4134a823958..f15758c7a262 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -390,6 +390,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev, | |||
390 | struct radeon_sa_bo *vb); | 390 | struct radeon_sa_bo *vb); |
391 | int r600_mc_wait_for_idle(struct radeon_device *rdev); | 391 | int r600_mc_wait_for_idle(struct radeon_device *rdev); |
392 | uint64_t r600_get_gpu_clock(struct radeon_device *rdev); | 392 | uint64_t r600_get_gpu_clock(struct radeon_device *rdev); |
393 | u32 r600_get_xclk(struct radeon_device *rdev); | ||
393 | 394 | ||
394 | /* | 395 | /* |
395 | * rv770,rv730,rv710,rv740 | 396 | * rv770,rv730,rv710,rv740 |
@@ -407,6 +408,7 @@ int rv770_copy_dma(struct radeon_device *rdev, | |||
407 | uint64_t src_offset, uint64_t dst_offset, | 408 | uint64_t src_offset, uint64_t dst_offset, |
408 | unsigned num_gpu_pages, | 409 | unsigned num_gpu_pages, |
409 | struct radeon_fence **fence); | 410 | struct radeon_fence **fence); |
411 | u32 rv770_get_xclk(struct radeon_device *rdev); | ||
410 | 412 | ||
411 | /* | 413 | /* |
412 | * evergreen | 414 | * evergreen |
@@ -521,5 +523,6 @@ int si_copy_dma(struct radeon_device *rdev, | |||
521 | unsigned num_gpu_pages, | 523 | unsigned num_gpu_pages, |
522 | struct radeon_fence **fence); | 524 | struct radeon_fence **fence); |
523 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); | 525 | void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
526 | u32 si_get_xclk(struct radeon_device *rdev); | ||
524 | 527 | ||
525 | #endif | 528 | #endif |
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 9c312f9afb68..96f05cde116a 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -282,7 +282,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) | |||
282 | break; | 282 | break; |
283 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: | 283 | case RADEON_INFO_CLOCK_CRYSTAL_FREQ: |
284 | /* return clock value in KHz */ | 284 | /* return clock value in KHz */ |
285 | value = rdev->clock.spll.reference_freq * 10; | 285 | if (rdev->asic->get_xclk) |
286 | value = radeon_get_xclk(rdev) * 10; | ||
287 | else | ||
288 | value = rdev->clock.spll.reference_freq * 10; | ||
286 | break; | 289 | break; |
287 | case RADEON_INFO_NUM_BACKENDS: | 290 | case RADEON_INFO_NUM_BACKENDS: |
288 | if (rdev->family >= CHIP_TAHITI) | 291 | if (rdev->family >= CHIP_TAHITI) |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 1b2444f4d8f4..d63fe1d0f53f 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -43,6 +43,31 @@ static void rv770_gpu_init(struct radeon_device *rdev); | |||
43 | void rv770_fini(struct radeon_device *rdev); | 43 | void rv770_fini(struct radeon_device *rdev); |
44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); | 44 | static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
45 | 45 | ||
46 | #define PCIE_BUS_CLK 10000 | ||
47 | #define TCLK (PCIE_BUS_CLK / 10) | ||
48 | |||
49 | /** | ||
50 | * rv770_get_xclk - get the xclk | ||
51 | * | ||
52 | * @rdev: radeon_device pointer | ||
53 | * | ||
54 | * Returns the reference clock used by the gfx engine | ||
55 | * (r7xx-cayman). | ||
56 | */ | ||
57 | u32 rv770_get_xclk(struct radeon_device *rdev) | ||
58 | { | ||
59 | u32 reference_clock = rdev->clock.spll.reference_freq; | ||
60 | u32 tmp = RREG32(CG_CLKPIN_CNTL); | ||
61 | |||
62 | if (tmp & MUX_TCLK_TO_XCLK) | ||
63 | return TCLK; | ||
64 | |||
65 | if (tmp & XTALIN_DIVIDE) | ||
66 | return reference_clock / 4; | ||
67 | |||
68 | return reference_clock; | ||
69 | } | ||
70 | |||
46 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) | 71 | u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
47 | { | 72 | { |
48 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; | 73 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index 20e29d23d348..c55f950a4af7 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h | |||
@@ -128,6 +128,10 @@ | |||
128 | #define GUI_ACTIVE (1<<31) | 128 | #define GUI_ACTIVE (1<<31) |
129 | #define GRBM_STATUS2 0x8014 | 129 | #define GRBM_STATUS2 0x8014 |
130 | 130 | ||
131 | #define CG_CLKPIN_CNTL 0x660 | ||
132 | # define MUX_TCLK_TO_XCLK (1 << 8) | ||
133 | # define XTALIN_DIVIDE (1 << 9) | ||
134 | |||
131 | #define CG_MULT_THERMAL_STATUS 0x740 | 135 | #define CG_MULT_THERMAL_STATUS 0x740 |
132 | #define ASIC_T(x) ((x) << 16) | 136 | #define ASIC_T(x) ((x) << 16) |
133 | #define ASIC_T_MASK 0x3FF0000 | 137 | #define ASIC_T_MASK 0x3FF0000 |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 719f03e061db..b5064fae0726 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -70,6 +70,33 @@ extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); | |||
70 | extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); | 70 | extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); |
71 | extern bool evergreen_is_display_hung(struct radeon_device *rdev); | 71 | extern bool evergreen_is_display_hung(struct radeon_device *rdev); |
72 | 72 | ||
73 | #define PCIE_BUS_CLK 10000 | ||
74 | #define TCLK (PCIE_BUS_CLK / 10) | ||
75 | |||
76 | /** | ||
77 | * si_get_xclk - get the xclk | ||
78 | * | ||
79 | * @rdev: radeon_device pointer | ||
80 | * | ||
81 | * Returns the reference clock used by the gfx engine | ||
82 | * (SI). | ||
83 | */ | ||
84 | u32 si_get_xclk(struct radeon_device *rdev) | ||
85 | { | ||
86 | u32 reference_clock = rdev->clock.spll.reference_freq; | ||
87 | u32 tmp; | ||
88 | |||
89 | tmp = RREG32(CG_CLKPIN_CNTL_2); | ||
90 | if (tmp & MUX_TCLK_TO_XCLK) | ||
91 | return TCLK; | ||
92 | |||
93 | tmp = RREG32(CG_CLKPIN_CNTL); | ||
94 | if (tmp & XTALIN_DIVIDE) | ||
95 | return reference_clock / 4; | ||
96 | |||
97 | return reference_clock; | ||
98 | } | ||
99 | |||
73 | /* get temperature in millidegrees */ | 100 | /* get temperature in millidegrees */ |
74 | int si_get_temp(struct radeon_device *rdev) | 101 | int si_get_temp(struct radeon_device *rdev) |
75 | { | 102 | { |
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index 07fc455e35ae..23fc08fc8e7f 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h | |||
@@ -58,6 +58,11 @@ | |||
58 | #define VGA_HDP_CONTROL 0x328 | 58 | #define VGA_HDP_CONTROL 0x328 |
59 | #define VGA_MEMORY_DISABLE (1 << 4) | 59 | #define VGA_MEMORY_DISABLE (1 << 4) |
60 | 60 | ||
61 | #define CG_CLKPIN_CNTL 0x660 | ||
62 | # define XTALIN_DIVIDE (1 << 1) | ||
63 | #define CG_CLKPIN_CNTL_2 0x664 | ||
64 | # define MUX_TCLK_TO_XCLK (1 << 8) | ||
65 | |||
61 | #define DMIF_ADDR_CONFIG 0xBD4 | 66 | #define DMIF_ADDR_CONFIG 0xBD4 |
62 | 67 | ||
63 | #define SRBM_STATUS 0xE50 | 68 | #define SRBM_STATUS 0xE50 |