3 files changed, 12 insertions, 7 deletions

diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 820116067c10..516e6e9a5594 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
         if (! ((asid += ASID_INC) & ASID_MASK) ) {
                 if (cpu_has_vtag_icache)
                         flush_icache_all();
-#ifdef CONFIG_VIRTUALIZATION
+#ifdef CONFIG_KVM
                 kvm_local_flush_tlb_all();      /* start new asid cycle */
 #else
                 local_flush_tlb_all();  /* start new asid cycle */
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
 #define MCOUNT_OFFSET_INSNS 4
 #endif
 
+#ifdef CONFIG_DYNAMIC_FTRACE
+
 /* Arch override because MIPS doesn't need to run this from stop_machine() */
 void arch_ftrace_update_code(int command)
 {
         ftrace_modify_all_code(command);
 }
 
+#endif
+
 /*
  * Check if the address is in kernel space
  *
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
 }
 
 /*
- * The Au1xxx wait is available only if using 32khz counter or
- * external timer source, but specifically not CP0 Counter.
- * alchemy/common/time.c may override cpu_wait!
+ * Au1 'wait' is only useful when the 32kHz counter is used as timer,
+ * since coreclock (and the cp0 counter) stops upon executing it. Only an
+ * interrupt can wake it, so they must be enabled before entering idle modes.
  */
 static void au1k_wait(void)
 {
+        unsigned long c0status = read_c0_status() | 1;  /* irqs on */
+
         __asm__(
         "       .set    mips3                   \n"
         "       cache   0x14, 0(%0)             \n"
         "       cache   0x14, 32(%0)            \n"
         "       sync                            \n"
-        "       nop                             \n"
+        "       mtc0    %1, $12                 \n" /* wr c0status */
         "       wait                            \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       .set    mips0                   \n"
-        : : "r" (au1k_wait));
-        local_irq_enable();
+        : : "r" (au1k_wait), "r" (c0status));
 }
 
 static int __initdata nowait;