diff options
author | Shengjiu Wang <b02247@freescale.com> | 2014-06-10 03:08:38 -0400 |
---|---|---|
committer | Shengjiu Wang <b02247@freescale.com> | 2014-06-10 06:17:38 -0400 |
commit | a6b32f60cb01958e04899bc04ca0d55e8fc8ae54 (patch) | |
tree | c5d43309c5cbc7be9a4a7ef5b1e2f22fdfe97563 /sound/soc/fsl | |
parent | ce7311e1dd414b2f3af1babae43b868d8b67b18f (diff) |
ENGR00317675-1 ASoC: fsl: esai: refine esai for tdm support
Add parameter for slots, and caculate the number of TX/RX pins with
slots.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
Diffstat (limited to 'sound/soc/fsl')
-rw-r--r-- | sound/soc/fsl/fsl_esai.c | 14 | ||||
-rw-r--r-- | sound/soc/fsl/fsl_esai.h | 8 |
2 files changed, 13 insertions, 9 deletions
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c index 36d7a184827e..09d904a064cc 100644 --- a/sound/soc/fsl/fsl_esai.c +++ b/sound/soc/fsl/fsl_esai.c | |||
@@ -58,6 +58,7 @@ struct fsl_esai { | |||
58 | struct clk *dmaclk; | 58 | struct clk *dmaclk; |
59 | u32 fifo_depth; | 59 | u32 fifo_depth; |
60 | u32 slot_width; | 60 | u32 slot_width; |
61 | u32 slots; | ||
61 | u32 hck_rate[2]; | 62 | u32 hck_rate[2]; |
62 | bool sck_div[2]; | 63 | bool sck_div[2]; |
63 | bool slave_mode; | 64 | bool slave_mode; |
@@ -343,6 +344,7 @@ static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, | |||
343 | ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask)); | 344 | ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask)); |
344 | 345 | ||
345 | esai_priv->slot_width = slot_width; | 346 | esai_priv->slot_width = slot_width; |
347 | esai_priv->slots = slots; | ||
346 | 348 | ||
347 | return 0; | 349 | return 0; |
348 | } | 350 | } |
@@ -476,9 +478,10 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream, | |||
476 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | 478 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
477 | u32 width = snd_pcm_format_width(params_format(params)); | 479 | u32 width = snd_pcm_format_width(params_format(params)); |
478 | u32 channels = params_channels(params); | 480 | u32 channels = params_channels(params); |
481 | u32 pin = DIV_ROUND_UP(channels, esai_priv->slots); | ||
479 | u32 bclk, mask, val, ret; | 482 | u32 bclk, mask, val, ret; |
480 | 483 | ||
481 | bclk = params_rate(params) * esai_priv->slot_width * 2; | 484 | bclk = params_rate(params) * esai_priv->slot_width * esai_priv->slots; |
482 | 485 | ||
483 | ret = fsl_esai_set_bclk(dai, tx, bclk); | 486 | ret = fsl_esai_set_bclk(dai, tx, bclk); |
484 | if (ret) | 487 | if (ret) |
@@ -495,7 +498,7 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream, | |||
495 | mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | | 498 | mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | |
496 | (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); | 499 | (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); |
497 | val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | | 500 | val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | |
498 | (tx ? ESAI_xFCR_TE(channels) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(channels)); | 501 | (tx ? ESAI_xFCR_TE(pin) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pin)); |
499 | 502 | ||
500 | regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); | 503 | regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); |
501 | 504 | ||
@@ -541,6 +544,7 @@ static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, | |||
541 | struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); | 544 | struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); |
542 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | 545 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
543 | u8 i, channels = substream->runtime->channels; | 546 | u8 i, channels = substream->runtime->channels; |
547 | u32 pin = DIV_ROUND_UP(channels, esai_priv->slots); | ||
544 | 548 | ||
545 | switch (cmd) { | 549 | switch (cmd) { |
546 | case SNDRV_PCM_TRIGGER_START: | 550 | case SNDRV_PCM_TRIGGER_START: |
@@ -555,7 +559,7 @@ static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, | |||
555 | 559 | ||
556 | regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), | 560 | regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), |
557 | tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, | 561 | tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, |
558 | tx ? ESAI_xCR_TE(channels) : ESAI_xCR_RE(channels)); | 562 | tx ? ESAI_xCR_TE(pin) : ESAI_xCR_RE(pin)); |
559 | break; | 563 | break; |
560 | case SNDRV_PCM_TRIGGER_SUSPEND: | 564 | case SNDRV_PCM_TRIGGER_SUSPEND: |
561 | case SNDRV_PCM_TRIGGER_STOP: | 565 | case SNDRV_PCM_TRIGGER_STOP: |
@@ -732,9 +736,9 @@ static int restore_reg(struct snd_soc_dai *cpu_dai) | |||
732 | regmap_write(esai_priv->regmap, REG_ESAI_TFCR, esai_priv->reg_cache[2] & ~ESAI_xFCR_xFEN); | 736 | regmap_write(esai_priv->regmap, REG_ESAI_TFCR, esai_priv->reg_cache[2] & ~ESAI_xFCR_xFEN); |
733 | regmap_write(esai_priv->regmap, REG_ESAI_RFCR, esai_priv->reg_cache[4] & ~ESAI_xFCR_xFEN); | 737 | regmap_write(esai_priv->regmap, REG_ESAI_RFCR, esai_priv->reg_cache[4] & ~ESAI_xFCR_xFEN); |
734 | regmap_write(esai_priv->regmap, REG_ESAI_SAICR, esai_priv->reg_cache[8]); | 738 | regmap_write(esai_priv->regmap, REG_ESAI_SAICR, esai_priv->reg_cache[8]); |
735 | regmap_write(esai_priv->regmap, REG_ESAI_TCR, esai_priv->reg_cache[9] & ~ESAI_xCR_TE(12)); | 739 | regmap_write(esai_priv->regmap, REG_ESAI_TCR, esai_priv->reg_cache[9] & ~ESAI_xCR_TE(6)); |
736 | regmap_write(esai_priv->regmap, REG_ESAI_TCCR, esai_priv->reg_cache[10]); | 740 | regmap_write(esai_priv->regmap, REG_ESAI_TCCR, esai_priv->reg_cache[10]); |
737 | regmap_write(esai_priv->regmap, REG_ESAI_RCR, esai_priv->reg_cache[11] & ~ESAI_xCR_RE(8)); | 741 | regmap_write(esai_priv->regmap, REG_ESAI_RCR, esai_priv->reg_cache[11] & ~ESAI_xCR_RE(4)); |
738 | regmap_write(esai_priv->regmap, REG_ESAI_RCCR, esai_priv->reg_cache[12]); | 742 | regmap_write(esai_priv->regmap, REG_ESAI_RCCR, esai_priv->reg_cache[12]); |
739 | regmap_write(esai_priv->regmap, REG_ESAI_TSMA, esai_priv->reg_cache[13]); | 743 | regmap_write(esai_priv->regmap, REG_ESAI_TSMA, esai_priv->reg_cache[13]); |
740 | regmap_write(esai_priv->regmap, REG_ESAI_TSMB, esai_priv->reg_cache[14]); | 744 | regmap_write(esai_priv->regmap, REG_ESAI_TSMB, esai_priv->reg_cache[14]); |
diff --git a/sound/soc/fsl/fsl_esai.h b/sound/soc/fsl/fsl_esai.h index 75e14033e8d8..91a550f4a10d 100644 --- a/sound/soc/fsl/fsl_esai.h +++ b/sound/soc/fsl/fsl_esai.h | |||
@@ -130,8 +130,8 @@ | |||
130 | #define ESAI_xFCR_RE_WIDTH 4 | 130 | #define ESAI_xFCR_RE_WIDTH 4 |
131 | #define ESAI_xFCR_TE_MASK (((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT) | 131 | #define ESAI_xFCR_TE_MASK (((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT) |
132 | #define ESAI_xFCR_RE_MASK (((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT) | 132 | #define ESAI_xFCR_RE_MASK (((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT) |
133 | #define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - ((x + 1) >> 1))) & ESAI_xFCR_TE_MASK) | 133 | #define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - x)) & ESAI_xFCR_TE_MASK) |
134 | #define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - ((x + 1) >> 1))) & ESAI_xFCR_RE_MASK) | 134 | #define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - x)) & ESAI_xFCR_RE_MASK) |
135 | #define ESAI_xFCR_xFR_SHIFT 1 | 135 | #define ESAI_xFCR_xFR_SHIFT 1 |
136 | #define ESAI_xFCR_xFR_MASK (1 << ESAI_xFCR_xFR_SHIFT) | 136 | #define ESAI_xFCR_xFR_MASK (1 << ESAI_xFCR_xFR_SHIFT) |
137 | #define ESAI_xFCR_xFR (1 << ESAI_xFCR_xFR_SHIFT) | 137 | #define ESAI_xFCR_xFR (1 << ESAI_xFCR_xFR_SHIFT) |
@@ -272,8 +272,8 @@ | |||
272 | #define ESAI_xCR_RE_WIDTH 4 | 272 | #define ESAI_xCR_RE_WIDTH 4 |
273 | #define ESAI_xCR_TE_MASK (((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT) | 273 | #define ESAI_xCR_TE_MASK (((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT) |
274 | #define ESAI_xCR_RE_MASK (((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT) | 274 | #define ESAI_xCR_RE_MASK (((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT) |
275 | #define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - ((x + 1) >> 1))) & ESAI_xCR_TE_MASK) | 275 | #define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - x)) & ESAI_xCR_TE_MASK) |
276 | #define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - ((x + 1) >> 1))) & ESAI_xCR_RE_MASK) | 276 | #define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - x)) & ESAI_xCR_RE_MASK) |
277 | 277 | ||
278 | /* | 278 | /* |
279 | * Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8 | 279 | * Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8 |