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authorMark Brown <broonie@linaro.org>2013-06-07 11:19:58 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:00:42 -0400
commitea689c50a38359cbd4fbb42deb38a9a103452a64 (patch)
treeee6cfb4d10275621a930f5cd6b9b998ba684408d /sound/soc/codecs
parent2426ca4ffd5a2324d09a2bb85262310c4c0a0d96 (diff)
ASoC: wm8962: Restore device state after reset in runtime resume
Commit 9c24b1672283644adf871244771ebf387dd73f90 upstream. After the device has been reset we need to repeat the same initialisation we do on probe to make sure that the device is in a known state. Tested-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'sound/soc/codecs')
-rw-r--r--sound/soc/codecs/wm8962.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c
index 2bb087c264dc..3e2a0a574f13 100644
--- a/sound/soc/codecs/wm8962.c
+++ b/sound/soc/codecs/wm8962.c
@@ -3759,6 +3759,21 @@ static int wm8962_runtime_resume(struct device *dev)
3759 3759
3760 wm8962_reset(wm8962); 3760 wm8962_reset(wm8962);
3761 3761
3762 /* SYSCLK defaults to on; make sure it is off so we can safely
3763 * write to registers if the device is declocked.
3764 */
3765 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3766 WM8962_SYSCLK_ENA, 0);
3767
3768 /* Ensure we have soft control over all registers */
3769 regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
3770 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3771
3772 /* Ensure that the oscillator and PLLs are disabled */
3773 regmap_update_bits(wm8962->regmap, WM8962_PLL2,
3774 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3775 0);
3776
3762 regcache_sync(wm8962->regmap); 3777 regcache_sync(wm8962->regmap);
3763 3778
3764 return 0; 3779 return 0;