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authorTakashi Iwai <tiwai@suse.de>2005-11-17 04:21:19 -0500
committerJaroslav Kysela <perex@suse.cz>2006-01-03 06:16:37 -0500
commitbdbae7e62837c22c5399df0789a24e9d8a1d675f (patch)
tree4bffa9bf42f5b7541bc432f8b2437e8130278f88 /sound/pci
parentc8eb6ba16a5803fab9cc0d1d0dd04a75bf91b6d5 (diff)
[ALSA] Remove snd_vx_delay() function
Replace snd_vx_delay() with appropriate delay/sleep functions. Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/pci')
-rw-r--r--sound/pci/vx222/vx222_ops.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/sound/pci/vx222/vx222_ops.c b/sound/pci/vx222/vx222_ops.c
index 967bd5e6b23c..2d4d0c29b4c4 100644
--- a/sound/pci/vx222/vx222_ops.c
+++ b/sound/pci/vx222/vx222_ops.c
@@ -154,7 +154,7 @@ static void vx2_reset_dsp(vx_core_t *_chip)
154 /* set the reset dsp bit to 0 */ 154 /* set the reset dsp bit to 0 */
155 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); 155 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK);
156 156
157 snd_vx_delay(_chip, XX_DSP_RESET_WAIT_TIME); 157 mdelay(XX_DSP_RESET_WAIT_TIME);
158 158
159 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; 159 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK;
160 /* set the reset dsp bit to 1 */ 160 /* set the reset dsp bit to 1 */
@@ -362,10 +362,10 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
362 /* XILINX reset (wait at least 1 milisecond between reset on and off). */ 362 /* XILINX reset (wait at least 1 milisecond between reset on and off). */
363 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); 363 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
364 vx_inl(chip, CNTRL); 364 vx_inl(chip, CNTRL);
365 snd_vx_delay(chip, 10); 365 msleep(10);
366 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); 366 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE);
367 vx_inl(chip, CNTRL); 367 vx_inl(chip, CNTRL);
368 snd_vx_delay(chip, 10); 368 msleep(10);
369 369
370 if (chip->type == VX_TYPE_BOARD) 370 if (chip->type == VX_TYPE_BOARD)
371 port = VX_CNTRL; 371 port = VX_CNTRL;
@@ -381,7 +381,7 @@ static int vx2_load_xilinx_binary(vx_core_t *chip, const struct firmware *xilinx
381 } 381 }
382 put_xilinx_data(chip, port, 4, 0xff); /* end signature */ 382 put_xilinx_data(chip, port, 4, 0xff); /* end signature */
383 383
384 snd_vx_delay(chip, 200); 384 msleep(200);
385 385
386 /* test after loading (is buggy with VX222) */ 386 /* test after loading (is buggy with VX222) */
387 if (chip->type != VX_TYPE_BOARD) { 387 if (chip->type != VX_TYPE_BOARD) {
@@ -720,17 +720,17 @@ static void vx2_reset_codec(vx_core_t *_chip)
720 /* Set the reset CODEC bit to 0. */ 720 /* Set the reset CODEC bit to 0. */
721 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); 721 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK);
722 vx_inl(chip, CDSP); 722 vx_inl(chip, CDSP);
723 snd_vx_delay(_chip, 10); 723 msleep(10);
724 /* Set the reset CODEC bit to 1. */ 724 /* Set the reset CODEC bit to 1. */
725 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; 725 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK;
726 vx_outl(chip, CDSP, chip->regCDSP); 726 vx_outl(chip, CDSP, chip->regCDSP);
727 vx_inl(chip, CDSP); 727 vx_inl(chip, CDSP);
728 if (_chip->type == VX_TYPE_BOARD) { 728 if (_chip->type == VX_TYPE_BOARD) {
729 snd_vx_delay(_chip, 1); 729 msleep(1);
730 return; 730 return;
731 } 731 }
732 732
733 snd_vx_delay(_chip, 5); /* additionnel wait time for AKM's */ 733 msleep(5); /* additionnel wait time for AKM's */
734 734
735 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ 735 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */
736 736