ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk API

The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can
possibly lock up the downstream divider and result in no clock output.
Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide
these two buggy muxes from clk API.  Then no clk_set_parent() can be
called on these muxes to switch parent clock at run-time.

Kernel parameter 'ldb_di_clk_sel' is created to select parent of
ldb_di_clk among the following clocks at boot time.

	'pll5_video_div'
	'pll2_pfd0_352m'
	'pll2_pfd2_396m'
	'mmdc_ch1_axi'
	'pll3_usb_otg'

Example format: ldb_di_clk_sel=pll5_video_div

If the kernel parameter is absent or invalid, pll2_pfd0_352m will be
selected by default.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

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