atyfb: fix CONFIG_ namespace violations

Fix namespace violations by changing non-kconfig CONFIG_ names to CNFG_*.

Fixes breakage in staging/, which adds a real CONFIG_PANEL.

Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

3 files changed, 23 insertions, 23 deletions

diff --git a/include/video/aty128.h b/include/video/aty128.h
index 7079beb005e8..51ac69f05bdc 100644
--- a/include/video/aty128.h
+++ b/include/video/aty128.h
@@ -21,9 +21,9 @@
 #define I2C_CNTL_1                              0x0094
 #define PALETTE_INDEX                           0x00b0
 #define PALETTE_DATA                            0x00b4
-#define CONFIG_CNTL                             0x00e0
+#define CNFG_CNTL                               0x00e0
 #define GEN_RESET_CNTL                          0x00f0
-#define CONFIG_MEMSIZE                          0x00f8
+#define CNFG_MEMSIZE                            0x00f8
 #define MEM_CNTL                                0x0140
 #define MEM_POWER_MISC                          0x015c
 #define AGP_BASE                                0x0170
diff --git a/include/video/mach64.h b/include/video/mach64.h
index a8332e528ec1..89e91c0cb737 100644
--- a/include/video/mach64.h
+++ b/include/video/mach64.h
@@ -103,7 +103,7 @@
 #define CUR_HORZ_VERT_OFF       0x0070  /* Dword offset 0_1C */
 #define CUR2_HORZ_VERT_OFF      0x0070  /* Dword offset 0_1C */
 
-#define CONFIG_PANEL_LG         0x0074  /* Dword offset 0_1D (LG) */
+#define CNFG_PANEL_LG           0x0074  /* Dword offset 0_1D (LG) */
 
 /* General I/O Control */
 #define GP_IO                   0x0078  /* Dword offset 0_1E */
@@ -146,8 +146,8 @@
 #define CLOCK_SEL_CNTL          0x0090  /* Dword offset 0_24 */
 
 /* Configuration */
-#define CONFIG_STAT1            0x0094  /* Dword offset 0_25 */
-#define CONFIG_STAT2            0x0098  /* Dword offset 0_26 */
+#define CNFG_STAT1              0x0094  /* Dword offset 0_25 */
+#define CNFG_STAT2              0x0098  /* Dword offset 0_26 */
 
 /* Bus Control */
 #define BUS_CNTL                0x00A0  /* Dword offset 0_28 */
@@ -190,9 +190,9 @@
 #define POWER_MANAGEMENT_LG     0x00D8  /* Dword offset 0_36 (LG) */
 
 /* Configuration */
-#define CONFIG_CNTL             0x00DC  /* Dword offset 0_37 (CT, ET, VT) */
-#define CONFIG_CHIP_ID          0x00E0  /* Dword offset 0_38 */
-#define CONFIG_STAT0            0x00E4  /* Dword offset 0_39 */
+#define CNFG_CNTL               0x00DC  /* Dword offset 0_37 (CT, ET, VT) */
+#define CNFG_CHIP_ID            0x00E0  /* Dword offset 0_38 */
+#define CNFG_STAT0              0x00E4  /* Dword offset 0_39 */
 
 /* Test and Debug */
 #define CRC_SIG                 0x00E8  /* Dword offset 0_3A */
@@ -851,17 +851,17 @@
 #define PLL_YCLK_CNTL           0x29
 #define PM_DYN_CLK_CNTL         0x2A
 
-/* CONFIG_CNTL register constants */
+/* CNFG_CNTL register constants */
 #define APERTURE_4M_ENABLE      1
 #define APERTURE_8M_ENABLE      2
 #define VGA_APERTURE_ENABLE     4
 
-/* CONFIG_STAT0 register constants (GX, CX) */
+/* CNFG_STAT0 register constants (GX, CX) */
 #define CFG_BUS_TYPE            0x00000007
 #define CFG_MEM_TYPE            0x00000038
 #define CFG_INIT_DAC_TYPE       0x00000e00
 
-/* CONFIG_STAT0 register constants (CT, ET, VT) */
+/* CNFG_STAT0 register constants (CT, ET, VT) */
 #define CFG_MEM_TYPE_xT         0x00000007
 
 #define ISA                     0
@@ -942,7 +942,7 @@
 #define PCI_ATI_VENDOR_ID       0x1002
 
 
-/* CONFIG_CHIP_ID register constants */
+/* CNFG_CHIP_ID register constants */
 #define CFG_CHIP_TYPE           0x0000FFFF
 #define CFG_CHIP_CLASS          0x00FF0000
 #define CFG_CHIP_REV            0xFF000000
@@ -951,7 +951,7 @@
 #define CFG_CHIP_MINOR          0xC0000000
 
 
-/* Chip IDs read from CONFIG_CHIP_ID */
+/* Chip IDs read from CNFG_CHIP_ID */
 
 /* mach64GX family */
 #define GX_CHIP_ID      0xD7    /* mach64GX (ATI888GX00) */
@@ -1254,7 +1254,7 @@
 #define CRTC2_DISPLAY_DIS       0x00000400
 
 /* LCD register indices */
-#define CONFIG_PANEL            0x00
+#define CNFG_PANEL              0x00
 #define LCD_GEN_CNTL            0x01
 #define DSTN_CONTROL            0x02
 #define HFB_PITCH_ADDR          0x03
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 1cd09cc5b169..e072b16b39ab 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -11,13 +11,13 @@
 #define HI_STAT                                0x004C  
 #define BUS_CNTL1                              0x0034
 #define I2C_CNTL_1                             0x0094  
-#define CONFIG_CNTL                            0x00E0  
-#define CONFIG_MEMSIZE                         0x00F8  
-#define CONFIG_APER_0_BASE                     0x0100  
-#define CONFIG_APER_1_BASE                     0x0104  
-#define CONFIG_APER_SIZE                       0x0108  
-#define CONFIG_REG_1_BASE                      0x010C  
-#define CONFIG_REG_APER_SIZE                   0x0110  
+#define CNFG_CNTL                              0x00E0
+#define CNFG_MEMSIZE                           0x00F8
+#define CNFG_APER_0_BASE                       0x0100
+#define CNFG_APER_1_BASE                       0x0104
+#define CNFG_APER_SIZE                         0x0108
+#define CNFG_REG_1_BASE                        0x010C
+#define CNFG_REG_APER_SIZE                     0x0110
 #define PAD_AGPINPUT_DELAY                     0x0164  
 #define PAD_CTLR_STRENGTH                      0x0168  
 #define PAD_CTLR_UPDATE                        0x016C
@@ -509,7 +509,7 @@
 /* CLOCK_CNTL_INDEX bit constants */
 #define PLL_WR_EN                                  0x00000080
 
-/* CONFIG_CNTL bit constants */
+/* CNFG_CNTL bit constants */
 #define CFG_VGA_RAM_EN                             0x00000100
 #define CFG_ATI_REV_ID_MASK                        (0xf << 16)
 #define CFG_ATI_REV_A11                            (0 << 16)
@@ -980,7 +980,7 @@
 
 /* masks */
 
-#define CONFIG_MEMSIZE_MASK             0x1f000000
+#define CNFG_MEMSIZE_MASK               0x1f000000
 #define MEM_CFG_TYPE                    0x40000000
 #define DST_OFFSET_MASK                 0x003fffff
 #define DST_PITCH_MASK                  0x3fc00000