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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/video
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/video')
-rw-r--r--include/video/aty128.h422
-rw-r--r--include/video/cirrus.h122
-rw-r--r--include/video/cvisionppc.h51
-rw-r--r--include/video/edid.h27
-rw-r--r--include/video/epson1355.h64
-rw-r--r--include/video/gbe.h317
-rw-r--r--include/video/iga.h24
-rw-r--r--include/video/kyro.h92
-rw-r--r--include/video/mach64.h1377
-rw-r--r--include/video/maxinefb.h38
-rw-r--r--include/video/neomagic.h207
-rw-r--r--include/video/newport.h582
-rw-r--r--include/video/permedia2.h233
-rw-r--r--include/video/pm3fb.h1241
-rw-r--r--include/video/pmag-ba-fb.h24
-rw-r--r--include/video/pmagb-b-fb.h32
-rw-r--r--include/video/radeon.h1985
-rw-r--r--include/video/s1d13xxxfb.h166
-rw-r--r--include/video/s3blit.h79
-rw-r--r--include/video/sgivw.h682
-rw-r--r--include/video/sisfb.h198
-rw-r--r--include/video/sstfb.h354
-rw-r--r--include/video/tdfx.h192
-rw-r--r--include/video/tgafb.h238
-rw-r--r--include/video/trident.h175
-rw-r--r--include/video/tx3912.h62
-rw-r--r--include/video/vga.h482
-rw-r--r--include/video/w100fb.h21
28 files changed, 9487 insertions, 0 deletions
diff --git a/include/video/aty128.h b/include/video/aty128.h
new file mode 100644
index 000000000000..7079beb005e8
--- /dev/null
+++ b/include/video/aty128.h
@@ -0,0 +1,422 @@
1/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $
2 * linux/drivers/video/aty128.h
3 * Register definitions for ATI Rage128 boards
4 *
5 * Anthony Tong <atong@uiuc.edu>, 1999
6 * Brad Douglas <brad@neruo.com>, 2000
7 */
8
9#ifndef REG_RAGE128_H
10#define REG_RAGE128_H
11
12#define CLOCK_CNTL_INDEX 0x0008
13#define CLOCK_CNTL_DATA 0x000c
14#define BIOS_0_SCRATCH 0x0010
15#define BUS_CNTL 0x0030
16#define BUS_CNTL1 0x0034
17#define GEN_INT_CNTL 0x0040
18#define CRTC_GEN_CNTL 0x0050
19#define CRTC_EXT_CNTL 0x0054
20#define DAC_CNTL 0x0058
21#define I2C_CNTL_1 0x0094
22#define PALETTE_INDEX 0x00b0
23#define PALETTE_DATA 0x00b4
24#define CONFIG_CNTL 0x00e0
25#define GEN_RESET_CNTL 0x00f0
26#define CONFIG_MEMSIZE 0x00f8
27#define MEM_CNTL 0x0140
28#define MEM_POWER_MISC 0x015c
29#define AGP_BASE 0x0170
30#define AGP_CNTL 0x0174
31#define AGP_APER_OFFSET 0x0178
32#define PCI_GART_PAGE 0x017c
33#define PC_NGUI_MODE 0x0180
34#define PC_NGUI_CTLSTAT 0x0184
35#define MPP_TB_CONFIG 0x01C0
36#define MPP_GP_CONFIG 0x01C8
37#define VIPH_CONTROL 0x01D0
38#define CRTC_H_TOTAL_DISP 0x0200
39#define CRTC_H_SYNC_STRT_WID 0x0204
40#define CRTC_V_TOTAL_DISP 0x0208
41#define CRTC_V_SYNC_STRT_WID 0x020c
42#define CRTC_VLINE_CRNT_VLINE 0x0210
43#define CRTC_CRNT_FRAME 0x0214
44#define CRTC_GUI_TRIG_VLINE 0x0218
45#define CRTC_OFFSET 0x0224
46#define CRTC_OFFSET_CNTL 0x0228
47#define CRTC_PITCH 0x022c
48#define OVR_CLR 0x0230
49#define OVR_WID_LEFT_RIGHT 0x0234
50#define OVR_WID_TOP_BOTTOM 0x0238
51#define LVDS_GEN_CNTL 0x02d0
52#define DDA_CONFIG 0x02e0
53#define DDA_ON_OFF 0x02e4
54#define VGA_DDA_CONFIG 0x02e8
55#define VGA_DDA_ON_OFF 0x02ec
56#define CRTC2_H_TOTAL_DISP 0x0300
57#define CRTC2_H_SYNC_STRT_WID 0x0304
58#define CRTC2_V_TOTAL_DISP 0x0308
59#define CRTC2_V_SYNC_STRT_WID 0x030c
60#define CRTC2_VLINE_CRNT_VLINE 0x0310
61#define CRTC2_CRNT_FRAME 0x0314
62#define CRTC2_GUI_TRIG_VLINE 0x0318
63#define CRTC2_OFFSET 0x0324
64#define CRTC2_OFFSET_CNTL 0x0328
65#define CRTC2_PITCH 0x032c
66#define DDA2_CONFIG 0x03e0
67#define DDA2_ON_OFF 0x03e4
68#define CRTC2_GEN_CNTL 0x03f8
69#define CRTC2_STATUS 0x03fc
70#define OV0_SCALE_CNTL 0x0420
71#define SUBPIC_CNTL 0x0540
72#define PM4_BUFFER_OFFSET 0x0700
73#define PM4_BUFFER_CNTL 0x0704
74#define PM4_BUFFER_WM_CNTL 0x0708
75#define PM4_BUFFER_DL_RPTR_ADDR 0x070c
76#define PM4_BUFFER_DL_RPTR 0x0710
77#define PM4_BUFFER_DL_WPTR 0x0714
78#define PM4_VC_FPU_SETUP 0x071c
79#define PM4_FPU_CNTL 0x0720
80#define PM4_VC_FORMAT 0x0724
81#define PM4_VC_CNTL 0x0728
82#define PM4_VC_I01 0x072c
83#define PM4_VC_VLOFF 0x0730
84#define PM4_VC_VLSIZE 0x0734
85#define PM4_IW_INDOFF 0x0738
86#define PM4_IW_INDSIZE 0x073c
87#define PM4_FPU_FPX0 0x0740
88#define PM4_FPU_FPY0 0x0744
89#define PM4_FPU_FPX1 0x0748
90#define PM4_FPU_FPY1 0x074c
91#define PM4_FPU_FPX2 0x0750
92#define PM4_FPU_FPY2 0x0754
93#define PM4_FPU_FPY3 0x0758
94#define PM4_FPU_FPY4 0x075c
95#define PM4_FPU_FPY5 0x0760
96#define PM4_FPU_FPY6 0x0764
97#define PM4_FPU_FPR 0x0768
98#define PM4_FPU_FPG 0x076c
99#define PM4_FPU_FPB 0x0770
100#define PM4_FPU_FPA 0x0774
101#define PM4_FPU_INTXY0 0x0780
102#define PM4_FPU_INTXY1 0x0784
103#define PM4_FPU_INTXY2 0x0788
104#define PM4_FPU_INTARGB 0x078c
105#define PM4_FPU_FPTWICEAREA 0x0790
106#define PM4_FPU_DMAJOR01 0x0794
107#define PM4_FPU_DMAJOR12 0x0798
108#define PM4_FPU_DMAJOR02 0x079c
109#define PM4_FPU_STAT 0x07a0
110#define PM4_STAT 0x07b8
111#define PM4_TEST_CNTL 0x07d0
112#define PM4_MICROCODE_ADDR 0x07d4
113#define PM4_MICROCODE_RADDR 0x07d8
114#define PM4_MICROCODE_DATAH 0x07dc
115#define PM4_MICROCODE_DATAL 0x07e0
116#define PM4_CMDFIFO_ADDR 0x07e4
117#define PM4_CMDFIFO_DATAH 0x07e8
118#define PM4_CMDFIFO_DATAL 0x07ec
119#define PM4_BUFFER_ADDR 0x07f0
120#define PM4_BUFFER_DATAH 0x07f4
121#define PM4_BUFFER_DATAL 0x07f8
122#define PM4_MICRO_CNTL 0x07fc
123#define CAP0_TRIG_CNTL 0x0950
124#define CAP1_TRIG_CNTL 0x09c0
125
126/******************************************************************************
127 * GUI Block Memory Mapped Registers *
128 * These registers are FIFOed. *
129 *****************************************************************************/
130#define PM4_FIFO_DATA_EVEN 0x1000
131#define PM4_FIFO_DATA_ODD 0x1004
132
133#define DST_OFFSET 0x1404
134#define DST_PITCH 0x1408
135#define DST_WIDTH 0x140c
136#define DST_HEIGHT 0x1410
137#define SRC_X 0x1414
138#define SRC_Y 0x1418
139#define DST_X 0x141c
140#define DST_Y 0x1420
141#define SRC_PITCH_OFFSET 0x1428
142#define DST_PITCH_OFFSET 0x142c
143#define SRC_Y_X 0x1434
144#define DST_Y_X 0x1438
145#define DST_HEIGHT_WIDTH 0x143c
146#define DP_GUI_MASTER_CNTL 0x146c
147#define BRUSH_SCALE 0x1470
148#define BRUSH_Y_X 0x1474
149#define DP_BRUSH_BKGD_CLR 0x1478
150#define DP_BRUSH_FRGD_CLR 0x147c
151#define DST_WIDTH_X 0x1588
152#define DST_HEIGHT_WIDTH_8 0x158c
153#define SRC_X_Y 0x1590
154#define DST_X_Y 0x1594
155#define DST_WIDTH_HEIGHT 0x1598
156#define DST_WIDTH_X_INCY 0x159c
157#define DST_HEIGHT_Y 0x15a0
158#define DST_X_SUB 0x15a4
159#define DST_Y_SUB 0x15a8
160#define SRC_OFFSET 0x15ac
161#define SRC_PITCH 0x15b0
162#define DST_HEIGHT_WIDTH_BW 0x15b4
163#define CLR_CMP_CNTL 0x15c0
164#define CLR_CMP_CLR_SRC 0x15c4
165#define CLR_CMP_CLR_DST 0x15c8
166#define CLR_CMP_MASK 0x15cc
167#define DP_SRC_FRGD_CLR 0x15d8
168#define DP_SRC_BKGD_CLR 0x15dc
169#define DST_BRES_ERR 0x1628
170#define DST_BRES_INC 0x162c
171#define DST_BRES_DEC 0x1630
172#define DST_BRES_LNTH 0x1634
173#define DST_BRES_LNTH_SUB 0x1638
174#define SC_LEFT 0x1640
175#define SC_RIGHT 0x1644
176#define SC_TOP 0x1648
177#define SC_BOTTOM 0x164c
178#define SRC_SC_RIGHT 0x1654
179#define SRC_SC_BOTTOM 0x165c
180#define GUI_DEBUG0 0x16a0
181#define GUI_DEBUG1 0x16a4
182#define GUI_TIMEOUT 0x16b0
183#define GUI_TIMEOUT0 0x16b4
184#define GUI_TIMEOUT1 0x16b8
185#define GUI_PROBE 0x16bc
186#define DP_CNTL 0x16c0
187#define DP_DATATYPE 0x16c4
188#define DP_MIX 0x16c8
189#define DP_WRITE_MASK 0x16cc
190#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
191#define DEFAULT_OFFSET 0x16e0
192#define DEFAULT_PITCH 0x16e4
193#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
194#define SC_TOP_LEFT 0x16ec
195#define SC_BOTTOM_RIGHT 0x16f0
196#define SRC_SC_BOTTOM_RIGHT 0x16f4
197#define WAIT_UNTIL 0x1720
198#define CACHE_CNTL 0x1724
199#define GUI_STAT 0x1740
200#define PC_GUI_MODE 0x1744
201#define PC_GUI_CTLSTAT 0x1748
202#define PC_DEBUG_MODE 0x1760
203#define BRES_DST_ERR_DEC 0x1780
204#define TRAIL_BRES_T12_ERR_DEC 0x1784
205#define TRAIL_BRES_T12_INC 0x1788
206#define DP_T12_CNTL 0x178c
207#define DST_BRES_T1_LNTH 0x1790
208#define DST_BRES_T2_LNTH 0x1794
209#define SCALE_SRC_HEIGHT_WIDTH 0x1994
210#define SCALE_OFFSET_0 0x1998
211#define SCALE_PITCH 0x199c
212#define SCALE_X_INC 0x19a0
213#define SCALE_Y_INC 0x19a4
214#define SCALE_HACC 0x19a8
215#define SCALE_VACC 0x19ac
216#define SCALE_DST_X_Y 0x19b0
217#define SCALE_DST_HEIGHT_WIDTH 0x19b4
218#define SCALE_3D_CNTL 0x1a00
219#define SCALE_3D_DATATYPE 0x1a20
220#define SETUP_CNTL 0x1bc4
221#define SOLID_COLOR 0x1bc8
222#define WINDOW_XY_OFFSET 0x1bcc
223#define DRAW_LINE_POINT 0x1bd0
224#define SETUP_CNTL_PM4 0x1bd4
225#define DST_PITCH_OFFSET_C 0x1c80
226#define DP_GUI_MASTER_CNTL_C 0x1c84
227#define SC_TOP_LEFT_C 0x1c88
228#define SC_BOTTOM_RIGHT_C 0x1c8c
229
230#define CLR_CMP_MASK_3D 0x1A28
231#define MISC_3D_STATE_CNTL_REG 0x1CA0
232#define MC_SRC1_CNTL 0x19D8
233#define TEX_CNTL 0x1800
234
235/* CONSTANTS */
236#define GUI_ACTIVE 0x80000000
237#define ENGINE_IDLE 0x0
238
239#define PLL_WR_EN 0x00000080
240
241#define CLK_PIN_CNTL 0x0001
242#define PPLL_CNTL 0x0002
243#define PPLL_REF_DIV 0x0003
244#define PPLL_DIV_0 0x0004
245#define PPLL_DIV_1 0x0005
246#define PPLL_DIV_2 0x0006
247#define PPLL_DIV_3 0x0007
248#define VCLK_ECP_CNTL 0x0008
249#define HTOTAL_CNTL 0x0009
250#define X_MPLL_REF_FB_DIV 0x000a
251#define XPLL_CNTL 0x000b
252#define XDLL_CNTL 0x000c
253#define XCLK_CNTL 0x000d
254#define MPLL_CNTL 0x000e
255#define MCLK_CNTL 0x000f
256#define AGP_PLL_CNTL 0x0010
257#define FCP_CNTL 0x0012
258#define PLL_TEST_CNTL 0x0013
259#define P2PLL_CNTL 0x002a
260#define P2PLL_REF_DIV 0x002b
261#define P2PLL_DIV_0 0x002b
262#define POWER_MANAGEMENT 0x002f
263
264#define PPLL_RESET 0x01
265#define PPLL_ATOMIC_UPDATE_EN 0x10000
266#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000
267#define PPLL_REF_DIV_MASK 0x3FF
268#define PPLL_FB3_DIV_MASK 0x7FF
269#define PPLL_POST3_DIV_MASK 0x70000
270#define PPLL_ATOMIC_UPDATE_R 0x8000
271#define PPLL_ATOMIC_UPDATE_W 0x8000
272#define MEM_CFG_TYPE_MASK 0x3
273#define XCLK_SRC_SEL_MASK 0x7
274#define XPLL_FB_DIV_MASK 0xFF00
275#define X_MPLL_REF_DIV_MASK 0xFF
276
277/* CRTC control values (CRTC_GEN_CNTL) */
278#define CRTC_CSYNC_EN 0x00000010
279
280#define CRTC2_DBL_SCAN_EN 0x00000001
281#define CRTC2_DISPLAY_DIS 0x00800000
282#define CRTC2_FIFO_EXTSENSE 0x00200000
283#define CRTC2_ICON_EN 0x00100000
284#define CRTC2_CUR_EN 0x00010000
285#define CRTC2_EN 0x02000000
286#define CRTC2_DISP_REQ_EN_B 0x04000000
287
288#define CRTC_PIX_WIDTH_MASK 0x00000700
289#define CRTC_PIX_WIDTH_4BPP 0x00000100
290#define CRTC_PIX_WIDTH_8BPP 0x00000200
291#define CRTC_PIX_WIDTH_15BPP 0x00000300
292#define CRTC_PIX_WIDTH_16BPP 0x00000400
293#define CRTC_PIX_WIDTH_24BPP 0x00000500
294#define CRTC_PIX_WIDTH_32BPP 0x00000600
295
296/* DAC_CNTL bit constants */
297#define DAC_8BIT_EN 0x00000100
298#define DAC_MASK 0xFF000000
299#define DAC_BLANKING 0x00000004
300#define DAC_RANGE_CNTL 0x00000003
301#define DAC_CLK_SEL 0x00000010
302#define DAC_PALETTE_ACCESS_CNTL 0x00000020
303#define DAC_PALETTE2_SNOOP_EN 0x00000040
304#define DAC_PDWN 0x00008000
305
306/* CRTC_EXT_CNTL */
307#define CRT_CRTC_ON 0x00008000
308
309/* GEN_RESET_CNTL bit constants */
310#define SOFT_RESET_GUI 0x00000001
311#define SOFT_RESET_VCLK 0x00000100
312#define SOFT_RESET_PCLK 0x00000200
313#define SOFT_RESET_ECP 0x00000400
314#define SOFT_RESET_DISPENG_XCLK 0x00000800
315
316/* PC_GUI_CTLSTAT bit constants */
317#define PC_BUSY_INIT 0x10000000
318#define PC_BUSY_GUI 0x20000000
319#define PC_BUSY_NGUI 0x40000000
320#define PC_BUSY 0x80000000
321
322#define BUS_MASTER_DIS 0x00000040
323#define PM4_BUFFER_CNTL_NONPM4 0x00000000
324
325/* DP_DATATYPE bit constants */
326#define DST_8BPP 0x00000002
327#define DST_15BPP 0x00000003
328#define DST_16BPP 0x00000004
329#define DST_24BPP 0x00000005
330#define DST_32BPP 0x00000006
331
332#define BRUSH_SOLIDCOLOR 0x00000d00
333
334/* DP_GUI_MASTER_CNTL bit constants */
335#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
336#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
337#define GMC_SRC_CLIP_DEFAULT 0x00000000
338#define GMC_DST_CLIP_DEFAULT 0x00000000
339#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
340#define GMC_SRC_DSTCOLOR 0x00003000
341#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
342#define GMC_DP_SRC_RECT 0x02000000
343#define GMC_3D_FCN_EN_CLR 0x00000000
344#define GMC_AUX_CLIP_CLEAR 0x20000000
345#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
346#define GMC_WRITE_MASK_SET 0x40000000
347#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
348
349/* DP_GUI_MASTER_CNTL ROP3 named constants */
350#define ROP3_PATCOPY 0x00f00000
351#define ROP3_SRCCOPY 0x00cc0000
352
353#define SRC_DSTCOLOR 0x00030000
354
355/* DP_CNTL bit constants */
356#define DST_X_RIGHT_TO_LEFT 0x00000000
357#define DST_X_LEFT_TO_RIGHT 0x00000001
358#define DST_Y_BOTTOM_TO_TOP 0x00000000
359#define DST_Y_TOP_TO_BOTTOM 0x00000002
360#define DST_X_MAJOR 0x00000000
361#define DST_Y_MAJOR 0x00000004
362#define DST_X_TILE 0x00000008
363#define DST_Y_TILE 0x00000010
364#define DST_LAST_PEL 0x00000020
365#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
366#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
367#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
368#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
369#define DST_BRES_SIGN 0x00000100
370#define DST_HOST_BIG_ENDIAN_EN 0x00000200
371#define DST_POLYLINE_NONLAST 0x00008000
372#define DST_RASTER_STALL 0x00010000
373#define DST_POLY_EDGE 0x00040000
374
375/* DP_MIX bit constants */
376#define DP_SRC_RECT 0x00000200
377#define DP_SRC_HOST 0x00000300
378#define DP_SRC_HOST_BYTEALIGN 0x00000400
379
380/* LVDS_GEN_CNTL constants */
381#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
382#define LVDS_BL_MOD_LEVEL_SHIFT 8
383#define LVDS_BL_MOD_EN 0x00010000
384#define LVDS_DIGION 0x00040000
385#define LVDS_BLON 0x00080000
386#define LVDS_ON 0x00000001
387#define LVDS_DISPLAY_DIS 0x00000002
388#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
389#define LVDS_PANEL_24BITS_TFT 0x00000008
390#define LVDS_FRAME_MOD_NO 0x00000000
391#define LVDS_FRAME_MOD_2_LEVELS 0x00000010
392#define LVDS_FRAME_MOD_4_LEVELS 0x00000020
393#define LVDS_RST_FM 0x00000040
394#define LVDS_EN 0x00000080
395
396/* CRTC2_GEN_CNTL constants */
397#define CRTC2_EN 0x02000000
398
399/* POWER_MANAGEMENT constants */
400#define PWR_MGT_ON 0x00000001
401#define PWR_MGT_MODE_MASK 0x00000006
402#define PWR_MGT_MODE_PIN 0x00000000
403#define PWR_MGT_MODE_REGISTER 0x00000002
404#define PWR_MGT_MODE_TIMER 0x00000004
405#define PWR_MGT_MODE_PCI 0x00000006
406#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
407#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
408#define PWR_MGT_STANDBY_POL 0x00000020
409#define PWR_MGT_SUSPEND_POL 0x00000040
410#define PWR_MGT_SELF_REFRESH 0x00000080
411#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
412#define PWR_MGT_KEYBD_SNOOP 0x00000200
413#define PWR_MGT_TRISTATE_MEM_EN 0x00000800
414#define PWR_MGT_SELW4MS 0x00001000
415#define PWR_MGT_SLOWDOWN_MCLK 0x00002000
416
417#define PMI_PMSCR_REG 0x60
418
419/* used by ATI bug fix for hardware ROM */
420#define RAGE128_MPP_TB_CONFIG 0x01c0
421
422#endif /* REG_RAGE128_H */
diff --git a/include/video/cirrus.h b/include/video/cirrus.h
new file mode 100644
index 000000000000..b2776b6c8679
--- /dev/null
+++ b/include/video/cirrus.h
@@ -0,0 +1,122 @@
1/*
2 * drivers/video/clgenfb.h - Cirrus Logic chipset constants
3 *
4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
5 *
6 * Original clgenfb author: Frank Neumann
7 *
8 * Based on retz3fb.c and clgen.c:
9 * Copyright (C) 1997 Jes Sorensen
10 * Copyright (C) 1996 Frank Neumann
11 *
12 ***************************************************************
13 *
14 * Format this code with GNU indent '-kr -i8 -pcs' options.
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file COPYING in the main directory of this archive
18 * for more details.
19 *
20 */
21
22#ifndef __CLGENFB_H__
23#define __CLGENFB_H__
24
25/* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */
26/* OLD COMMENT: these definitions might most of the time also work */
27/* OLD COMMENT: for other CL-GD542x/543x based boards.. */
28
29/*** External/General Registers ***/
30#define CL_POS102 0x102 /* POS102 register */
31#define CL_VSSM 0x46e8 /* Adapter Sleep */
32#define CL_VSSM2 0x3c3 /* Motherboard Sleep */
33
34/*** VGA Sequencer Registers ***/
35#define CL_SEQR0 0x0 /* Reset */
36/* the following are from the "extension registers" group */
37#define CL_SEQR6 0x6 /* Unlock ALL Extensions */
38#define CL_SEQR7 0x7 /* Extended Sequencer Mode */
39#define CL_SEQR8 0x8 /* EEPROM Control */
40#define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */
41#define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */
42#define CL_SEQRB 0xb /* VCLK0 Numerator */
43#define CL_SEQRC 0xc /* VCLK1 Numerator */
44#define CL_SEQRD 0xd /* VCLK2 Numerator */
45#define CL_SEQRE 0xe /* VCLK3 Numerator */
46#define CL_SEQRF 0xf /* DRAM Control */
47#define CL_SEQR10 0x10 /* Graphics Cursor X Position */
48#define CL_SEQR11 0x11 /* Graphics Cursor Y Position */
49#define CL_SEQR12 0x12 /* Graphics Cursor Attributes */
50#define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */
51#define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
52#define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
53#define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
54#define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */
55#define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */
56#define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */
57#define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */
58#define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */
59#define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */
60#define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */
61#define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */
62#define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */
63
64/*** CRT Controller Registers ***/
65#define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */
66#define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */
67#define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */
68/* the following are from the "extension registers" group */
69#define CL_CRT19 0x19 /* Interlace End */
70#define CL_CRT1A 0x1a /* Interlace Control */
71#define CL_CRT1B 0x1b /* Extended Display Controls */
72#define CL_CRT1C 0x1c /* Sync adjust and genlock register */
73#define CL_CRT1D 0x1d /* Overlay Extended Control register */
74#define CL_CRT25 0x25 /* Part Status Register */
75#define CL_CRT27 0x27 /* ID Register */
76#define CL_CRT51 0x51 /* P4 disable "flicker fixer" */
77
78/*** Graphics Controller Registers ***/
79/* the following are from the "extension registers" group */
80#define CL_GR9 0x9 /* Offset Register 0 */
81#define CL_GRA 0xa /* Offset Register 1 */
82#define CL_GRB 0xb /* Graphics Controller Mode Extensions */
83#define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */
84#define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */
85#define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */
86#define CL_GRF 0xf /* Display Compression Control register */
87#define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */
88#define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */
89#define CL_GR12 0x12 /* Background Color Byte 2 Register */
90#define CL_GR13 0x13 /* Foreground Color Byte 2 Register */
91#define CL_GR14 0x14 /* Background Color Byte 3 Register */
92#define CL_GR15 0x15 /* Foreground Color Byte 3 Register */
93/* the following are CL-GD5426/'28 specific blitter registers */
94#define CL_GR20 0x20 /* BLT Width Low */
95#define CL_GR21 0x21 /* BLT Width High */
96#define CL_GR22 0x22 /* BLT Height Low */
97#define CL_GR23 0x23 /* BLT Height High */
98#define CL_GR24 0x24 /* BLT Destination Pitch Low */
99#define CL_GR25 0x25 /* BLT Destination Pitch High */
100#define CL_GR26 0x26 /* BLT Source Pitch Low */
101#define CL_GR27 0x27 /* BLT Source Pitch High */
102#define CL_GR28 0x28 /* BLT Destination Start Low */
103#define CL_GR29 0x29 /* BLT Destination Start Mid */
104#define CL_GR2A 0x2a /* BLT Destination Start High */
105#define CL_GR2C 0x2c /* BLT Source Start Low */
106#define CL_GR2D 0x2d /* BLT Source Start Mid */
107#define CL_GR2E 0x2e /* BLT Source Start High */
108#define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */
109#define CL_GR30 0x30 /* BLT Mode */
110#define CL_GR31 0x31 /* BLT Start/Status */
111#define CL_GR32 0x32 /* BLT Raster Operation */
112#define CL_GR33 0x33 /* another P4 "compat" register.. */
113#define CL_GR34 0x34 /* Transparent Color Select Low */
114#define CL_GR35 0x35 /* Transparent Color Select High */
115#define CL_GR38 0x38 /* Source Transparent Color Mask Low */
116#define CL_GR39 0x39 /* Source Transparent Color Mask High */
117
118/*** Attribute Controller Registers ***/
119#define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */
120#define CL_AR34 0x34 /* TEST */
121
122#endif /* __CLGENFB_H__ */
diff --git a/include/video/cvisionppc.h b/include/video/cvisionppc.h
new file mode 100644
index 000000000000..11250eee9e98
--- /dev/null
+++ b/include/video/cvisionppc.h
@@ -0,0 +1,51 @@
1/*
2 * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer
3 * driver.
4 *
5 * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
6 * --------------------------------------------------------------------------
7 * $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $
8 * --------------------------------------------------------------------------
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive
11 * for more details.
12 */
13
14#ifndef CVISIONPPC_H
15#define CVISIONPPC_H
16
17#ifndef PM2FB_H
18#include "pm2fb.h"
19#endif
20
21struct cvppc_par {
22 unsigned char* pci_config;
23 unsigned char* pci_bridge;
24 u32 user_flags;
25};
26
27#define CSPPC_PCI_BRIDGE 0xfffe0000
28#define CSPPC_BRIDGE_ENDIAN 0x0000
29#define CSPPC_BRIDGE_INT 0x0010
30
31#define CVPPC_PCI_CONFIG 0xfffc0000
32#define CVPPC_ROM_ADDRESS 0xe2000001
33#define CVPPC_REGS_REGION 0xef000000
34#define CVPPC_FB_APERTURE_ONE 0xe0000000
35#define CVPPC_FB_APERTURE_TWO 0xe1000000
36#define CVPPC_FB_SIZE 0x00800000
37#define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
38#define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */
39#define CVPPC_MEMCLOCK 83000 /* in KHz */
40
41/* CVPPC_BRIDGE_ENDIAN */
42#define CSPPCF_BRIDGE_BIG_ENDIAN 0x02
43
44/* CVPPC_BRIDGE_INT */
45#define CSPPCF_BRIDGE_ACTIVE_INT2 0x01
46
47#endif /* CVISIONPPC_H */
48
49/*****************************************************************************
50 * That's all folks!
51 *****************************************************************************/
diff --git a/include/video/edid.h b/include/video/edid.h
new file mode 100644
index 000000000000..abc1b489c0db
--- /dev/null
+++ b/include/video/edid.h
@@ -0,0 +1,27 @@
1#ifndef __linux_video_edid_h__
2#define __linux_video_edid_h__
3
4#ifdef __KERNEL__
5
6#include <linux/config.h>
7#ifdef CONFIG_PPC_OF
8#include <linux/pci.h>
9#endif
10
11#ifdef CONFIG_X86
12struct edid_info {
13 unsigned char dummy[128];
14};
15
16extern struct edid_info edid_info;
17extern char *get_EDID_from_BIOS(void *);
18
19#endif /* CONFIG_X86 */
20
21#ifdef CONFIG_PPC_OF
22extern char *get_EDID_from_OF(struct pci_dev *pdev);
23#endif
24
25#endif /* __KERNEL__ */
26
27#endif /* __linux_video_edid_h__ */
diff --git a/include/video/epson1355.h b/include/video/epson1355.h
new file mode 100644
index 000000000000..9759f299499e
--- /dev/null
+++ b/include/video/epson1355.h
@@ -0,0 +1,64 @@
1/*
2 * include/video/epson13xx.h -- Epson 13xx frame buffer
3 *
4 * Copyright (C) Hewlett-Packard Company. All rights reserved.
5 *
6 * Written by Christopher Hoover <ch@hpl.hp.com>
7 *
8 */
9
10#ifndef _EPSON13XX_H_
11#define _EPSON13XX_H_
12
13#define REG_REVISION_CODE 0x00
14#define REG_MEMORY_CONFIG 0x01
15#define REG_PANEL_TYPE 0x02
16#define REG_MOD_RATE 0x03
17#define REG_HORZ_DISP_WIDTH 0x04
18#define REG_HORZ_NONDISP_PERIOD 0x05
19#define REG_HRTC_START_POSITION 0x06
20#define REG_HRTC_PULSE_WIDTH 0x07
21#define REG_VERT_DISP_HEIGHT0 0x08
22#define REG_VERT_DISP_HEIGHT1 0x09
23#define REG_VERT_NONDISP_PERIOD 0x0A
24#define REG_VRTC_START_POSITION 0x0B
25#define REG_VRTC_PULSE_WIDTH 0x0C
26#define REG_DISPLAY_MODE 0x0D
27#define REG_SCRN1_LINE_COMPARE0 0x0E
28#define REG_SCRN1_LINE_COMPARE1 0x0F
29#define REG_SCRN1_DISP_START_ADDR0 0x10
30#define REG_SCRN1_DISP_START_ADDR1 0x11
31#define REG_SCRN1_DISP_START_ADDR2 0x12
32#define REG_SCRN2_DISP_START_ADDR0 0x13
33#define REG_SCRN2_DISP_START_ADDR1 0x14
34#define REG_SCRN2_DISP_START_ADDR2 0x15
35#define REG_MEM_ADDR_OFFSET0 0x16
36#define REG_MEM_ADDR_OFFSET1 0x17
37#define REG_PIXEL_PANNING 0x18
38#define REG_CLOCK_CONFIG 0x19
39#define REG_POWER_SAVE_CONFIG 0x1A
40#define REG_MISC 0x1B
41#define REG_MD_CONFIG_READBACK0 0x1C
42#define REG_MD_CONFIG_READBACK1 0x1D
43#define REG_GPIO_CONFIG0 0x1E
44#define REG_GPIO_CONFIG1 0x1F
45#define REG_GPIO_CONTROL0 0x20
46#define REG_GPIO_CONTROL1 0x21
47#define REG_PERF_ENHANCEMENT0 0x22
48#define REG_PERF_ENHANCEMENT1 0x23
49#define REG_LUT_ADDR 0x24
50#define REG_RESERVED_1 0x25
51#define REG_LUT_DATA 0x26
52#define REG_INK_CURSOR_CONTROL 0x27
53#define REG_CURSOR_X_POSITION0 0x28
54#define REG_CURSOR_X_POSITION1 0x29
55#define REG_CURSOR_Y_POSITION0 0x2A
56#define REG_CURSOR_Y_POSITION1 0x2B
57#define REG_INK_CURSOR_COLOR0_0 0x2C
58#define REG_INK_CURSOR_COLOR0_1 0x2D
59#define REG_INK_CURSOR_COLOR1_0 0x2E
60#define REG_INK_CURSOR_COLOR1_1 0x2F
61#define REG_INK_CURSOR_START_ADDR 0x30
62#define REG_ALTERNATE_FRM 0x31
63
64#endif
diff --git a/include/video/gbe.h b/include/video/gbe.h
new file mode 100644
index 000000000000..ad510284f8a6
--- /dev/null
+++ b/include/video/gbe.h
@@ -0,0 +1,317 @@
1/*
2 * include/video/gbe.h -- SGI GBE (Graphics Back End)
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc. (Jeffrey Newquist)
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License version 2 as published by the Free Software Foundation.
8 */
9
10#ifndef __GBE_H__
11#define __GBE_H__
12
13struct sgi_gbe {
14 volatile uint32_t ctrlstat; /* general control */
15 volatile uint32_t dotclock; /* dot clock PLL control */
16 volatile uint32_t i2c; /* crt I2C control */
17 volatile uint32_t sysclk; /* system clock PLL control */
18 volatile uint32_t i2cfp; /* flat panel I2C control */
19 volatile uint32_t id; /* device id/chip revision */
20 volatile uint32_t config; /* power on configuration [1] */
21 volatile uint32_t bist; /* internal bist status [1] */
22 uint32_t _pad0[0x010000/4 - 8];
23 volatile uint32_t vt_xy; /* current dot coords */
24 volatile uint32_t vt_xymax; /* maximum dot coords */
25 volatile uint32_t vt_vsync; /* vsync on/off */
26 volatile uint32_t vt_hsync; /* hsync on/off */
27 volatile uint32_t vt_vblank; /* vblank on/off */
28 volatile uint32_t vt_hblank; /* hblank on/off */
29 volatile uint32_t vt_flags; /* polarity of vt signals */
30 volatile uint32_t vt_f2rf_lock; /* f2rf & framelck y coord */
31 volatile uint32_t vt_intr01; /* intr 0,1 y coords */
32 volatile uint32_t vt_intr23; /* intr 2,3 y coords */
33 volatile uint32_t fp_hdrv; /* flat panel hdrv on/off */
34 volatile uint32_t fp_vdrv; /* flat panel vdrv on/off */
35 volatile uint32_t fp_de; /* flat panel de on/off */
36 volatile uint32_t vt_hpixen; /* intrnl horiz pixel on/off */
37 volatile uint32_t vt_vpixen; /* intrnl vert pixel on/off */
38 volatile uint32_t vt_hcmap; /* cmap write (horiz) */
39 volatile uint32_t vt_vcmap; /* cmap write (vert) */
40 volatile uint32_t did_start_xy; /* eol/f did/xy reset val */
41 volatile uint32_t crs_start_xy; /* eol/f crs/xy reset val */
42 volatile uint32_t vc_start_xy; /* eol/f vc/xy reset val */
43 uint32_t _pad1[0xffb0/4];
44 volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */
45 volatile uint32_t ovr_inhwctrl; /* overlay plane ctrl 1 */
46 volatile uint32_t ovr_control; /* overlay plane ctrl 1 */
47 uint32_t _pad2[0xfff4/4];
48 volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */
49 volatile uint32_t frm_size_pixel;/*normal plane ctrl 1 */
50 volatile uint32_t frm_inhwctrl; /* normal plane ctrl 2 */
51 volatile uint32_t frm_control; /* normal plane ctrl 3 */
52 uint32_t _pad3[0xfff0/4];
53 volatile uint32_t did_inhwctrl; /* DID control */
54 volatile uint32_t did_control; /* DID shadow */
55 uint32_t _pad4[0x7ff8/4];
56 volatile uint32_t mode_regs[32];/* WID table */
57 uint32_t _pad5[0x7f80/4];
58 volatile uint32_t cmap[6144]; /* color map */
59 uint32_t _pad6[0x2000/4];
60 volatile uint32_t cm_fifo; /* color map fifo status */
61 uint32_t _pad7[0x7ffc/4];
62 volatile uint32_t gmap[256]; /* gamma map */
63 uint32_t _pad8[0x7c00/4];
64 volatile uint32_t gmap10[1024]; /* gamma map */
65 uint32_t _pad9[0x7000/4];
66 volatile uint32_t crs_pos; /* cusror control 0 */
67 volatile uint32_t crs_ctl; /* cusror control 1 */
68 volatile uint32_t crs_cmap[3]; /* crs cmap */
69 uint32_t _pad10[0x7fec/4];
70 volatile uint32_t crs_glyph[64];/* crs glyph */
71 uint32_t _pad11[0x7f00/4];
72 volatile uint32_t vc_0; /* video capture crtl 0 */
73 volatile uint32_t vc_1; /* video capture crtl 1 */
74 volatile uint32_t vc_2; /* video capture crtl 2 */
75 volatile uint32_t vc_3; /* video capture crtl 3 */
76 volatile uint32_t vc_4; /* video capture crtl 4 */
77 volatile uint32_t vc_5; /* video capture crtl 5 */
78 volatile uint32_t vc_6; /* video capture crtl 6 */
79 volatile uint32_t vc_7; /* video capture crtl 7 */
80 volatile uint32_t vc_8; /* video capture crtl 8 */
81};
82
83#define MASK(msb, lsb) \
84 ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
85#define GET(v, msb, lsb) \
86 ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
87#define SET(v, f, msb, lsb) \
88 ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
89
90#define GET_GBE_FIELD(reg, field, v) \
91 GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
92#define SET_GBE_FIELD(reg, field, v, f) \
93 SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
94
95/*
96 * Bit mask information
97 */
98#define GBE_CTRLSTAT_CHIPID_MSB 3
99#define GBE_CTRLSTAT_CHIPID_LSB 0
100#define GBE_CTRLSTAT_SENSE_N_MSB 4
101#define GBE_CTRLSTAT_SENSE_N_LSB 4
102#define GBE_CTRLSTAT_PCLKSEL_MSB 29
103#define GBE_CTRLSTAT_PCLKSEL_LSB 28
104
105#define GBE_DOTCLK_M_MSB 7
106#define GBE_DOTCLK_M_LSB 0
107#define GBE_DOTCLK_N_MSB 13
108#define GBE_DOTCLK_N_LSB 8
109#define GBE_DOTCLK_P_MSB 15
110#define GBE_DOTCLK_P_LSB 14
111#define GBE_DOTCLK_RUN_MSB 20
112#define GBE_DOTCLK_RUN_LSB 20
113
114#define GBE_VT_XY_Y_MSB 23
115#define GBE_VT_XY_Y_LSB 12
116#define GBE_VT_XY_X_MSB 11
117#define GBE_VT_XY_X_LSB 0
118#define GBE_VT_XY_FREEZE_MSB 31
119#define GBE_VT_XY_FREEZE_LSB 31
120
121#define GBE_FP_VDRV_ON_MSB 23
122#define GBE_FP_VDRV_ON_LSB 12
123#define GBE_FP_VDRV_OFF_MSB 11
124#define GBE_FP_VDRV_OFF_LSB 0
125
126#define GBE_FP_HDRV_ON_MSB 23
127#define GBE_FP_HDRV_ON_LSB 12
128#define GBE_FP_HDRV_OFF_MSB 11
129#define GBE_FP_HDRV_OFF_LSB 0
130
131#define GBE_FP_DE_ON_MSB 23
132#define GBE_FP_DE_ON_LSB 12
133#define GBE_FP_DE_OFF_MSB 11
134#define GBE_FP_DE_OFF_LSB 0
135
136#define GBE_VT_VSYNC_VSYNC_ON_MSB 23
137#define GBE_VT_VSYNC_VSYNC_ON_LSB 12
138#define GBE_VT_VSYNC_VSYNC_OFF_MSB 11
139#define GBE_VT_VSYNC_VSYNC_OFF_LSB 0
140
141#define GBE_VT_HSYNC_HSYNC_ON_MSB 23
142#define GBE_VT_HSYNC_HSYNC_ON_LSB 12
143#define GBE_VT_HSYNC_HSYNC_OFF_MSB 11
144#define GBE_VT_HSYNC_HSYNC_OFF_LSB 0
145
146#define GBE_VT_VBLANK_VBLANK_ON_MSB 23
147#define GBE_VT_VBLANK_VBLANK_ON_LSB 12
148#define GBE_VT_VBLANK_VBLANK_OFF_MSB 11
149#define GBE_VT_VBLANK_VBLANK_OFF_LSB 0
150
151#define GBE_VT_HBLANK_HBLANK_ON_MSB 23
152#define GBE_VT_HBLANK_HBLANK_ON_LSB 12
153#define GBE_VT_HBLANK_HBLANK_OFF_MSB 11
154#define GBE_VT_HBLANK_HBLANK_OFF_LSB 0
155
156#define GBE_VT_FLAGS_F2RF_HIGH_MSB 6
157#define GBE_VT_FLAGS_F2RF_HIGH_LSB 6
158#define GBE_VT_FLAGS_SYNC_LOW_MSB 5
159#define GBE_VT_FLAGS_SYNC_LOW_LSB 5
160#define GBE_VT_FLAGS_SYNC_HIGH_MSB 4
161#define GBE_VT_FLAGS_SYNC_HIGH_LSB 4
162#define GBE_VT_FLAGS_HDRV_LOW_MSB 3
163#define GBE_VT_FLAGS_HDRV_LOW_LSB 3
164#define GBE_VT_FLAGS_HDRV_INVERT_MSB 2
165#define GBE_VT_FLAGS_HDRV_INVERT_LSB 2
166#define GBE_VT_FLAGS_VDRV_LOW_MSB 1
167#define GBE_VT_FLAGS_VDRV_LOW_LSB 1
168#define GBE_VT_FLAGS_VDRV_INVERT_MSB 0
169#define GBE_VT_FLAGS_VDRV_INVERT_LSB 0
170
171#define GBE_VT_VCMAP_VCMAP_ON_MSB 23
172#define GBE_VT_VCMAP_VCMAP_ON_LSB 12
173#define GBE_VT_VCMAP_VCMAP_OFF_MSB 11
174#define GBE_VT_VCMAP_VCMAP_OFF_LSB 0
175
176#define GBE_VT_HCMAP_HCMAP_ON_MSB 23
177#define GBE_VT_HCMAP_HCMAP_ON_LSB 12
178#define GBE_VT_HCMAP_HCMAP_OFF_MSB 11
179#define GBE_VT_HCMAP_HCMAP_OFF_LSB 0
180
181#define GBE_VT_XYMAX_MAXX_MSB 11
182#define GBE_VT_XYMAX_MAXX_LSB 0
183#define GBE_VT_XYMAX_MAXY_MSB 23
184#define GBE_VT_XYMAX_MAXY_LSB 12
185
186#define GBE_VT_HPIXEN_HPIXEN_ON_MSB 23
187#define GBE_VT_HPIXEN_HPIXEN_ON_LSB 12
188#define GBE_VT_HPIXEN_HPIXEN_OFF_MSB 11
189#define GBE_VT_HPIXEN_HPIXEN_OFF_LSB 0
190
191#define GBE_VT_VPIXEN_VPIXEN_ON_MSB 23
192#define GBE_VT_VPIXEN_VPIXEN_ON_LSB 12
193#define GBE_VT_VPIXEN_VPIXEN_OFF_MSB 11
194#define GBE_VT_VPIXEN_VPIXEN_OFF_LSB 0
195
196#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0
197#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0
198
199#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0
200#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0
201
202#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13
203#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13
204
205#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0
206#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0
207#define GBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31
208#define GBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9
209#define GBE_FRM_CONTROL_FRM_LINEAR_MSB 1
210#define GBE_FRM_CONTROL_FRM_LINEAR_LSB 1
211
212#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0
213#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0
214
215#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12
216#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5
217#define GBE_FRM_SIZE_TILE_FRM_RHS_MSB 4
218#define GBE_FRM_SIZE_TILE_FRM_RHS_LSB 0
219#define GBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14
220#define GBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13
221#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15
222#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15
223
224#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31
225#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16
226
227#define GBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0
228#define GBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0
229#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0
230#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0
231
232#define GBE_DID_START_XY_DID_STARTY_MSB 23
233#define GBE_DID_START_XY_DID_STARTY_LSB 12
234#define GBE_DID_START_XY_DID_STARTX_MSB 11
235#define GBE_DID_START_XY_DID_STARTX_LSB 0
236
237#define GBE_CRS_START_XY_CRS_STARTY_MSB 23
238#define GBE_CRS_START_XY_CRS_STARTY_LSB 12
239#define GBE_CRS_START_XY_CRS_STARTX_MSB 11
240#define GBE_CRS_START_XY_CRS_STARTX_LSB 0
241
242#define GBE_WID_AUX_MSB 12
243#define GBE_WID_AUX_LSB 11
244#define GBE_WID_GAMMA_MSB 10
245#define GBE_WID_GAMMA_LSB 10
246#define GBE_WID_CM_MSB 9
247#define GBE_WID_CM_LSB 5
248#define GBE_WID_TYP_MSB 4
249#define GBE_WID_TYP_LSB 2
250#define GBE_WID_BUF_MSB 1
251#define GBE_WID_BUF_LSB 0
252
253#define GBE_VC_START_XY_VC_STARTY_MSB 23
254#define GBE_VC_START_XY_VC_STARTY_LSB 12
255#define GBE_VC_START_XY_VC_STARTX_MSB 11
256#define GBE_VC_START_XY_VC_STARTX_LSB 0
257
258/* Constants */
259
260#define GBE_FRM_DEPTH_8 0
261#define GBE_FRM_DEPTH_16 1
262#define GBE_FRM_DEPTH_32 2
263
264#define GBE_CMODE_I8 0
265#define GBE_CMODE_I12 1
266#define GBE_CMODE_RG3B2 2
267#define GBE_CMODE_RGB4 3
268#define GBE_CMODE_ARGB5 4
269#define GBE_CMODE_RGB8 5
270#define GBE_CMODE_RGBA5 6
271#define GBE_CMODE_RGB10 7
272
273#define GBE_BMODE_BOTH 3
274
275#define GBE_CRS_MAGIC 54
276#define GBE_PIXEN_MAGIC_ON 19
277#define GBE_PIXEN_MAGIC_OFF 2
278
279#define GBE_TLB_SIZE 128
280
281/* [1] - only GBE revision 2 and later */
282
283/*
284 * Video Timing Data Structure
285 */
286
287struct gbe_timing_info {
288 int flags;
289 short width; /* Monitor resolution */
290 short height;
291 int fields_sec; /* fields/sec (Hz -3 dec. places */
292 int cfreq; /* pixel clock frequency (MHz -3 dec. places) */
293 short htotal; /* Horizontal total pixels */
294 short hblank_start; /* Horizontal blank start */
295 short hblank_end; /* Horizontal blank end */
296 short hsync_start; /* Horizontal sync start */
297 short hsync_end; /* Horizontal sync end */
298 short vtotal; /* Vertical total lines */
299 short vblank_start; /* Vertical blank start */
300 short vblank_end; /* Vertical blank end */
301 short vsync_start; /* Vertical sync start */
302 short vsync_end; /* Vertical sync end */
303 short pll_m; /* PLL M parameter */
304 short pll_n; /* PLL P parameter */
305 short pll_p; /* PLL N parameter */
306};
307
308/* Defines for gbe_vof_info_t flags */
309
310#define GBE_VOF_UNKNOWNMON 1
311#define GBE_VOF_STEREO 2
312#define GBE_VOF_DO_GENSYNC 4 /* enable incoming sync */
313#define GBE_VOF_SYNC_ON_GREEN 8 /* sync on green */
314#define GBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */
315#define GBE_VOF_MAGICKEY 0x2000 /* Backdoor key */
316
317#endif /* ! __GBE_H__ */
diff --git a/include/video/iga.h b/include/video/iga.h
new file mode 100644
index 000000000000..5a48f16578f8
--- /dev/null
+++ b/include/video/iga.h
@@ -0,0 +1,24 @@
1/* $Id: iga.h,v 1.2 1999/09/11 22:56:31 zaitcev Exp $
2 * iga1682.h: Sparc/PCI iga1682 driver constants etc.
3 *
4 * Copyleft 1998 V. Roganov and G. Raiko
5 */
6
7#ifndef _IGA1682_H
8#define _IGA1682_H 1
9
10#define IGA_ATTR_CTL 0x3C0
11#define IGA_IDX_VGA_OVERSCAN 0x11
12#define DAC_W_INDEX 0x03C8
13#define DAC_DATA 0x03C9
14#define IGA_EXT_CNTRL 0x3CE
15#define IGA_IDX_EXT_BUS_CNTL 0x30
16#define MEM_SIZE_ALIAS 0x3
17#define MEM_SIZE_1M 0x0
18#define MEM_SIZE_2M 0x1
19#define MEM_SIZE_4M 0x2
20#define MEM_SIZE_RESERVED 0x3
21#define IGA_IDX_OVERSCAN_COLOR 0x58
22#define IGA_IDX_EXT_MEM_2 0x72
23
24#endif /* !(_IGA1682_H) */
diff --git a/include/video/kyro.h b/include/video/kyro.h
new file mode 100644
index 000000000000..1bed37cfa68c
--- /dev/null
+++ b/include/video/kyro.h
@@ -0,0 +1,92 @@
1/*
2 * linux/drivers/video/kyro/kryo.h
3 *
4 * Copyright (C) 2002 STMicroelectronics
5 * Copyright (C) 2004 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 */
11
12#ifndef _KYRO_H
13#define _KYRO_H
14
15struct kyrofb_info {
16 void __iomem *regbase;
17
18 u32 HTot; /* Hor Total Time */
19 u32 HFP; /* Hor Front Porch */
20 u32 HST; /* Hor Sync Time */
21 u32 HBP; /* Hor Back Porch */
22 s32 HSP; /* Hor Sync Polarity */
23 u32 VTot; /* Ver Total Time */
24 u32 VFP; /* Ver Front Porch */
25 u32 VST; /* Ver Sync Time */
26 u32 VBP; /* Ver Back Porch */
27 s32 VSP; /* Ver Sync Polarity */
28 u32 XRES; /* X Resolution */
29 u32 YRES; /* Y Resolution */
30 u32 VFREQ; /* Ver Frequency */
31 u32 PIXCLK; /* Pixel Clock */
32 u32 HCLK; /* Hor Clock */
33
34 /* Usefull to hold depth here for Linux */
35 u8 PIXDEPTH;
36
37#ifdef CONFIG_MTRR
38 int mtrr_handle;
39#endif
40};
41
42extern int kyro_dev_init(void);
43extern void kyro_dev_reset(void);
44
45extern unsigned char *kyro_dev_physical_fb_ptr(void);
46extern unsigned char *kyro_dev_virtual_fb_ptr(void);
47extern void *kyro_dev_physical_regs_ptr(void);
48extern void *kyro_dev_virtual_regs_ptr(void);
49extern unsigned int kyro_dev_fb_size(void);
50extern unsigned int kyro_dev_regs_size(void);
51
52extern u32 kyro_dev_overlay_offset(void);
53
54/*
55 * benedict.gaster@superh.com
56 * Added the follow IOCTLS for the creation of overlay services...
57 */
58#define KYRO_IOC_MAGIC 'k'
59
60#define KYRO_IOCTL_OVERLAY_CREATE _IO(KYRO_IOC_MAGIC, 0)
61#define KYRO_IOCTL_OVERLAY_VIEWPORT_SET _IO(KYRO_IOC_MAGIC, 1)
62#define KYRO_IOCTL_SET_VIDEO_MODE _IO(KYRO_IOC_MAGIC, 2)
63#define KYRO_IOCTL_UVSTRIDE _IO(KYRO_IOC_MAGIC, 3)
64#define KYRO_IOCTL_OVERLAY_OFFSET _IO(KYRO_IOC_MAGIC, 4)
65#define KYRO_IOCTL_STRIDE _IO(KYRO_IOC_MAGIC, 5)
66
67/*
68 * The follow 3 structures are used to pass data from user space into the kernel
69 * for the creation of overlay surfaces and setting the video mode.
70 */
71typedef struct _OVERLAY_CREATE {
72 u32 ulWidth;
73 u32 ulHeight;
74 int bLinear;
75} overlay_create;
76
77typedef struct _OVERLAY_VIEWPORT_SET {
78 u32 xOrgin;
79 u32 yOrgin;
80 u32 xSize;
81 u32 ySize;
82} overlay_viewport_set;
83
84typedef struct _SET_VIDEO_MODE {
85 u32 ulWidth;
86 u32 ulHeight;
87 u32 ulScan;
88 u8 displayDepth;
89 int bLinear;
90} set_video_mode;
91
92#endif /* _KYRO_H */
diff --git a/include/video/mach64.h b/include/video/mach64.h
new file mode 100644
index 000000000000..09a7f4a7289f
--- /dev/null
+++ b/include/video/mach64.h
@@ -0,0 +1,1377 @@
1/*
2 * ATI Mach64 Register Definitions
3 *
4 * Copyright (C) 1997 Michael AK Tesch
5 * written with much help from Jon Howell
6 *
7 * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15/*
16 * most of the rest of this file comes from ATI sample code
17 */
18#ifndef REGMACH64_H
19#define REGMACH64_H
20
21/* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
22
23/* Accelerator CRTC */
24#define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
25#define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
26#define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
27#define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
28#define CRTC_H_SYNC_STRT 0x0004
29#define CRTC2_H_SYNC_STRT 0x0004
30#define CRTC_H_SYNC_DLY 0x0005
31#define CRTC2_H_SYNC_DLY 0x0005
32#define CRTC_H_SYNC_WID 0x0006
33#define CRTC2_H_SYNC_WID 0x0006
34#define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
35#define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
36#define CRTC_V_TOTAL 0x0008
37#define CRTC2_V_TOTAL 0x0008
38#define CRTC_V_DISP 0x000A
39#define CRTC2_V_DISP 0x000A
40#define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
41#define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
42#define CRTC_V_SYNC_STRT 0x000C
43#define CRTC2_V_SYNC_STRT 0x000C
44#define CRTC_V_SYNC_WID 0x000E
45#define CRTC2_V_SYNC_WID 0x000E
46#define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
47#define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
48#define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */
49#define CRTC_OFFSET 0x0014
50#define CRTC_PITCH 0x0016
51#define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */
52#define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */
53#define CRTC_PIX_WIDTH 0x001D
54#define CRTC_FIFO 0x001E
55#define CRTC_EXT_DISP 0x001F
56
57/* Memory Buffer Control */
58#define DSP_CONFIG 0x0020 /* Dword offset 0_08 */
59#define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */
60#define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */
61#define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */
62#define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */
63#define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */
64#define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */
65
66/* Accelerator CRTC */
67#define CRT_TRAP 0x0038 /* Dword offset 0_0E */
68
69#define I2C_CNTL_0 0x003C /* Dword offset 0_0F */
70
71#define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */
72
73/* Overscan */
74#define OVR_CLR 0x0040 /* Dword offset 0_10 */
75#define OVR2_CLR 0x0040 /* Dword offset 0_10 */
76#define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
77#define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
78#define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
79#define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
80
81/* Memory Buffer Control */
82#define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */
83#define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */
84#define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */
85#define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */
86#define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */
87#define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */
88#define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */
89#define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */
90
91/* Accelerator CRTC */
92#define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */
93
94/* Hardware Cursor */
95#define CUR_CLR0 0x0060 /* Dword offset 0_18 */
96#define CUR2_CLR0 0x0060 /* Dword offset 0_18 */
97#define CUR_CLR1 0x0064 /* Dword offset 0_19 */
98#define CUR2_CLR1 0x0064 /* Dword offset 0_19 */
99#define CUR_OFFSET 0x0068 /* Dword offset 0_1A */
100#define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */
101#define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
102#define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
103#define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
104#define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
105
106#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
107
108/* General I/O Control */
109#define GP_IO 0x0078 /* Dword offset 0_1E */
110
111/* Test and Debug */
112#define HW_DEBUG 0x007C /* Dword offset 0_1F */
113
114/* Scratch Pad and Test */
115#define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */
116#define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */
117#define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */
118#define SCRATCH_REG3 0x008C /* Dword offset 0_23 */
119
120/* Clock Control */
121#define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */
122/* CLOCK_CNTL register constants CT LAYOUT */
123#define CLOCK_SEL 0x0f
124#define CLOCK_SEL_INTERNAL 0x03
125#define CLOCK_SEL_EXTERNAL 0x0c
126#define CLOCK_DIV 0x30
127#define CLOCK_DIV1 0x00
128#define CLOCK_DIV2 0x10
129#define CLOCK_DIV4 0x20
130#define CLOCK_STROBE 0x40
131/* ? 0x80 */
132/* CLOCK_CNTL register constants GX LAYOUT */
133#define CLOCK_BIT 0x04 /* For ICS2595 */
134#define CLOCK_PULSE 0x08 /* For ICS2595 */
135/*#define CLOCK_STROBE 0x40 dito as CT */
136#define CLOCK_DATA 0x80
137
138/* For internal PLL(CT) start */
139#define CLOCK_CNTL_ADDR CLOCK_CNTL + 1
140#define PLL_WR_EN 0x02
141#define PLL_ADDR 0xfc
142#define CLOCK_CNTL_DATA CLOCK_CNTL + 2
143#define PLL_DATA 0xff
144/* For internal PLL(CT) end */
145
146#define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
147
148/* Configuration */
149#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
150#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
151
152/* Bus Control */
153#define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
154
155#define LCD_INDEX 0x00A4 /* Dword offset 0_29 */
156#define LCD_DATA 0x00A8 /* Dword offset 0_2A */
157
158#define HFB_PITCH_ADDR_LG 0x00A8 /* Dword offset 0_2A (LG) */
159
160/* Memory Control */
161#define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */
162#define MEM_CNTL 0x00B0 /* Dword offset 0_2C */
163#define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */
164#define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */
165
166#define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */
167
168#define LT_GIO_LG 0x00BC /* Dword offset 0_2F (LG) */
169
170/* DAC Control */
171#define DAC_REGS 0x00C0 /* Dword offset 0_30 */
172#define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */
173#define DAC_DATA 0x00C1 /* Dword offset 0_30 */
174#define DAC_MASK 0x00C2 /* Dword offset 0_30 */
175#define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */
176#define DAC_CNTL 0x00C4 /* Dword offset 0_31 */
177
178#define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */
179
180#define HORZ_STRETCHING_LG 0x00C8 /* Dword offset 0_32 (LG) */
181#define VERT_STRETCHING_LG 0x00CC /* Dword offset 0_33 (LG) */
182
183/* Test and Debug */
184#define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */
185
186/* Custom Macros */
187#define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */
188
189#define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 (LG) */
190#define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
191
192/* Configuration */
193#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
194#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
195#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
196
197/* Test and Debug */
198#define CRC_SIG 0x00E8 /* Dword offset 0_3A */
199#define CRC2_SIG 0x00E8 /* Dword offset 0_3A */
200
201
202/* GUI MEMORY MAPPED Registers */
203
204/* Draw Engine Destination Trajectory */
205#define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */
206#define DST_X 0x0104 /* Dword offset 0_41 */
207#define DST_Y 0x0108 /* Dword offset 0_42 */
208#define DST_Y_X 0x010C /* Dword offset 0_43 */
209#define DST_WIDTH 0x0110 /* Dword offset 0_44 */
210#define DST_HEIGHT 0x0114 /* Dword offset 0_45 */
211#define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */
212#define DST_X_WIDTH 0x011C /* Dword offset 0_47 */
213#define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */
214#define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */
215#define DST_BRES_INC 0x0128 /* Dword offset 0_4A */
216#define DST_BRES_DEC 0x012C /* Dword offset 0_4B */
217#define DST_CNTL 0x0130 /* Dword offset 0_4C */
218#define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */
219#define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */
220#define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */
221#define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */
222#define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */
223#define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */
224#define Z_CNTL 0x014C /* Dword offset 0_53 */
225#define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */
226#define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */
227#define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */
228#define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */
229#define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */
230#define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */
231#define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */
232#define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */
233#define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */
234#define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */
235#define SECONDARY_T_START 0x017C /* Dword offset 0_5F */
236
237/* Draw Engine Source Trajectory */
238#define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */
239#define SRC_X 0x0184 /* Dword offset 0_61 */
240#define SRC_Y 0x0188 /* Dword offset 0_62 */
241#define SRC_Y_X 0x018C /* Dword offset 0_63 */
242#define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */
243#define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */
244#define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */
245#define SRC_X_START 0x019C /* Dword offset 0_67 */
246#define SRC_Y_START 0x01A0 /* Dword offset 0_68 */
247#define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */
248#define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */
249#define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */
250#define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */
251#define SRC_CNTL 0x01B4 /* Dword offset 0_6D */
252
253#define SCALE_OFF 0x01C0 /* Dword offset 0_70 */
254#define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */
255
256#define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */
257#define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */
258#define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */
259#define TEX_3_OFF 0x01CC /* Dword offset 0_73 */
260#define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */
261#define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */
262#define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */
263#define TEX_7_OFF 0x01DC /* Dword offset 0_77 */
264
265#define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */
266#define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */
267
268#define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */
269#define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */
270#define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */
271#define S_Y_INC 0x01EC /* Dword offset 0_7B */
272
273#define SCALE_PITCH 0x01EC /* Dword offset 0_7B */
274#define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */
275
276#define RED_X_INC 0x01F0 /* Dword offset 0_7C */
277#define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */
278
279#define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */
280#define SCALE_VACC 0x01F8 /* Dword offset 0_7E */
281#define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */
282
283/* Host Data */
284#define HOST_DATA0 0x0200 /* Dword offset 0_80 */
285#define HOST_DATA1 0x0204 /* Dword offset 0_81 */
286#define HOST_DATA2 0x0208 /* Dword offset 0_82 */
287#define HOST_DATA3 0x020C /* Dword offset 0_83 */
288#define HOST_DATA4 0x0210 /* Dword offset 0_84 */
289#define HOST_DATA5 0x0214 /* Dword offset 0_85 */
290#define HOST_DATA6 0x0218 /* Dword offset 0_86 */
291#define HOST_DATA7 0x021C /* Dword offset 0_87 */
292#define HOST_DATA8 0x0220 /* Dword offset 0_88 */
293#define HOST_DATA9 0x0224 /* Dword offset 0_89 */
294#define HOST_DATAA 0x0228 /* Dword offset 0_8A */
295#define HOST_DATAB 0x022C /* Dword offset 0_8B */
296#define HOST_DATAC 0x0230 /* Dword offset 0_8C */
297#define HOST_DATAD 0x0234 /* Dword offset 0_8D */
298#define HOST_DATAE 0x0238 /* Dword offset 0_8E */
299#define HOST_DATAF 0x023C /* Dword offset 0_8F */
300#define HOST_CNTL 0x0240 /* Dword offset 0_90 */
301
302/* GUI Bus Mastering */
303#define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */
304#define BM_ADDR 0x0248 /* Dword offset 0_92 */
305#define BM_DATA 0x0248 /* Dword offset 0_92 */
306#define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */
307
308/* Pattern */
309#define PAT_REG0 0x0280 /* Dword offset 0_A0 */
310#define PAT_REG1 0x0284 /* Dword offset 0_A1 */
311#define PAT_CNTL 0x0288 /* Dword offset 0_A2 */
312
313/* Scissors */
314#define SC_LEFT 0x02A0 /* Dword offset 0_A8 */
315#define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */
316#define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */
317#define SC_TOP 0x02AC /* Dword offset 0_AB */
318#define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */
319#define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */
320
321/* Data Path */
322#define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */
323#define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */
324#define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */
325#define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */
326#define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */
327#define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */
328#define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */
329#define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */
330#define DP_MIX 0x02D4 /* Dword offset 0_B5 */
331#define DP_SRC 0x02D8 /* Dword offset 0_B6 */
332#define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */
333#define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */
334
335/* Draw Engine Destination Trajectory */
336#define DST_X_Y 0x02E8 /* Dword offset 0_BA */
337#define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */
338
339/* Data Path */
340#define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */
341#define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */
342#define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */
343
344/* Color Compare */
345#define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */
346#define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */
347#define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */
348
349/* Command FIFO */
350#define FIFO_STAT 0x0310 /* Dword offset 0_C4 */
351
352#define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */
353#define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */
354
355/* Engine Control */
356#define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */
357
358/* Engine Status/FIFO */
359#define GUI_STAT 0x0338 /* Dword offset 0_CE */
360
361#define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */
362#define STW_EXP 0x0344 /* Dword offset 0_D1 */
363#define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */
364#define S_X_INC 0x034C /* Dword offset 0_D3 */
365#define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */
366
367#define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */
368
369#define S_START 0x0354 /* Dword offset 0_D5 */
370#define W_X_INC 0x0358 /* Dword offset 0_D6 */
371#define W_Y_INC 0x035C /* Dword offset 0_D7 */
372#define W_START 0x0360 /* Dword offset 0_D8 */
373#define T_X_INC 0x0364 /* Dword offset 0_D9 */
374#define T_Y_INC 0x0368 /* Dword offset 0_DA */
375
376#define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */
377
378#define T_START 0x036C /* Dword offset 0_DB */
379#define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */
380#define TEX_CNTL 0x0374 /* Dword offset 0_DD */
381#define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */
382#define TEX_PALETTE 0x037C /* Dword offset 0_DF */
383
384#define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */
385#define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */
386#define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */
387#define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */
388
389/* Draw Engine Destination Trajectory */
390#define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */
391
392#define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */
393
394#define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */
395#define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */
396#define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */
397
398#define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */
399
400#define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */
401#define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */
402#define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */
403#define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */
404#define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */
405#define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */
406
407#define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
408
409#define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
410#define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */
411#define RED_START 0x03C8 /* Dword offset 0_F2 */
412
413#define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */
414#define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
415
416#define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
417#define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */
418
419#define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */
420#define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */
421
422#define GREEN_START 0x03D4 /* Dword offset 0_F5 */
423#define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */
424#define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */
425#define BLUE_START 0x03E0 /* Dword offset 0_F8 */
426#define Z_X_INC 0x03E4 /* Dword offset 0_F9 */
427#define Z_Y_INC 0x03E8 /* Dword offset 0_FA */
428#define Z_START 0x03EC /* Dword offset 0_FB */
429#define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */
430#define FOG_X_INC 0x03F0 /* Dword offset 0_FC */
431#define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */
432#define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */
433#define ALPHA_START 0x03F8 /* Dword offset 0_FE */
434#define FOG_START 0x03F8 /* Dword offset 0_FE */
435
436#define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */
437#define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */
438#define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */
439#define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */
440#define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */
441#define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */
442#define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */
443
444#define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */
445#define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */
446#define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */
447#define SCALER_TEST 0x042C /* Dword offset 1_0B */
448#define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */
449#define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */
450#define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */
451
452#define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */
453#define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */
454#define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */
455#define VBI_START_END 0x044C /* Dword offset 1_13 */
456#define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */
457#define TRIG_CNTL 0x0454 /* Dword offset 1_15 */
458
459#define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */
460#define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */
461
462#define VAL_WIDTH 0x0460 /* Dword offset 1_18 */
463#define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */
464#define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */
465
466/* GenLocking */
467#define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */
468#define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */
469#define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */
470#define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */
471
472#define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */
473#define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */
474#define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */
475
476/* GenLocking */
477#define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */
478#define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */
479#define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */
480#define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */
481
482#define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */
483#define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */
484#define MPP_ADDR 0x04C8 /* Dword offset 1_32 */
485#define MPP_DATA 0x04CC /* Dword offset 1_33 */
486#define TVO_CNTL 0x0500 /* Dword offset 1_40 */
487
488/* Test and Debug */
489#define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */
490
491/* AGP */
492#define AGP_BASE 0x0548 /* Dword offset 1_52 */
493#define AGP_CNTL 0x054C /* Dword offset 1_53 */
494
495#define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */
496#define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */
497#define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */
498#define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */
499#define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */
500#define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */
501
502/* Command FIFO */
503#define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */
504#define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */
505#define GUI_CNTL 0x0578 /* Dword offset 1_5E */
506
507/* Bus Mastering */
508#define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */
509#define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */
510#define BM_COMMAND 0x0588 /* Dword offset 1_62 */
511#define BM_STATUS 0x058C /* Dword offset 1_63 */
512#define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */
513#define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */
514
515#define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */
516#define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */
517#define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */
518#define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */
519
520/* Setup Engine */
521#define VERTEX_1_S 0x0640 /* Dword offset 1_90 */
522#define VERTEX_1_T 0x0644 /* Dword offset 1_91 */
523#define VERTEX_1_W 0x0648 /* Dword offset 1_92 */
524#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */
525#define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */
526#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */
527#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */
528#define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */
529#define VERTEX_2_S 0x0660 /* Dword offset 1_98 */
530#define VERTEX_2_T 0x0664 /* Dword offset 1_99 */
531#define VERTEX_2_W 0x0668 /* Dword offset 1_9A */
532#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */
533#define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */
534#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */
535#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */
536#define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */
537#define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */
538#define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */
539#define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */
540#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */
541#define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */
542#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */
543#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */
544#define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */
545#define VERTEX_1_S 0x0640 /* Dword offset 1_AB */
546#define VERTEX_1_T 0x0644 /* Dword offset 1_AC */
547#define VERTEX_1_W 0x0648 /* Dword offset 1_AD */
548#define VERTEX_2_S 0x0660 /* Dword offset 1_AE */
549#define VERTEX_2_T 0x0664 /* Dword offset 1_AF */
550#define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */
551#define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */
552#define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */
553#define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */
554#define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */
555#define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */
556#define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */
557#define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */
558#define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */
559#define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */
560#define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */
561#define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */
562#define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */
563#define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */
564#define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */
565#define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */
566#define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */
567#define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */
568#define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */
569#define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */
570#define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */
571#define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */
572#define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */
573#define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */
574#define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */
575#define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */
576#define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */
577
578
579#define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */
580
581/* CRTC control values (mostly CRTC_GEN_CNTL) */
582
583#define CRTC_H_SYNC_NEG 0x00200000
584#define CRTC_V_SYNC_NEG 0x00200000
585
586#define CRTC_DBL_SCAN_EN 0x00000001
587#define CRTC_INTERLACE_EN 0x00000002
588#define CRTC_HSYNC_DIS 0x00000004
589#define CRTC_VSYNC_DIS 0x00000008
590#define CRTC_CSYNC_EN 0x00000010
591#define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */
592#define CRTC_DISPLAY_DIS 0x00000040
593#define CRTC_VGA_XOVERSCAN 0x00000080
594
595#define CRTC_PIX_WIDTH_MASK 0x00000700
596#define CRTC_PIX_WIDTH_4BPP 0x00000100
597#define CRTC_PIX_WIDTH_8BPP 0x00000200
598#define CRTC_PIX_WIDTH_15BPP 0x00000300
599#define CRTC_PIX_WIDTH_16BPP 0x00000400
600#define CRTC_PIX_WIDTH_24BPP 0x00000500
601#define CRTC_PIX_WIDTH_32BPP 0x00000600
602
603#define CRTC_BYTE_PIX_ORDER 0x00000800
604#define CRTC_PIX_ORDER_MSN_LSN 0x00000000
605#define CRTC_PIX_ORDER_LSN_MSN 0x00000800
606
607#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */
608#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */
609#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */
610#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */
611#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */
612
613#define CRTC_FIFO_LWM 0x000f0000
614#define CRTC_HVSYNC_IO_DRIVE 0x00010000 /* XC/XL */
615#define CRTC2_PIX_WIDTH 0x000e0000 /* LTPro */
616
617#define CRTC_VGA_128KAP_PAGING 0x00100000
618#define CRTC_VFC_SYNC_TRISTATE 0x00200000 /* VTB/GTB/LT */
619#define CRTC2_EN 0x00200000 /* LTPro */
620#define CRTC_LOCK_REGS 0x00400000
621#define CRTC_SYNC_TRISTATE 0x00800000
622
623#define CRTC_EXT_DISP_EN 0x01000000
624#define CRTC_EN 0x02000000
625#define CRTC_DISP_REQ_EN 0x04000000
626#define CRTC_VGA_LINEAR 0x08000000
627#define CRTC_VSYNC_FALL_EDGE 0x10000000
628#define CRTC_VGA_TEXT_132 0x20000000
629#define CRTC_CNT_EN 0x40000000
630#define CRTC_CUR_B_TEST 0x80000000
631
632#define CRTC_CRNT_VLINE 0x07f00000
633
634#define CRTC_PRESERVED_MASK 0x0001f000
635
636#define CRTC_VBLANK 0x00000001
637#define CRTC_VBLANK_INT_EN 0x00000002
638#define CRTC_VBLANK_INT 0x00000004
639#define CRTC_VBLANK_INT_AK CRTC_VBLANK_INT
640#define CRTC_VLINE_INT_EN 0x00000008
641#define CRTC_VLINE_INT 0x00000010
642#define CRTC_VLINE_INT_AK CRTC_VLINE_INT
643#define CRTC_VLINE_SYNC 0x00000020
644#define CRTC_FRAME 0x00000040
645#define SNAPSHOT_INT_EN 0x00000080
646#define SNAPSHOT_INT 0x00000100
647#define SNAPSHOT_INT_AK SNAPSHOT_INT
648#define I2C_INT_EN 0x00000200
649#define I2C_INT 0x00000400
650#define I2C_INT_AK I2C_INT
651#define CRTC2_VBLANK 0x00000800
652#define CRTC2_VBLANK_INT_EN 0x00001000
653#define CRTC2_VBLANK_INT 0x00002000
654#define CRTC2_VBLANK_INT_AK CRTC2_VBLANK_INT
655#define CRTC2_VLINE_INT_EN 0x00004000
656#define CRTC2_VLINE_INT 0x00008000
657#define CRTC2_VLINE_INT_AK CRTC2_VLINE_INT
658#define CAPBUF0_INT_EN 0x00010000
659#define CAPBUF0_INT 0x00020000
660#define CAPBUF0_INT_AK CAPBUF0_INT
661#define CAPBUF1_INT_EN 0x00040000
662#define CAPBUF1_INT 0x00080000
663#define CAPBUF1_INT_AK CAPBUF1_INT
664#define OVERLAY_EOF_INT_EN 0x00100000
665#define OVERLAY_EOF_INT 0x00200000
666#define OVERLAY_EOF_INT_AK OVERLAY_EOF_INT
667#define ONESHOT_CAP_INT_EN 0x00400000
668#define ONESHOT_CAP_INT 0x00800000
669#define ONESHOT_CAP_INT_AK ONESHOT_CAP_INT
670#define BUSMASTER_EOL_INT_EN 0x01000000
671#define BUSMASTER_EOL_INT 0x02000000
672#define BUSMASTER_EOL_INT_AK BUSMASTER_EOL_INT
673#define GP_INT_EN 0x04000000
674#define GP_INT 0x08000000
675#define GP_INT_AK GP_INT
676#define CRTC2_VLINE_SYNC 0x10000000
677#define SNAPSHOT2_INT_EN 0x20000000
678#define SNAPSHOT2_INT 0x40000000
679#define SNAPSHOT2_INT_AK SNAPSHOT2_INT
680#define VBLANK_BIT2_INT 0x80000000
681#define VBLANK_BIT2_INT_AK VBLANK_BIT2_INT
682
683#define CRTC_INT_EN_MASK (CRTC_VBLANK_INT_EN | \
684 CRTC_VLINE_INT_EN | \
685 SNAPSHOT_INT_EN | \
686 I2C_INT_EN | \
687 CRTC2_VBLANK_INT_EN | \
688 CRTC2_VLINE_INT_EN | \
689 CAPBUF0_INT_EN | \
690 CAPBUF1_INT_EN | \
691 OVERLAY_EOF_INT_EN | \
692 ONESHOT_CAP_INT_EN | \
693 BUSMASTER_EOL_INT_EN | \
694 GP_INT_EN | \
695 SNAPSHOT2_INT_EN)
696
697/* DAC control values */
698
699#define DAC_EXT_SEL_RS2 0x01
700#define DAC_EXT_SEL_RS3 0x02
701#define DAC_8BIT_EN 0x00000100
702#define DAC_PIX_DLY_MASK 0x00000600
703#define DAC_PIX_DLY_0NS 0x00000000
704#define DAC_PIX_DLY_2NS 0x00000200
705#define DAC_PIX_DLY_4NS 0x00000400
706#define DAC_BLANK_ADJ_MASK 0x00001800
707#define DAC_BLANK_ADJ_0 0x00000000
708#define DAC_BLANK_ADJ_1 0x00000800
709#define DAC_BLANK_ADJ_2 0x00001000
710
711/* DAC control values (my source XL/XC Register reference) */
712#define DAC_OUTPUT_MASK 0x00000001 /* 0 - PAL, 1 - NTSC */
713#define DAC_MISTERY_BIT 0x00000002 /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */
714#define DAC_BLANKING 0x00000004
715#define DAC_CMP_DISABLE 0x00000008
716#define DAC1_CLK_SEL 0x00000010
717#define PALETTE_ACCESS_CNTL 0x00000020
718#define PALETTE2_SNOOP_EN 0x00000040
719#define DAC_CMP_OUTPUT 0x00000080 /* read only */
720/* #define DAC_8BIT_EN is ok */
721#define CRT_SENSE 0x00000800 /* read only */
722#define CRT_DETECTION_ON 0x00001000
723#define DAC_VGA_ADR_EN 0x00002000
724#define DAC_FEA_CON_EN 0x00004000
725#define DAC_PDWN 0x00008000
726#define DAC_TYPE_MASK 0x00070000 /* read only */
727
728
729
730/* Mix control values */
731
732#define MIX_NOT_DST 0x0000
733#define MIX_0 0x0001
734#define MIX_1 0x0002
735#define MIX_DST 0x0003
736#define MIX_NOT_SRC 0x0004
737#define MIX_XOR 0x0005
738#define MIX_XNOR 0x0006
739#define MIX_SRC 0x0007
740#define MIX_NAND 0x0008
741#define MIX_NOT_SRC_OR_DST 0x0009
742#define MIX_SRC_OR_NOT_DST 0x000a
743#define MIX_OR 0x000b
744#define MIX_AND 0x000c
745#define MIX_SRC_AND_NOT_DST 0x000d
746#define MIX_NOT_SRC_AND_DST 0x000e
747#define MIX_NOR 0x000f
748
749/* Maximum engine dimensions */
750#define ENGINE_MIN_X 0
751#define ENGINE_MIN_Y 0
752#define ENGINE_MAX_X 4095
753#define ENGINE_MAX_Y 16383
754
755/* Mach64 engine bit constants - these are typically ORed together */
756
757/* BUS_CNTL register constants */
758#define BUS_APER_REG_DIS 0x00000010
759#define BUS_FIFO_ERR_ACK 0x00200000
760#define BUS_HOST_ERR_ACK 0x00800000
761
762/* GEN_TEST_CNTL register constants */
763#define GEN_OVR_OUTPUT_EN 0x20
764#define HWCURSOR_ENABLE 0x80
765#define GUI_ENGINE_ENABLE 0x100
766#define BLOCK_WRITE_ENABLE 0x200
767
768/* DSP_CONFIG register constants */
769#define DSP_XCLKS_PER_QW 0x00003fff
770#define DSP_LOOP_LATENCY 0x000f0000
771#define DSP_PRECISION 0x00700000
772
773/* DSP_ON_OFF register constants */
774#define DSP_OFF 0x000007ff
775#define DSP_ON 0x07ff0000
776#define VGA_DSP_OFF DSP_OFF
777#define VGA_DSP_ON DSP_ON
778#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW
779
780/* PLL register indices and fields */
781#define MPLL_CNTL 0x00
782#define PLL_PC_GAIN 0x07
783#define PLL_VC_GAIN 0x18
784#define PLL_DUTY_CYC 0xE0
785#define VPLL_CNTL 0x01
786#define PLL_REF_DIV 0x02
787#define PLL_GEN_CNTL 0x03
788#define PLL_OVERRIDE 0x01 /* PLL_SLEEP */
789#define PLL_MCLK_RST 0x02 /* PLL_MRESET */
790#define OSC_EN 0x04
791#define EXT_CLK_EN 0x08
792#define FORCE_DCLK_TRI_STATE 0x08 /* VT4 -> */
793#define MCLK_SRC_SEL 0x70
794#define EXT_CLK_CNTL 0x80
795#define DLL_PWDN 0x80 /* VT4 -> */
796#define MCLK_FB_DIV 0x04
797#define PLL_VCLK_CNTL 0x05
798#define PLL_VCLK_SRC_SEL 0x03
799#define PLL_VCLK_RST 0x04
800#define PLL_VCLK_INVERT 0x08
801#define VCLK_POST_DIV 0x06
802#define VCLK0_POST 0x03
803#define VCLK1_POST 0x0C
804#define VCLK2_POST 0x30
805#define VCLK3_POST 0xC0
806#define VCLK0_FB_DIV 0x07
807#define VCLK1_FB_DIV 0x08
808#define VCLK2_FB_DIV 0x09
809#define VCLK3_FB_DIV 0x0A
810#define PLL_EXT_CNTL 0x0B
811#define PLL_XCLK_MCLK_RATIO 0x03
812#define PLL_XCLK_SRC_SEL 0x07
813#define PLL_MFB_TIMES_4_2B 0x08
814#define PLL_VCLK0_XDIV 0x10
815#define PLL_VCLK1_XDIV 0x20
816#define PLL_VCLK2_XDIV 0x40
817#define PLL_VCLK3_XDIV 0x80
818#define DLL_CNTL 0x0C
819#define DLL1_CNTL 0x0C
820#define VFC_CNTL 0x0D
821#define PLL_TEST_CNTL 0x0E
822#define PLL_TEST_COUNT 0x0F
823#define LVDS_CNTL0 0x10
824#define LVDS_CNTL1 0x11
825#define AGP1_CNTL 0x12
826#define AGP2_CNTL 0x13
827#define DLL2_CNTL 0x14
828#define SCLK_FB_DIV 0x15
829#define SPLL_CNTL1 0x16
830#define SPLL_CNTL2 0x17
831#define APLL_STRAPS 0x18
832#define EXT_VPLL_CNTL 0x19
833#define EXT_VPLL_EN 0x04
834#define EXT_VPLL_VGA_EN 0x08
835#define EXT_VPLL_INSYNC 0x10
836#define EXT_VPLL_REF_DIV 0x1A
837#define EXT_VPLL_FB_DIV 0x1B
838#define EXT_VPLL_MSB 0x1C
839#define HTOTAL_CNTL 0x1D
840#define BYTE_CLK_CNTL 0x1E
841#define TV_PLL_CNTL1 0x1F
842#define TV_PLL_CNTL2 0x20
843#define TV_PLL_CNTL 0x21
844#define EXT_TV_PLL 0x22
845#define V2PLL_CNTL 0x23
846#define PLL_V2CLK_CNTL 0x24
847#define EXT_V2PLL_REF_DIV 0x25
848#define EXT_V2PLL_FB_DIV 0x26
849#define EXT_V2PLL_MSB 0x27
850#define HTOTAL2_CNTL 0x28
851#define PLL_YCLK_CNTL 0x29
852#define PM_DYN_CLK_CNTL 0x2A
853
854/* CONFIG_CNTL register constants */
855#define APERTURE_4M_ENABLE 1
856#define APERTURE_8M_ENABLE 2
857#define VGA_APERTURE_ENABLE 4
858
859/* CONFIG_STAT0 register constants (GX, CX) */
860#define CFG_BUS_TYPE 0x00000007
861#define CFG_MEM_TYPE 0x00000038
862#define CFG_INIT_DAC_TYPE 0x00000e00
863
864/* CONFIG_STAT0 register constants (CT, ET, VT) */
865#define CFG_MEM_TYPE_xT 0x00000007
866
867#define ISA 0
868#define EISA 1
869#define LOCAL_BUS 6
870#define PCI 7
871
872/* Memory types for GX, CX */
873#define DRAMx4 0
874#define VRAMx16 1
875#define VRAMx16ssr 2
876#define DRAMx16 3
877#define GraphicsDRAMx16 4
878#define EnhancedVRAMx16 5
879#define EnhancedVRAMx16ssr 6
880
881/* Memory types for CT, ET, VT, GT */
882#define DRAM 1
883#define EDO 2
884#define PSEUDO_EDO 3
885#define SDRAM 4
886#define SGRAM 5
887#define WRAM 6
888
889#define DAC_INTERNAL 0x00
890#define DAC_IBMRGB514 0x01
891#define DAC_ATI68875 0x02
892#define DAC_TVP3026_A 0x72
893#define DAC_BT476 0x03
894#define DAC_BT481 0x04
895#define DAC_ATT20C491 0x14
896#define DAC_SC15026 0x24
897#define DAC_MU9C1880 0x34
898#define DAC_IMSG174 0x44
899#define DAC_ATI68860_B 0x05
900#define DAC_ATI68860_C 0x15
901#define DAC_TVP3026_B 0x75
902#define DAC_STG1700 0x06
903#define DAC_ATT498 0x16
904#define DAC_STG1702 0x07
905#define DAC_SC15021 0x17
906#define DAC_ATT21C498 0x27
907#define DAC_STG1703 0x37
908#define DAC_CH8398 0x47
909#define DAC_ATT20C408 0x57
910
911#define CLK_ATI18818_0 0
912#define CLK_ATI18818_1 1
913#define CLK_STG1703 2
914#define CLK_CH8398 3
915#define CLK_INTERNAL 4
916#define CLK_ATT20C408 5
917#define CLK_IBMRGB514 6
918
919/* MEM_CNTL register constants */
920#define MEM_SIZE_ALIAS 0x00000007
921#define MEM_SIZE_512K 0x00000000
922#define MEM_SIZE_1M 0x00000001
923#define MEM_SIZE_2M 0x00000002
924#define MEM_SIZE_4M 0x00000003
925#define MEM_SIZE_6M 0x00000004
926#define MEM_SIZE_8M 0x00000005
927#define MEM_SIZE_ALIAS_GTB 0x0000000F
928#define MEM_SIZE_2M_GTB 0x00000003
929#define MEM_SIZE_4M_GTB 0x00000007
930#define MEM_SIZE_6M_GTB 0x00000009
931#define MEM_SIZE_8M_GTB 0x0000000B
932#define MEM_BNDRY 0x00030000
933#define MEM_BNDRY_0K 0x00000000
934#define MEM_BNDRY_256K 0x00010000
935#define MEM_BNDRY_512K 0x00020000
936#define MEM_BNDRY_1M 0x00030000
937#define MEM_BNDRY_EN 0x00040000
938
939#define ONE_MB 0x100000
940/* ATI PCI constants */
941#define PCI_ATI_VENDOR_ID 0x1002
942
943
944/* CONFIG_CHIP_ID register constants */
945#define CFG_CHIP_TYPE 0x0000FFFF
946#define CFG_CHIP_CLASS 0x00FF0000
947#define CFG_CHIP_REV 0xFF000000
948#define CFG_CHIP_MAJOR 0x07000000
949#define CFG_CHIP_FND_ID 0x38000000
950#define CFG_CHIP_MINOR 0xC0000000
951
952
953/* Chip IDs read from CONFIG_CHIP_ID */
954
955/* mach64GX family */
956#define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
957#define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */
958
959#define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */
960#define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */
961
962/* mach64CT family */
963#define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */
964#define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */
965
966/* mach64CT family / mach64VT class */
967#define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */
968#define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */
969#define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */
970
971/* mach64CT family / mach64GT (3D RAGE) class */
972#define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */
973#define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */
974#define LG_CHIP_ID 0x4c47 /* RAGE LT */
975#define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */
976#define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */
977#define LT_CHIP_ID 0x4c54 /* RAGE LT */
978
979/* mach64CT family / (Rage XL) class */
980#define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */
981#define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */
982#define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */
983#define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */
984#define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */
985#define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */
986
987#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
988 (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
989 (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
990
991#define GT_CHIP_ID 0x4754 /* RAGE (GT) */
992#define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */
993#define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */
994#define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */
995#define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */
996#define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */
997#define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */
998#define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */
999#define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */
1000#define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */
1001
1002#define LM_CHIP_ID 0x4c4d /* RAGE Mobility AGP, full function */
1003#define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */
1004#define LR_CHIP_ID 0x4c52 /* RAGE Mobility PCI, full function */
1005#define LS_CHIP_ID 0x4c53 /* RAGE Mobility PCI */
1006
1007#define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \
1008 (id)==LR_CHIP_ID || (id)==LS_CHIP_ID)
1009/* Mach64 major ASIC revisions */
1010#define MACH64_ASIC_NEC_VT_A3 0x08
1011#define MACH64_ASIC_NEC_VT_A4 0x48
1012#define MACH64_ASIC_SGS_VT_A4 0x40
1013#define MACH64_ASIC_SGS_VT_B1S1 0x01
1014#define MACH64_ASIC_SGS_GT_B1S1 0x01
1015#define MACH64_ASIC_SGS_GT_B1S2 0x41
1016#define MACH64_ASIC_UMC_GT_B2U1 0x1a
1017#define MACH64_ASIC_UMC_GT_B2U2 0x5a
1018#define MACH64_ASIC_UMC_VT_B2U3 0x9a
1019#define MACH64_ASIC_UMC_GT_B2U3 0x9a
1020#define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b
1021#define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b
1022#define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c
1023#define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c
1024
1025/* Mach64 foundries */
1026#define MACH64_FND_SGS 0
1027#define MACH64_FND_NEC 1
1028#define MACH64_FND_UMC 3
1029
1030/* Mach64 chip types */
1031#define MACH64_UNKNOWN 0
1032#define MACH64_GX 1
1033#define MACH64_CX 2
1034#define MACH64_CT 3Restore
1035#define MACH64_ET 4
1036#define MACH64_VT 5
1037#define MACH64_GT 6
1038
1039/* DST_CNTL register constants */
1040#define DST_X_RIGHT_TO_LEFT 0
1041#define DST_X_LEFT_TO_RIGHT 1
1042#define DST_Y_BOTTOM_TO_TOP 0
1043#define DST_Y_TOP_TO_BOTTOM 2
1044#define DST_X_MAJOR 0
1045#define DST_Y_MAJOR 4
1046#define DST_X_TILE 8
1047#define DST_Y_TILE 0x10
1048#define DST_LAST_PEL 0x20
1049#define DST_POLYGON_ENABLE 0x40
1050#define DST_24_ROTATION_ENABLE 0x80
1051
1052/* SRC_CNTL register constants */
1053#define SRC_PATTERN_ENABLE 1
1054#define SRC_ROTATION_ENABLE 2
1055#define SRC_LINEAR_ENABLE 4
1056#define SRC_BYTE_ALIGN 8
1057#define SRC_LINE_X_RIGHT_TO_LEFT 0
1058#define SRC_LINE_X_LEFT_TO_RIGHT 0x10
1059
1060/* HOST_CNTL register constants */
1061#define HOST_BYTE_ALIGN 1
1062
1063/* GUI_TRAJ_CNTL register constants */
1064#define PAT_MONO_8x8_ENABLE 0x01000000
1065#define PAT_CLR_4x2_ENABLE 0x02000000
1066#define PAT_CLR_8x1_ENABLE 0x04000000
1067
1068/* DP_CHAIN_MASK register constants */
1069#define DP_CHAIN_4BPP 0x8888
1070#define DP_CHAIN_7BPP 0xD2D2
1071#define DP_CHAIN_8BPP 0x8080
1072#define DP_CHAIN_8BPP_RGB 0x9292
1073#define DP_CHAIN_15BPP 0x4210
1074#define DP_CHAIN_16BPP 0x8410
1075#define DP_CHAIN_24BPP 0x8080
1076#define DP_CHAIN_32BPP 0x8080
1077
1078/* DP_PIX_WIDTH register constants */
1079#define DST_1BPP 0x0
1080#define DST_4BPP 0x1
1081#define DST_8BPP 0x2
1082#define DST_15BPP 0x3
1083#define DST_16BPP 0x4
1084#define DST_24BPP 0x5
1085#define DST_32BPP 0x6
1086#define DST_MASK 0xF
1087#define SRC_1BPP 0x000
1088#define SRC_4BPP 0x100
1089#define SRC_8BPP 0x200
1090#define SRC_15BPP 0x300
1091#define SRC_16BPP 0x400
1092#define SRC_24BPP 0x500
1093#define SRC_32BPP 0x600
1094#define SRC_MASK 0xF00
1095#define DP_HOST_TRIPLE_EN 0x2000
1096#define HOST_1BPP 0x00000
1097#define HOST_4BPP 0x10000
1098#define HOST_8BPP 0x20000
1099#define HOST_15BPP 0x30000
1100#define HOST_16BPP 0x40000
1101#define HOST_24BPP 0x50000
1102#define HOST_32BPP 0x60000
1103#define HOST_MASK 0xF0000
1104#define BYTE_ORDER_MSB_TO_LSB 0
1105#define BYTE_ORDER_LSB_TO_MSB 0x1000000
1106#define BYTE_ORDER_MASK 0x1000000
1107
1108/* DP_MIX register constants */
1109#define BKGD_MIX_NOT_D 0
1110#define BKGD_MIX_ZERO 1
1111#define BKGD_MIX_ONE 2
1112#define BKGD_MIX_D 3
1113#define BKGD_MIX_NOT_S 4
1114#define BKGD_MIX_D_XOR_S 5
1115#define BKGD_MIX_NOT_D_XOR_S 6
1116#define BKGD_MIX_S 7
1117#define BKGD_MIX_NOT_D_OR_NOT_S 8
1118#define BKGD_MIX_D_OR_NOT_S 9
1119#define BKGD_MIX_NOT_D_OR_S 10
1120#define BKGD_MIX_D_OR_S 11
1121#define BKGD_MIX_D_AND_S 12
1122#define BKGD_MIX_NOT_D_AND_S 13
1123#define BKGD_MIX_D_AND_NOT_S 14
1124#define BKGD_MIX_NOT_D_AND_NOT_S 15
1125#define BKGD_MIX_D_PLUS_S_DIV2 0x17
1126#define FRGD_MIX_NOT_D 0
1127#define FRGD_MIX_ZERO 0x10000
1128#define FRGD_MIX_ONE 0x20000
1129#define FRGD_MIX_D 0x30000
1130#define FRGD_MIX_NOT_S 0x40000
1131#define FRGD_MIX_D_XOR_S 0x50000
1132#define FRGD_MIX_NOT_D_XOR_S 0x60000
1133#define FRGD_MIX_S 0x70000
1134#define FRGD_MIX_NOT_D_OR_NOT_S 0x80000
1135#define FRGD_MIX_D_OR_NOT_S 0x90000
1136#define FRGD_MIX_NOT_D_OR_S 0xa0000
1137#define FRGD_MIX_D_OR_S 0xb0000
1138#define FRGD_MIX_D_AND_S 0xc0000
1139#define FRGD_MIX_NOT_D_AND_S 0xd0000
1140#define FRGD_MIX_D_AND_NOT_S 0xe0000
1141#define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000
1142#define FRGD_MIX_D_PLUS_S_DIV2 0x170000
1143
1144/* DP_SRC register constants */
1145#define BKGD_SRC_BKGD_CLR 0
1146#define BKGD_SRC_FRGD_CLR 1
1147#define BKGD_SRC_HOST 2
1148#define BKGD_SRC_BLIT 3
1149#define BKGD_SRC_PATTERN 4
1150#define FRGD_SRC_BKGD_CLR 0
1151#define FRGD_SRC_FRGD_CLR 0x100
1152#define FRGD_SRC_HOST 0x200
1153#define FRGD_SRC_BLIT 0x300
1154#define FRGD_SRC_PATTERN 0x400
1155#define MONO_SRC_ONE 0
1156#define MONO_SRC_PATTERN 0x10000
1157#define MONO_SRC_HOST 0x20000
1158#define MONO_SRC_BLIT 0x30000
1159
1160/* CLR_CMP_CNTL register constants */
1161#define COMPARE_FALSE 0
1162#define COMPARE_TRUE 1
1163#define COMPARE_NOT_EQUAL 4
1164#define COMPARE_EQUAL 5
1165#define COMPARE_DESTINATION 0
1166#define COMPARE_SOURCE 0x1000000
1167
1168/* FIFO_STAT register constants */
1169#define FIFO_ERR 0x80000000
1170
1171/* CONTEXT_LOAD_CNTL constants */
1172#define CONTEXT_NO_LOAD 0
1173#define CONTEXT_LOAD 0x10000
1174#define CONTEXT_LOAD_AND_DO_FILL 0x20000
1175#define CONTEXT_LOAD_AND_DO_LINE 0x30000
1176#define CONTEXT_EXECUTE 0
1177#define CONTEXT_CMD_DISABLE 0x80000000
1178
1179/* GUI_STAT register constants */
1180#define ENGINE_IDLE 0
1181#define ENGINE_BUSY 1
1182#define SCISSOR_LEFT_FLAG 0x10
1183#define SCISSOR_RIGHT_FLAG 0x20
1184#define SCISSOR_TOP_FLAG 0x40
1185#define SCISSOR_BOTTOM_FLAG 0x80
1186
1187/* ATI VGA Extended Regsiters */
1188#define sioATIEXT 0x1ce
1189#define bioATIEXT 0x3ce
1190
1191#define ATI2E 0xae
1192#define ATI32 0xb2
1193#define ATI36 0xb6
1194
1195/* VGA Graphics Controller Registers */
1196#define R_GENMO 0x3cc
1197#define VGAGRA 0x3ce
1198#define GRA06 0x06
1199
1200/* VGA Seququencer Registers */
1201#define VGASEQ 0x3c4
1202#define SEQ02 0x02
1203#define SEQ04 0x04
1204
1205#define MACH64_MAX_X ENGINE_MAX_X
1206#define MACH64_MAX_Y ENGINE_MAX_Y
1207
1208#define INC_X 0x0020
1209#define INC_Y 0x0080
1210
1211#define RGB16_555 0x0000
1212#define RGB16_565 0x0040
1213#define RGB16_655 0x0080
1214#define RGB16_664 0x00c0
1215
1216#define POLY_TEXT_TYPE 0x0001
1217#define IMAGE_TEXT_TYPE 0x0002
1218#define TEXT_TYPE_8_BIT 0x0004
1219#define TEXT_TYPE_16_BIT 0x0008
1220#define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
1221#define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
1222#define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
1223#define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
1224
1225#define MACH64_NUM_CLOCKS 16
1226#define MACH64_NUM_FREQS 50
1227
1228/* Power Management register constants (LT & LT Pro) */
1229#define PWR_MGT_ON 0x00000001
1230#define PWR_MGT_MODE_MASK 0x00000006
1231#define AUTO_PWR_UP 0x00000008
1232#define USE_F32KHZ 0x00000400
1233#define TRISTATE_MEM_EN 0x00000800
1234#define SELF_REFRESH 0x00000080
1235#define PWR_BLON 0x02000000
1236#define STANDBY_NOW 0x10000000
1237#define SUSPEND_NOW 0x20000000
1238#define PWR_MGT_STATUS_MASK 0xC0000000
1239#define PWR_MGT_STATUS_SUSPEND 0x80000000
1240
1241/* PM Mode constants */
1242#define PWR_MGT_MODE_PIN 0x00000000
1243#define PWR_MGT_MODE_REG 0x00000002
1244#define PWR_MGT_MODE_TIMER 0x00000004
1245#define PWR_MGT_MODE_PCI 0x00000006
1246
1247/* LCD registers (LT Pro) */
1248
1249/* LCD Index register */
1250#define LCD_INDEX_MASK 0x0000003F
1251#define LCD_DISPLAY_DIS 0x00000100
1252#define LCD_SRC_SEL 0x00000200
1253#define CRTC2_DISPLAY_DIS 0x00000400
1254
1255/* LCD register indices */
1256#define CONFIG_PANEL 0x00
1257#define LCD_GEN_CNTL 0x01
1258#define DSTN_CONTROL 0x02
1259#define HFB_PITCH_ADDR 0x03
1260#define HORZ_STRETCHING 0x04
1261#define VERT_STRETCHING 0x05
1262#define EXT_VERT_STRETCH 0x06
1263#define LT_GIO 0x07
1264#define POWER_MANAGEMENT 0x08
1265#define ZVGPIO 0x09
1266#define ICON_CLR0 0x0A
1267#define ICON_CLR1 0x0B
1268#define ICON_OFFSET 0x0C
1269#define ICON_HORZ_VERT_POSN 0x0D
1270#define ICON_HORZ_VERT_OFF 0x0E
1271#define ICON2_CLR0 0x0F
1272#define ICON2_CLR1 0x10
1273#define ICON2_OFFSET 0x11
1274#define ICON2_HORZ_VERT_POSN 0x12
1275#define ICON2_HORZ_VERT_OFF 0x13
1276#define LCD_MISC_CNTL 0x14
1277#define APC_CNTL 0x1C
1278#define POWER_MANAGEMENT_2 0x1D
1279#define ALPHA_BLENDING 0x25
1280#define PORTRAIT_GEN_CNTL 0x26
1281#define APC_CTRL_IO 0x27
1282#define TEST_IO 0x28
1283#define TEST_OUTPUTS 0x29
1284#define DP1_MEM_ACCESS 0x2A
1285#define DP0_MEM_ACCESS 0x2B
1286#define DP0_DEBUG_A 0x2C
1287#define DP0_DEBUG_B 0x2D
1288#define DP1_DEBUG_A 0x2E
1289#define DP1_DEBUG_B 0x2F
1290#define DPCTRL_DEBUG_A 0x30
1291#define DPCTRL_DEBUG_B 0x31
1292#define MEMBLK_DEBUG 0x32
1293#define APC_LUT_AB 0x33
1294#define APC_LUT_CD 0x34
1295#define APC_LUT_EF 0x35
1296#define APC_LUT_GH 0x36
1297#define APC_LUT_IJ 0x37
1298#define APC_LUT_KL 0x38
1299#define APC_LUT_MN 0x39
1300#define APC_LUT_OP 0x3A
1301
1302/* Values in LCD_GEN_CTRL */
1303#define CRT_ON 0x00000001ul
1304#define LCD_ON 0x00000002ul
1305#define HORZ_DIVBY2_EN 0x00000004ul
1306#define DONT_DS_ICON 0x00000008ul
1307#define LOCK_8DOT 0x00000010ul
1308#define ICON_ENABLE 0x00000020ul
1309#define DONT_SHADOW_VPAR 0x00000040ul
1310#define V2CLK_PM_EN 0x00000080ul
1311#define RST_FM 0x00000100ul
1312#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */
1313#define DIS_HOR_CRT_DIVBY2 0x00000400ul
1314#define SCLK_SEL 0x00000800ul
1315#define SCLK_DELAY 0x0000f000ul
1316#define TVCLK_PM_EN 0x00010000ul
1317#define VCLK_DAC_PM_EN 0x00020000ul
1318#define VCLK_LCD_OFF 0x00040000ul
1319#define SELECT_WAIT_4MS 0x00080000ul
1320#define XTALIN_PM_EN 0x00080000ul /* XC/XL */
1321#define V2CLK_DAC_PM_EN 0x00100000ul
1322#define LVDS_EN 0x00200000ul
1323#define LVDS_PLL_EN 0x00400000ul
1324#define LVDS_PLL_RESET 0x00800000ul
1325#define LVDS_RESERVED_BITS 0x07000000ul
1326#define CRTC_RW_SELECT 0x08000000ul /* LTPro */
1327#define USE_SHADOWED_VEND 0x10000000ul
1328#define USE_SHADOWED_ROWCUR 0x20000000ul
1329#define SHADOW_EN 0x40000000ul
1330#define SHADOW_RW_EN 0x80000000ul
1331
1332#define LCD_SET_PRIMARY_MASK 0x07FFFBFBul
1333
1334/* Values in HORZ_STRETCHING */
1335#define HORZ_STRETCH_BLEND 0x00000ffful
1336#define HORZ_STRETCH_RATIO 0x0000fffful
1337#define HORZ_STRETCH_LOOP 0x00070000ul
1338#define HORZ_STRETCH_LOOP09 0x00000000ul
1339#define HORZ_STRETCH_LOOP11 0x00010000ul
1340#define HORZ_STRETCH_LOOP12 0x00020000ul
1341#define HORZ_STRETCH_LOOP14 0x00030000ul
1342#define HORZ_STRETCH_LOOP15 0x00040000ul
1343/* ? 0x00050000ul */
1344/* ? 0x00060000ul */
1345/* ? 0x00070000ul */
1346/* ? 0x00080000ul */
1347#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */
1348/* ? 0x10000000ul */
1349#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */
1350#define HORZ_STRETCH_MODE 0x40000000ul
1351#define HORZ_STRETCH_EN 0x80000000ul
1352
1353/* Values in VERT_STRETCHING */
1354#define VERT_STRETCH_RATIO0 0x000003fful
1355#define VERT_STRETCH_RATIO1 0x000ffc00ul
1356#define VERT_STRETCH_RATIO2 0x3ff00000ul
1357#define VERT_STRETCH_USE0 0x40000000ul
1358#define VERT_STRETCH_EN 0x80000000ul
1359
1360/* Values in EXT_VERT_STRETCH */
1361#define VERT_STRETCH_RATIO3 0x000003fful
1362#define FORCE_DAC_DATA 0x000000fful
1363#define FORCE_DAC_DATA_SEL 0x00000300ul
1364#define VERT_STRETCH_MODE 0x00000400ul
1365#define VERT_PANEL_SIZE 0x003ff800ul
1366#define AUTO_VERT_RATIO 0x00400000ul
1367#define USE_AUTO_FP_POS 0x00800000ul
1368#define USE_AUTO_LCD_VSYNC 0x01000000ul
1369/* ? 0xfe000000ul */
1370
1371/* Values in LCD_MISC_CNTL */
1372#define BIAS_MOD_LEVEL_MASK 0x0000ff00
1373#define BIAS_MOD_LEVEL_SHIFT 8
1374#define BLMOD_EN 0x00010000
1375#define BIASMOD_EN 0x00020000
1376
1377#endif /* REGMACH64_H */
diff --git a/include/video/maxinefb.h b/include/video/maxinefb.h
new file mode 100644
index 000000000000..6aeb4acca2bd
--- /dev/null
+++ b/include/video/maxinefb.h
@@ -0,0 +1,38 @@
1/*
2 * linux/drivers/video/maxinefb.h
3 *
4 * DECstation 5000/xx onboard framebuffer support, Copyright (C) 1999 by
5 * Michael Engel <engel@unix-ag.org> and Karsten Merker <merker@guug.de>
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
9 */
10
11#include <asm/addrspace.h>
12
13/*
14 * IMS332 video controller register base address
15 */
16#define MAXINEFB_IMS332_ADDRESS KSEG1ADDR(0x1c140000)
17
18/*
19 * Begin of DECstation 5000/xx onboard framebuffer memory, default resolution
20 * is 1024x768x8
21 */
22#define DS5000_xx_ONBOARD_FBMEM_START KSEG1ADDR(0x0a000000)
23
24/*
25 * The IMS 332 video controller used in the DECstation 5000/xx series
26 * uses 32 bits wide registers; the following defines declare the
27 * register numbers, to get the real offset, these have to be multiplied
28 * by four.
29 */
30
31#define IMS332_REG_CURSOR_RAM 0x200 /* hardware cursor bitmap */
32
33/*
34 * The color palette entries have the form 0x00BBGGRR
35 */
36#define IMS332_REG_COLOR_PALETTE 0x100 /* color palette, 256 entries */
37#define IMS332_REG_CURSOR_COLOR_PALETTE 0x0a1 /* cursor color palette, */
38 /* 3 entries */
diff --git a/include/video/neomagic.h b/include/video/neomagic.h
new file mode 100644
index 000000000000..bdaee70868dd
--- /dev/null
+++ b/include/video/neomagic.h
@@ -0,0 +1,207 @@
1/*
2 * linux/include/video/neo_reg.h -- NeoMagic Framebuffer Driver
3 *
4 * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
9 */
10
11#define NEO_BS0_BLT_BUSY 0x00000001
12#define NEO_BS0_FIFO_AVAIL 0x00000002
13#define NEO_BS0_FIFO_PEND 0x00000004
14
15#define NEO_BC0_DST_Y_DEC 0x00000001
16#define NEO_BC0_X_DEC 0x00000002
17#define NEO_BC0_SRC_TRANS 0x00000004
18#define NEO_BC0_SRC_IS_FG 0x00000008
19#define NEO_BC0_SRC_Y_DEC 0x00000010
20#define NEO_BC0_FILL_PAT 0x00000020
21#define NEO_BC0_SRC_MONO 0x00000040
22#define NEO_BC0_SYS_TO_VID 0x00000080
23
24#define NEO_BC1_DEPTH8 0x00000100
25#define NEO_BC1_DEPTH16 0x00000200
26#define NEO_BC1_X_320 0x00000400
27#define NEO_BC1_X_640 0x00000800
28#define NEO_BC1_X_800 0x00000c00
29#define NEO_BC1_X_1024 0x00001000
30#define NEO_BC1_X_1152 0x00001400
31#define NEO_BC1_X_1280 0x00001800
32#define NEO_BC1_X_1600 0x00001c00
33#define NEO_BC1_DST_TRANS 0x00002000
34#define NEO_BC1_MSTR_BLT 0x00004000
35#define NEO_BC1_FILTER_Z 0x00008000
36
37#define NEO_BC2_WR_TR_DST 0x00800000
38
39#define NEO_BC3_SRC_XY_ADDR 0x01000000
40#define NEO_BC3_DST_XY_ADDR 0x02000000
41#define NEO_BC3_CLIP_ON 0x04000000
42#define NEO_BC3_FIFO_EN 0x08000000
43#define NEO_BC3_BLT_ON_ADDR 0x10000000
44#define NEO_BC3_SKIP_MAPPING 0x80000000
45
46#define NEO_MODE1_DEPTH8 0x0100
47#define NEO_MODE1_DEPTH16 0x0200
48#define NEO_MODE1_DEPTH24 0x0300
49#define NEO_MODE1_X_320 0x0400
50#define NEO_MODE1_X_640 0x0800
51#define NEO_MODE1_X_800 0x0c00
52#define NEO_MODE1_X_1024 0x1000
53#define NEO_MODE1_X_1152 0x1400
54#define NEO_MODE1_X_1280 0x1800
55#define NEO_MODE1_X_1600 0x1c00
56#define NEO_MODE1_BLT_ON_ADDR 0x2000
57
58/* These are offseted in MMIO space by par->CursorOff */
59#define NEOREG_CURSCNTL 0x00
60#define NEOREG_CURSX 0x04
61#define NEOREG_CURSY 0x08
62#define NEOREG_CURSBGCOLOR 0x0C
63#define NEOREG_CURSFGCOLOR 0x10
64#define NEOREG_CURSMEMPOS 0x14
65
66#define NEO_CURS_DISABLE 0x00000000
67#define NEO_CURS_ENABLE 0x00000001
68#define NEO_ICON64_ENABLE 0x00000008
69#define NEO_ICON128_ENABLE 0x0000000C
70#define NEO_ICON_BLANK 0x00000010
71
72#define NEO_GR01_SUPPRESS_VSYNC 0x10
73#define NEO_GR01_SUPPRESS_HSYNC 0x20
74
75#ifdef __KERNEL__
76
77#ifdef NEOFB_DEBUG
78# define DBG(x) printk (KERN_DEBUG "neofb: %s\n", (x));
79#else
80# define DBG(x)
81#endif
82
83#define PCI_CHIP_NM2070 0x0001
84#define PCI_CHIP_NM2090 0x0002
85#define PCI_CHIP_NM2093 0x0003
86#define PCI_CHIP_NM2097 0x0083
87#define PCI_CHIP_NM2160 0x0004
88#define PCI_CHIP_NM2200 0x0005
89#define PCI_CHIP_NM2230 0x0025
90#define PCI_CHIP_NM2360 0x0006
91#define PCI_CHIP_NM2380 0x0016
92
93
94struct xtimings {
95 unsigned int pixclock;
96 unsigned int HDisplay;
97 unsigned int HSyncStart;
98 unsigned int HSyncEnd;
99 unsigned int HTotal;
100 unsigned int VDisplay;
101 unsigned int VSyncStart;
102 unsigned int VSyncEnd;
103 unsigned int VTotal;
104 unsigned int sync;
105 int dblscan;
106 int interlaced;
107};
108
109
110/* --------------------------------------------------------------------- */
111
112typedef volatile struct {
113 __u32 bltStat;
114 __u32 bltCntl;
115 __u32 xpColor;
116 __u32 fgColor;
117 __u32 bgColor;
118 __u32 pitch;
119 __u32 clipLT;
120 __u32 clipRB;
121 __u32 srcBitOffset;
122 __u32 srcStart;
123 __u32 reserved0;
124 __u32 dstStart;
125 __u32 xyExt;
126
127 __u32 reserved1[19];
128
129 __u32 pageCntl;
130 __u32 pageBase;
131 __u32 postBase;
132 __u32 postPtr;
133 __u32 dataPtr;
134} Neo2200;
135
136#define MMIO_SIZE 0x200000
137
138#define NEO_EXT_CR_MAX 0x85
139#define NEO_EXT_GR_MAX 0xC7
140
141struct neofb_par {
142 struct vgastate state;
143 atomic_t ref_count;
144
145 unsigned char MiscOutReg; /* Misc */
146 unsigned char CRTC[25]; /* Crtc Controller */
147 unsigned char Sequencer[5]; /* Video Sequencer */
148 unsigned char Graphics[9]; /* Video Graphics */
149 unsigned char Attribute[21]; /* Video Atribute */
150
151 unsigned char GeneralLockReg;
152 unsigned char ExtCRTDispAddr;
153 unsigned char ExtCRTOffset;
154 unsigned char SysIfaceCntl1;
155 unsigned char SysIfaceCntl2;
156 unsigned char ExtColorModeSelect;
157 unsigned char biosMode;
158
159 unsigned char PanelDispCntlReg1;
160 unsigned char PanelDispCntlReg2;
161 unsigned char PanelDispCntlReg3;
162 unsigned char PanelVertCenterReg1;
163 unsigned char PanelVertCenterReg2;
164 unsigned char PanelVertCenterReg3;
165 unsigned char PanelVertCenterReg4;
166 unsigned char PanelVertCenterReg5;
167 unsigned char PanelHorizCenterReg1;
168 unsigned char PanelHorizCenterReg2;
169 unsigned char PanelHorizCenterReg3;
170 unsigned char PanelHorizCenterReg4;
171 unsigned char PanelHorizCenterReg5;
172
173 int ProgramVCLK;
174 unsigned char VCLK3NumeratorLow;
175 unsigned char VCLK3NumeratorHigh;
176 unsigned char VCLK3Denominator;
177 unsigned char VerticalExt;
178
179#ifdef CONFIG_MTRR
180 int mtrr;
181#endif
182 u8 __iomem *mmio_vbase;
183 u8 cursorOff;
184 u8 *cursorPad; /* Must die !! */
185
186 Neo2200 __iomem *neo2200;
187
188 /* Panels size */
189 int NeoPanelWidth;
190 int NeoPanelHeight;
191
192 int maxClock;
193
194 int pci_burst;
195 int lcd_stretch;
196 int internal_display;
197 int external_display;
198 int libretto;
199};
200
201typedef struct {
202 int x_res;
203 int y_res;
204 int mode;
205} biosMode;
206
207#endif
diff --git a/include/video/newport.h b/include/video/newport.h
new file mode 100644
index 000000000000..812dac5b55f4
--- /dev/null
+++ b/include/video/newport.h
@@ -0,0 +1,582 @@
1/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $
2 *
3 * newport.h: Defines and register layout for NEWPORT graphics
4 * hardware.
5 *
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 *
8 * Ulf Carlsson - Compability with the IRIX structures added
9 */
10
11#ifndef _SGI_NEWPORT_H
12#define _SGI_NEWPORT_H
13
14
15typedef volatile unsigned int npireg_t;
16
17union npfloat {
18 volatile float flt;
19 npireg_t word;
20};
21
22typedef union npfloat npfreg_t;
23
24union np_dcb {
25 npireg_t byword;
26 struct { volatile unsigned short s0, s1; } byshort;
27 struct { volatile unsigned char b0, b1, b2, b3; } bybytes;
28};
29
30struct newport_rexregs {
31 npireg_t drawmode1; /* GL extra mode bits */
32
33#define DM1_PLANES 0x00000007
34#define DM1_NOPLANES 0x00000000
35#define DM1_RGBPLANES 0x00000001
36#define DM1_RGBAPLANES 0x00000002
37#define DM1_OLAYPLANES 0x00000004
38#define DM1_PUPPLANES 0x00000005
39#define DM1_CIDPLANES 0x00000006
40
41#define NPORT_DMODE1_DDMASK 0x00000018
42#define NPORT_DMODE1_DD4 0x00000000
43#define NPORT_DMODE1_DD8 0x00000008
44#define NPORT_DMODE1_DD12 0x00000010
45#define NPORT_DMODE1_DD24 0x00000018
46#define NPORT_DMODE1_DSRC 0x00000020
47#define NPORT_DMODE1_YFLIP 0x00000040
48#define NPORT_DMODE1_RWPCKD 0x00000080
49#define NPORT_DMODE1_HDMASK 0x00000300
50#define NPORT_DMODE1_HD4 0x00000000
51#define NPORT_DMODE1_HD8 0x00000100
52#define NPORT_DMODE1_HD12 0x00000200
53#define NPORT_DMODE1_HD32 0x00000300
54#define NPORT_DMODE1_RWDBL 0x00000400
55#define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */
56#define NPORT_DMODE1_CCMASK 0x00007000
57#define NPORT_DMODE1_CCLT 0x00001000
58#define NPORT_DMODE1_CCEQ 0x00002000
59#define NPORT_DMODE1_CCGT 0x00004000
60#define NPORT_DMODE1_RGBMD 0x00008000
61#define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */
62#define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */
63#define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */
64#define NPORT_DMODE1_SFMASK 0x00380000
65#define NPORT_DMODE1_SF0 0x00000000
66#define NPORT_DMODE1_SF1 0x00080000
67#define NPORT_DMODE1_SFDC 0x00100000
68#define NPORT_DMODE1_SFMDC 0x00180000
69#define NPORT_DMODE1_SFSA 0x00200000
70#define NPORT_DMODE1_SFMSA 0x00280000
71#define NPORT_DMODE1_DFMASK 0x01c00000
72#define NPORT_DMODE1_DF0 0x00000000
73#define NPORT_DMODE1_DF1 0x00400000
74#define NPORT_DMODE1_DFSC 0x00800000
75#define NPORT_DMODE1_DFMSC 0x00c00000
76#define NPORT_DMODE1_DFSA 0x01000000
77#define NPORT_DMODE1_DFMSA 0x01400000
78#define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */
79#define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */
80#define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */
81#define NPORT_DMODE1_LOMASK 0xf0000000
82#define NPORT_DMODE1_LOZERO 0x00000000
83#define NPORT_DMODE1_LOAND 0x10000000
84#define NPORT_DMODE1_LOANDR 0x20000000
85#define NPORT_DMODE1_LOSRC 0x30000000
86#define NPORT_DMODE1_LOANDI 0x40000000
87#define NPORT_DMODE1_LODST 0x50000000
88#define NPORT_DMODE1_LOXOR 0x60000000
89#define NPORT_DMODE1_LOOR 0x70000000
90#define NPORT_DMODE1_LONOR 0x80000000
91#define NPORT_DMODE1_LOXNOR 0x90000000
92#define NPORT_DMODE1_LONDST 0xa0000000
93#define NPORT_DMODE1_LOORR 0xb0000000
94#define NPORT_DMODE1_LONSRC 0xc0000000
95#define NPORT_DMODE1_LOORI 0xd0000000
96#define NPORT_DMODE1_LONAND 0xe0000000
97#define NPORT_DMODE1_LOONE 0xf0000000
98
99 npireg_t drawmode0; /* REX command register */
100
101 /* These bits define the graphics opcode being performed. */
102#define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */
103#define NPORT_DMODE0_NOP 0x00000000 /* No operation */
104#define NPORT_DMODE0_RD 0x00000001 /* Read operation */
105#define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */
106#define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */
107
108 /* The following decide what addressing mode(s) are to be used */
109#define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */
110#define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */
111#define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */
112#define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */
113#define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */
114#define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */
115#define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */
116#define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */
117
118 /* And now some misc. operation control bits. */
119#define NPORT_DMODE0_DOSETUP 0x00000020
120#define NPORT_DMODE0_CHOST 0x00000040
121#define NPORT_DMODE0_AHOST 0x00000080
122#define NPORT_DMODE0_STOPX 0x00000100
123#define NPORT_DMODE0_STOPY 0x00000200
124#define NPORT_DMODE0_SK1ST 0x00000400
125#define NPORT_DMODE0_SKLST 0x00000800
126#define NPORT_DMODE0_ZPENAB 0x00001000
127#define NPORT_DMODE0_LISPENAB 0x00002000
128#define NPORT_DMODE0_LISLST 0x00004000
129#define NPORT_DMODE0_L32 0x00008000
130#define NPORT_DMODE0_ZOPQ 0x00010000
131#define NPORT_DMODE0_LISOPQ 0x00020000
132#define NPORT_DMODE0_SHADE 0x00040000
133#define NPORT_DMODE0_LRONLY 0x00080000
134#define NPORT_DMODE0_XYOFF 0x00100000
135#define NPORT_DMODE0_CLAMP 0x00200000
136#define NPORT_DMODE0_ENDPF 0x00400000
137#define NPORT_DMODE0_YSTR 0x00800000
138
139 npireg_t lsmode; /* Mode for line stipple ops */
140 npireg_t lspattern; /* Pattern for line stipple ops */
141 npireg_t lspatsave; /* Backup save pattern */
142 npireg_t zpattern; /* Pixel zpattern */
143 npireg_t colorback; /* Background color */
144 npireg_t colorvram; /* Clear color for fast vram */
145 npireg_t alpharef; /* Reference value for afunctions */
146 unsigned int pad0;
147 npireg_t smask0x; /* Window GL relative screen mask 0 */
148 npireg_t smask0y; /* Window GL relative screen mask 0 */
149 npireg_t _setup;
150 npireg_t _stepz;
151 npireg_t _lsrestore;
152 npireg_t _lssave;
153
154 unsigned int _pad1[0x30];
155
156 /* Iterators, full state for context switch */
157 npfreg_t _xstart; /* X-start point (current) */
158 npfreg_t _ystart; /* Y-start point (current) */
159 npfreg_t _xend; /* x-end point */
160 npfreg_t _yend; /* y-end point */
161 npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */
162 npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */
163 npfreg_t bresd;
164 npfreg_t bress1;
165 npireg_t bresoctinc1;
166 volatile int bresrndinc2;
167 npireg_t brese1;
168 npireg_t bress2;
169 npireg_t aweight0;
170 npireg_t aweight1;
171 npfreg_t xstartf;
172 npfreg_t ystartf;
173 npfreg_t xendf;
174 npfreg_t yendf;
175 npireg_t xstarti;
176 npfreg_t xendf1;
177 npireg_t xystarti;
178 npireg_t xyendi;
179 npireg_t xstartendi;
180
181 unsigned int _unused2[0x29];
182
183 npfreg_t colorred;
184 npfreg_t coloralpha;
185 npfreg_t colorgrn;
186 npfreg_t colorblue;
187 npfreg_t slopered;
188 npfreg_t slopealpha;
189 npfreg_t slopegrn;
190 npfreg_t slopeblue;
191 npireg_t wrmask;
192 npireg_t colori;
193 npfreg_t colorx;
194 npfreg_t slopered1;
195 npireg_t hostrw0;
196 npireg_t hostrw1;
197 npireg_t dcbmode;
198#define NPORT_DMODE_WMASK 0x00000003
199#define NPORT_DMODE_W4 0x00000000
200#define NPORT_DMODE_W1 0x00000001
201#define NPORT_DMODE_W2 0x00000002
202#define NPORT_DMODE_W3 0x00000003
203#define NPORT_DMODE_EDPACK 0x00000004
204#define NPORT_DMODE_ECINC 0x00000008
205#define NPORT_DMODE_CMASK 0x00000070
206#define NPORT_DMODE_AMASK 0x00000780
207#define NPORT_DMODE_AVC2 0x00000000
208#define NPORT_DMODE_ACMALL 0x00000080
209#define NPORT_DMODE_ACM0 0x00000100
210#define NPORT_DMODE_ACM1 0x00000180
211#define NPORT_DMODE_AXMALL 0x00000200
212#define NPORT_DMODE_AXM0 0x00000280
213#define NPORT_DMODE_AXM1 0x00000300
214#define NPORT_DMODE_ABT 0x00000380
215#define NPORT_DMODE_AVCC1 0x00000400
216#define NPORT_DMODE_AVAB1 0x00000480
217#define NPORT_DMODE_ALG3V0 0x00000500
218#define NPORT_DMODE_A1562 0x00000580
219#define NPORT_DMODE_ESACK 0x00000800
220#define NPORT_DMODE_EASACK 0x00001000
221#define NPORT_DMODE_CWMASK 0x0003e000
222#define NPORT_DMODE_CHMASK 0x007c0000
223#define NPORT_DMODE_CSMASK 0x0f800000
224#define NPORT_DMODE_SENDIAN 0x10000000
225
226 unsigned int _unused3;
227
228 union np_dcb dcbdata0;
229 npireg_t dcbdata1;
230};
231
232struct newport_cregs {
233 npireg_t smask1x;
234 npireg_t smask1y;
235 npireg_t smask2x;
236 npireg_t smask2y;
237 npireg_t smask3x;
238 npireg_t smask3y;
239 npireg_t smask4x;
240 npireg_t smask4y;
241 npireg_t topscan;
242 npireg_t xywin;
243 npireg_t clipmode;
244#define NPORT_CMODE_SM0 0x00000001
245#define NPORT_CMODE_SM1 0x00000002
246#define NPORT_CMODE_SM2 0x00000004
247#define NPORT_CMODE_SM3 0x00000008
248#define NPORT_CMODE_SM4 0x00000010
249#define NPORT_CMODE_CMSK 0x00001e00
250
251 unsigned int _unused0;
252 unsigned int config;
253#define NPORT_CFG_G32MD 0x00000001
254#define NPORT_CFG_BWIDTH 0x00000002
255#define NPORT_CFG_ERCVR 0x00000004
256#define NPORT_CFG_BDMSK 0x00000078
257#define NPORT_CFG_BFAINT 0x00000080
258#define NPORT_CFG_GDMSK 0x00001f80
259#define NPORT_CFG_GD0 0x00000100
260#define NPORT_CFG_GD1 0x00000200
261#define NPORT_CFG_GD2 0x00000400
262#define NPORT_CFG_GD3 0x00000800
263#define NPORT_CFG_GD4 0x00001000
264#define NPORT_CFG_GFAINT 0x00002000
265#define NPORT_CFG_TOMSK 0x0001c000
266#define NPORT_CFG_VRMSK 0x000e0000
267#define NPORT_CFG_FBTYP 0x00100000
268
269 npireg_t _unused1;
270 npireg_t status;
271#define NPORT_STAT_VERS 0x00000007
272#define NPORT_STAT_GBUSY 0x00000008
273#define NPORT_STAT_BBUSY 0x00000010
274#define NPORT_STAT_VRINT 0x00000020
275#define NPORT_STAT_VIDINT 0x00000040
276#define NPORT_STAT_GLMSK 0x00001f80
277#define NPORT_STAT_BLMSK 0x0007e000
278#define NPORT_STAT_BFIRQ 0x00080000
279#define NPORT_STAT_GFIRQ 0x00100000
280
281 npireg_t ustatus;
282 npireg_t dcbreset;
283};
284
285struct newport_regs {
286 struct newport_rexregs set;
287 unsigned int _unused0[0x16e];
288 struct newport_rexregs go;
289 unsigned int _unused1[0x22e];
290 struct newport_cregs cset;
291 unsigned int _unused2[0x1ef];
292 struct newport_cregs cgo;
293};
294
295typedef struct {
296 unsigned int drawmode1;
297 unsigned int drawmode0;
298 unsigned int lsmode;
299 unsigned int lspattern;
300 unsigned int lspatsave;
301 unsigned int zpattern;
302 unsigned int colorback;
303 unsigned int colorvram;
304 unsigned int alpharef;
305 unsigned int smask0x;
306 unsigned int smask0y;
307 unsigned int _xstart;
308 unsigned int _ystart;
309 unsigned int _xend;
310 unsigned int _yend;
311 unsigned int xsave;
312 unsigned int xymove;
313 unsigned int bresd;
314 unsigned int bress1;
315 unsigned int bresoctinc1;
316 unsigned int bresrndinc2;
317 unsigned int brese1;
318 unsigned int bress2;
319
320 unsigned int aweight0;
321 unsigned int aweight1;
322 unsigned int colorred;
323 unsigned int coloralpha;
324 unsigned int colorgrn;
325 unsigned int colorblue;
326 unsigned int slopered;
327 unsigned int slopealpha;
328 unsigned int slopegrn;
329 unsigned int slopeblue;
330 unsigned int wrmask;
331 unsigned int hostrw0;
332 unsigned int hostrw1;
333
334 /* configregs */
335
336 unsigned int smask1x;
337 unsigned int smask1y;
338 unsigned int smask2x;
339 unsigned int smask2y;
340 unsigned int smask3x;
341 unsigned int smask3y;
342 unsigned int smask4x;
343 unsigned int smask4y;
344 unsigned int topscan;
345 unsigned int xywin;
346 unsigned int clipmode;
347 unsigned int config;
348
349 /* dcb registers */
350 unsigned int dcbmode;
351 unsigned int dcbdata0;
352 unsigned int dcbdata1;
353} newport_ctx;
354
355/* Reading/writing VC2 registers. */
356#define VC2_REGADDR_INDEX 0x00000000
357#define VC2_REGADDR_IREG 0x00000010
358#define VC2_REGADDR_RAM 0x00000030
359#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
360
361#define VC2_VLINET_ADDR 0x000
362#define VC2_VFRAMET_ADDR 0x400
363#define VC2_CGLYPH_ADDR 0x500
364
365/* Now the Indexed registers of the VC2. */
366#define VC2_IREG_VENTRY 0x00
367#define VC2_IREG_CENTRY 0x01
368#define VC2_IREG_CURSX 0x02
369#define VC2_IREG_CURSY 0x03
370#define VC2_IREG_CCURSX 0x04
371#define VC2_IREG_DENTRY 0x05
372#define VC2_IREG_SLEN 0x06
373#define VC2_IREG_RADDR 0x07
374#define VC2_IREG_VFPTR 0x08
375#define VC2_IREG_VLSPTR 0x09
376#define VC2_IREG_VLIR 0x0a
377#define VC2_IREG_VLCTR 0x0b
378#define VC2_IREG_CTPTR 0x0c
379#define VC2_IREG_WCURSY 0x0d
380#define VC2_IREG_DFPTR 0x0e
381#define VC2_IREG_DLTPTR 0x0f
382#define VC2_IREG_CONTROL 0x10
383#define VC2_IREG_CONFIG 0x20
384
385extern __inline__ void newport_vc2_set(struct newport_regs *regs, unsigned char vc2ireg,
386 unsigned short val)
387{
388 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 |
389 NPORT_DMODE_ECINC | VC2_PROTOCOL);
390 regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8);
391}
392
393extern __inline__ unsigned short newport_vc2_get(struct newport_regs *regs,
394 unsigned char vc2ireg)
395{
396 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 |
397 NPORT_DMODE_ECINC | VC2_PROTOCOL);
398 regs->set.dcbdata0.bybytes.b3 = vc2ireg;
399 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 |
400 NPORT_DMODE_ECINC | VC2_PROTOCOL);
401 return regs->set.dcbdata0.byshort.s1;
402}
403
404/* VC2 Control register bits */
405#define VC2_CTRL_EVIRQ 0x0001
406#define VC2_CTRL_EDISP 0x0002
407#define VC2_CTRL_EVIDEO 0x0004
408#define VC2_CTRL_EDIDS 0x0008
409#define VC2_CTRL_ECURS 0x0010
410#define VC2_CTRL_EGSYNC 0x0020
411#define VC2_CTRL_EILACE 0x0040
412#define VC2_CTRL_ECDISP 0x0080
413#define VC2_CTRL_ECCURS 0x0100
414#define VC2_CTRL_ECG64 0x0200
415#define VC2_CTRL_GLSEL 0x0400
416
417/* Controlling the color map on NEWPORT. */
418#define NCMAP_REGADDR_AREG 0x00000000
419#define NCMAP_REGADDR_ALO 0x00000000
420#define NCMAP_REGADDR_AHI 0x00000010
421#define NCMAP_REGADDR_PBUF 0x00000020
422#define NCMAP_REGADDR_CREG 0x00000030
423#define NCMAP_REGADDR_SREG 0x00000040
424#define NCMAP_REGADDR_RREG 0x00000060
425#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000)
426
427static __inline__ void newport_cmap_setaddr(struct newport_regs *regs,
428 unsigned short addr)
429{
430 regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
431 NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC |
432 NCMAP_REGADDR_AREG | NPORT_DMODE_W2);
433 regs->set.dcbdata0.byshort.s1 = addr;
434 regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
435 NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);
436}
437
438static __inline__ void newport_cmap_setrgb(struct newport_regs *regs,
439 unsigned char red,
440 unsigned char green,
441 unsigned char blue)
442{
443 regs->set.dcbdata0.byword =
444 (red << 24) |
445 (green << 16) |
446 (blue << 8);
447}
448
449/* Miscellaneous NEWPORT routines. */
450#define BUSY_TIMEOUT 100000
451static __inline__ int newport_wait(struct newport_regs *regs)
452{
453 int t = BUSY_TIMEOUT;
454
455 while (t--)
456 if (!(regs->cset.status & NPORT_STAT_GBUSY))
457 break;
458 return !t;
459}
460
461static __inline__ int newport_bfwait(struct newport_regs *regs)
462{
463 int t = BUSY_TIMEOUT;
464
465 while (t--)
466 if(!(regs->cset.status & NPORT_STAT_BBUSY))
467 break;
468 return !t;
469}
470
471/*
472 * DCBMODE register defines:
473 */
474
475/* Width of the data being transferred for each DCBDATA[01] word */
476#define DCB_DATAWIDTH_4 0x0
477#define DCB_DATAWIDTH_1 0x1
478#define DCB_DATAWIDTH_2 0x2
479#define DCB_DATAWIDTH_3 0x3
480
481/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */
482#define DCB_ENDATAPACK (1 << 2)
483
484/* Enables DCBCRS auto increment after each DCB transfer */
485#define DCB_ENCRSINC (1 << 3)
486
487/* shift for accessing the control register select address (DBCCRS, 3 bits) */
488#define DCB_CRS_SHIFT 4
489
490/* DCBADDR (4 bits): display bus slave address */
491#define DCB_ADDR_SHIFT 7
492#define DCB_VC2 (0 << DCB_ADDR_SHIFT)
493#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT)
494#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT)
495#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT)
496#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT)
497#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT)
498#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT)
499#define DCB_BT445 (7 << DCB_ADDR_SHIFT)
500#define DCB_VCC1 (8 << DCB_ADDR_SHIFT)
501#define DCB_VAB1 (9 << DCB_ADDR_SHIFT)
502#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT)
503#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT)
504#define DCB_RESERVED (15 << DCB_ADDR_SHIFT)
505
506/* DCB protocol ack types */
507#define DCB_ENSYNCACK (1 << 11)
508#define DCB_ENASYNCACK (1 << 12)
509
510#define DCB_CSWIDTH_SHIFT 13
511#define DCB_CSHOLD_SHIFT 18
512#define DCB_CSSETUP_SHIFT 23
513
514/* XMAP9 specific defines */
515/* XMAP9 -- registers as seen on the DCBMODE register*/
516# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT)
517# define XM9_PUPMODE (1 << 0)
518# define XM9_ODD_PIXEL (1 << 1)
519# define XM9_8_BITPLANES (1 << 2)
520# define XM9_SLOW_DCB (1 << 3)
521# define XM9_VIDEO_RGBMAP_MASK (3 << 4)
522# define XM9_EXPRESS_VIDEO (1 << 6)
523# define XM9_VIDEO_OPTION (1 << 7)
524# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT)
525# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT)
526# define XM9_FIFO_0_AVAIL 0
527# define XM9_FIFO_1_AVAIL 1
528# define XM9_FIFO_2_AVAIL 3
529# define XM9_FIFO_3_AVAIL 2
530# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL
531# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL
532# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT)
533# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT)
534# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT)
535# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT)
536
537
538#define DCB_CYCLES(setup,hold,width) \
539 ((hold << DCB_CSHOLD_SHIFT) | \
540 (setup << DCB_CSSETUP_SHIFT)| \
541 (width << DCB_CSWIDTH_SHIFT))
542
543#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0)
544#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0)
545#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
546#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3)
547
548static __inline__ void
549xmap9FIFOWait (struct newport_regs *rex)
550{
551 rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |
552 DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;
553 newport_bfwait (rex);
554
555 while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY)
556 ;
557}
558
559static __inline__ void
560xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq)
561{
562 if (cfreq > 119)
563 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
564 DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;
565 else if (cfreq > 59)
566 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
567 DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;
568 else
569 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
570 DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL;
571 rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff);
572}
573
574#define BT445_PROTOCOL DCB_CYCLES(1,1,3)
575
576#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT)
577#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT)
578
579#define BT445_REVISION_REG 0x01
580
581#endif /* !(_SGI_NEWPORT_H) */
582
diff --git a/include/video/permedia2.h b/include/video/permedia2.h
new file mode 100644
index 000000000000..b95d36289336
--- /dev/null
+++ b/include/video/permedia2.h
@@ -0,0 +1,233 @@
1/*
2 * Permedia2 framebuffer driver definitions.
3 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
4 * --------------------------------------------------------------------------
5 * $Id: pm2fb.h,v 1.26 2000/09/19 00:11:53 illo Exp $
6 * --------------------------------------------------------------------------
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 */
11
12#ifndef PM2FB_H
13#define PM2FB_H
14
15#define PM2_REFERENCE_CLOCK 14318 /* in KHz */
16#define PM2_MAX_PIXCLOCK 230000 /* in KHz */
17#define PM2_REGS_SIZE 0x10000
18
19#define PM2TAG(r) (u32 )(((r)-0x8000)>>3)
20
21/*****************************************************************************
22 * Permedia2 registers used in the framebuffer
23 *****************************************************************************/
24
25#define PM2R_RESET_STATUS 0x0000
26#define PM2R_IN_FIFO_SPACE 0x0018
27#define PM2R_OUT_FIFO_WORDS 0x0020
28#define PM2R_APERTURE_ONE 0x0050
29#define PM2R_APERTURE_TWO 0x0058
30#define PM2R_FIFO_DISCON 0x0068
31#define PM2R_CHIP_CONFIG 0x0070
32
33#define PM2R_REBOOT 0x1000
34#define PM2R_MEM_CONTROL 0x1040
35#define PM2R_BOOT_ADDRESS 0x1080
36#define PM2R_MEM_CONFIG 0x10c0
37#define PM2R_BYPASS_WRITE_MASK 0x1100
38#define PM2R_FRAMEBUFFER_WRITE_MASK 0x1140
39
40#define PM2R_OUT_FIFO 0x2000
41
42#define PM2R_SCREEN_BASE 0x3000
43#define PM2R_SCREEN_STRIDE 0x3008
44#define PM2R_H_TOTAL 0x3010
45#define PM2R_HG_END 0x3018
46#define PM2R_HB_END 0x3020
47#define PM2R_HS_START 0x3028
48#define PM2R_HS_END 0x3030
49#define PM2R_V_TOTAL 0x3038
50#define PM2R_VB_END 0x3040
51#define PM2R_VS_START 0x3048
52#define PM2R_VS_END 0x3050
53#define PM2R_VIDEO_CONTROL 0x3058
54#define PM2R_LINE_COUNT 0x3070
55#define PM2R_FIFO_CONTROL 0x3078
56
57#define PM2R_RD_PALETTE_WRITE_ADDRESS 0x4000
58#define PM2R_RD_PALETTE_DATA 0x4008
59#define PM2R_RD_PIXEL_MASK 0x4010
60#define PM2R_RD_PALETTE_READ_ADDRESS 0x4018
61#define PM2R_RD_INDEXED_DATA 0x4050
62
63#define PM2R_START_X_DOM 0x8000
64#define PM2R_D_X_DOM 0x8008
65#define PM2R_START_X_SUB 0x8010
66#define PM2R_D_X_SUB 0x8018
67#define PM2R_START_Y 0x8020
68#define PM2R_D_Y 0x8028
69#define PM2R_COUNT 0x8030
70#define PM2R_RENDER 0x8038
71#define PM2R_RASTERIZER_MODE 0x80a0
72#define PM2R_RECTANGLE_ORIGIN 0x80d0
73#define PM2R_RECTANGLE_SIZE 0x80d8
74#define PM2R_PACKED_DATA_LIMITS 0x8150
75#define PM2R_SCISSOR_MODE 0x8180
76#define PM2R_SCREEN_SIZE 0x8198
77#define PM2R_AREA_STIPPLE_MODE 0x81a0
78#define PM2R_WINDOW_ORIGIN 0x81c8
79#define PM2R_TEXTURE_ADDRESS_MODE 0x8380
80#define PM2R_TEXTURE_MAP_FORMAT 0x8588
81#define PM2R_TEXTURE_DATA_FORMAT 0x8590
82#define PM2R_TEXTURE_READ_MODE 0x8670
83#define PM2R_TEXEL_LUT_MODE 0x8678
84#define PM2R_TEXTURE_COLOR_MODE 0x8680
85#define PM2R_FOG_MODE 0x8690
86#define PM2R_COLOR_DDA_MODE 0x87e0
87#define PM2R_ALPHA_BLEND_MODE 0x8810
88#define PM2R_DITHER_MODE 0x8818
89#define PM2R_FB_SOFT_WRITE_MASK 0x8820
90#define PM2R_LOGICAL_OP_MODE 0x8828
91#define PM2R_LB_READ_MODE 0x8880
92#define PM2R_LB_READ_FORMAT 0x8888
93#define PM2R_LB_SOURCE_OFFSET 0x8890
94#define PM2R_LB_WINDOW_BASE 0x88b8
95#define PM2R_LB_WRITE_FORMAT 0x88c8
96#define PM2R_STENCIL_MODE 0x8988
97#define PM2R_DEPTH_MODE 0x89a0
98#define PM2R_FB_READ_MODE 0x8a80
99#define PM2R_FB_SOURCE_OFFSET 0x8a88
100#define PM2R_FB_PIXEL_OFFSET 0x8a90
101#define PM2R_FB_WINDOW_BASE 0x8ab0
102#define PM2R_FB_WRITE_MODE 0x8ab8
103#define PM2R_FB_HARD_WRITE_MASK 0x8ac0
104#define PM2R_FB_BLOCK_COLOR 0x8ac8
105#define PM2R_FB_READ_PIXEL 0x8ad0
106#define PM2R_FILTER_MODE 0x8c00
107#define PM2R_SYNC 0x8c40
108#define PM2R_YUV_MODE 0x8f00
109#define PM2R_STATISTICS_MODE 0x8c08
110#define PM2R_FB_SOURCE_DELTA 0x8d88
111#define PM2R_CONFIG 0x8d90
112#define PM2R_DELTA_MODE 0x9300
113
114/* Permedia2v */
115#define PM2VR_RD_INDEX_LOW 0x4020
116#define PM2VR_RD_INDEX_HIGH 0x4028
117#define PM2VR_RD_INDEXED_DATA 0x4030
118
119/* Permedia2 RAMDAC indexed registers */
120#define PM2I_RD_CURSOR_CONTROL 0x06
121#define PM2I_RD_COLOR_MODE 0x18
122#define PM2I_RD_MODE_CONTROL 0x19
123#define PM2I_RD_MISC_CONTROL 0x1e
124#define PM2I_RD_PIXEL_CLOCK_A1 0x20
125#define PM2I_RD_PIXEL_CLOCK_A2 0x21
126#define PM2I_RD_PIXEL_CLOCK_A3 0x22
127#define PM2I_RD_PIXEL_CLOCK_STATUS 0x29
128#define PM2I_RD_MEMORY_CLOCK_1 0x30
129#define PM2I_RD_MEMORY_CLOCK_2 0x31
130#define PM2I_RD_MEMORY_CLOCK_3 0x32
131#define PM2I_RD_MEMORY_CLOCK_STATUS 0x33
132#define PM2I_RD_COLOR_KEY_CONTROL 0x40
133#define PM2I_RD_OVERLAY_KEY 0x41
134#define PM2I_RD_RED_KEY 0x42
135#define PM2I_RD_GREEN_KEY 0x43
136#define PM2I_RD_BLUE_KEY 0x44
137
138/* Permedia2v extensions */
139#define PM2VI_RD_MISC_CONTROL 0x000
140#define PM2VI_RD_SYNC_CONTROL 0x001
141#define PM2VI_RD_DAC_CONTROL 0x002
142#define PM2VI_RD_PIXEL_SIZE 0x003
143#define PM2VI_RD_COLOR_FORMAT 0x004
144#define PM2VI_RD_CURSOR_MODE 0x005
145#define PM2VI_RD_CURSOR_X_LOW 0x007
146#define PM2VI_RD_CURSOR_X_HIGH 0x008
147#define PM2VI_RD_CURSOR_Y_LOW 0x009
148#define PM2VI_RD_CURSOR_Y_HIGH 0x00A
149#define PM2VI_RD_CURSOR_X_HOT 0x00B
150#define PM2VI_RD_CURSOR_Y_HOT 0x00C
151#define PM2VI_RD_CLK0_PRESCALE 0x201
152#define PM2VI_RD_CLK0_FEEDBACK 0x202
153#define PM2VI_RD_CLK0_POSTSCALE 0x203
154#define PM2VI_RD_CLK1_PRESCALE 0x204
155#define PM2VI_RD_CLK1_FEEDBACK 0x205
156#define PM2VI_RD_CLK1_POSTSCALE 0x206
157#define PM2VI_RD_CURSOR_PALETTE 0x303
158#define PM2VI_RD_CURSOR_PATTERN 0x400
159
160/* Fields and flags */
161#define PM2F_RENDER_AREASTIPPLE (1L<<0)
162#define PM2F_RENDER_FASTFILL (1L<<3)
163#define PM2F_RENDER_PRIMITIVE_MASK (3L<<6)
164#define PM2F_RENDER_LINE 0
165#define PM2F_RENDER_TRAPEZOID (1L<<6)
166#define PM2F_RENDER_POINT (2L<<6)
167#define PM2F_RENDER_RECTANGLE (3L<<6)
168#define PM2F_SYNCHRONIZATION (1L<<10)
169#define PM2F_PLL_LOCKED 0x10
170#define PM2F_BEING_RESET (1L<<31)
171#define PM2F_DATATYPE_COLOR 0x8000
172#define PM2F_VGA_ENABLE 0x02
173#define PM2F_VGA_FIXED 0x04
174#define PM2F_FB_WRITE_ENABLE 0x01
175#define PM2F_FB_READ_SOURCE_ENABLE 0x0200
176#define PM2F_RD_PALETTE_WIDTH_8 0x02
177#define PM2F_PART_PROD_MASK 0x01ff
178#define PM2F_SCREEN_SCISSOR_ENABLE 0x02
179#define PM2F_DATA_64_ENABLE 0x00010000
180#define PM2F_BLANK_LOW 0x02
181#define PM2F_HSYNC_MASK 0x18
182#define PM2F_VSYNC_MASK 0x60
183#define PM2F_HSYNC_ACT_HIGH 0x08
184#define PM2F_HSYNC_FORCED_LOW 0x10
185#define PM2F_HSYNC_ACT_LOW 0x18
186#define PM2F_VSYNC_ACT_HIGH 0x20
187#define PM2F_VSYNC_FORCED_LOW 0x40
188#define PM2F_VSYNC_ACT_LOW 0x60
189#define PM2F_LINE_DOUBLE 0x04
190#define PM2F_VIDEO_ENABLE 0x01
191#define PM2F_RD_PIXELFORMAT_SVGA 0x01
192#define PM2F_RD_PIXELFORMAT_RGB232OFFSET 0x02
193#define PM2F_RD_PIXELFORMAT_RGBA2321 0x03
194#define PM2F_RD_PIXELFORMAT_RGBA5551 0x04
195#define PM2F_RD_PIXELFORMAT_RGBA4444 0x05
196#define PM2F_RD_PIXELFORMAT_RGB565 0x06
197#define PM2F_RD_PIXELFORMAT_RGBA8888 0x08
198#define PM2F_RD_PIXELFORMAT_RGB888 0x09
199#define PM2F_RD_GUI_ACTIVE 0x10
200#define PM2F_RD_COLOR_MODE_RGB 0x20
201#define PM2F_DELTA_ORDER_RGB (1L<<18)
202#define PM2F_RD_TRUECOLOR 0x80
203#define PM2F_NO_ALPHA_BUFFER 0x10
204#define PM2F_TEXTEL_SIZE_16 0x00080000
205#define PM2F_TEXTEL_SIZE_32 0x00100000
206#define PM2F_TEXTEL_SIZE_4 0x00180000
207#define PM2F_TEXTEL_SIZE_24 0x00200000
208#define PM2F_INCREASE_X (1L<<21)
209#define PM2F_INCREASE_Y (1L<<22)
210#define PM2F_CONFIG_FB_WRITE_ENABLE (1L<<3)
211#define PM2F_CONFIG_FB_PACKED_DATA (1L<<2)
212#define PM2F_CONFIG_FB_READ_DEST_ENABLE (1L<<1)
213#define PM2F_CONFIG_FB_READ_SOURCE_ENABLE (1L<<0)
214#define PM2F_COLOR_KEY_TEST_OFF (1L<<4)
215#define PM2F_MEM_CONFIG_RAM_MASK (3L<<29)
216#define PM2F_MEM_BANKS_1 0L
217#define PM2F_MEM_BANKS_2 (1L<<29)
218#define PM2F_MEM_BANKS_3 (2L<<29)
219#define PM2F_MEM_BANKS_4 (3L<<29)
220#define PM2F_APERTURE_STANDARD 0
221#define PM2F_APERTURE_BYTESWAP 1
222#define PM2F_APERTURE_HALFWORDSWAP 2
223
224typedef enum {
225 PM2_TYPE_PERMEDIA2,
226 PM2_TYPE_PERMEDIA2V
227} pm2type_t;
228
229#endif /* PM2FB_H */
230
231/*****************************************************************************
232 * That's all folks!
233 *****************************************************************************/
diff --git a/include/video/pm3fb.h b/include/video/pm3fb.h
new file mode 100644
index 000000000000..8d3cef5d87a2
--- /dev/null
+++ b/include/video/pm3fb.h
@@ -0,0 +1,1241 @@
1/*
2 * linux/drivers/video/pm3fb.h -- 3DLabs Permedia3 frame buffer device
3 *
4 * Copyright (C) 2001 Romain Dolbeau <dolbeau@irisa.fr>
5 * Copyright (C) 2001 Sven Luther, <luther@dpt-info.u-strasbg.fr>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 *
11 * $Header: /cvsroot/linux/drivers/video/pm3fb.h,v 1.1 2002/02/25 19:11:06 marcelo Exp $
12 *
13 */
14
15#ifndef PM3FB_H
16#define PM3FB_H
17
18/**********************************************
19* GLINT Permedia3 Control Status registers *
20***********************************************/
21/* Control Status Registers */
22#define PM3ResetStatus 0x0000
23#define PM3IntEnable 0x0008
24#define PM3IntFlags 0x0010
25#define PM3InFIFOSpace 0x0018
26#define PM3OutFIFOWords 0x0020
27#define PM3DMAAddress 0x0028
28#define PM3DMACount 0x0030
29#define PM3ErrorFlags 0x0038
30#define PM3VClkCtl 0x0040
31#define PM3TestRegister 0x0048
32#define PM3Aperture0 0x0050
33#define PM3Aperture1 0x0058
34#define PM3DMAControl 0x0060
35#define PM3FIFODis 0x0068
36#define PM3ChipConfig 0x0070
37#define PM3AGPControl 0x0078
38
39#define PM3GPOutDMAAddress 0x0080
40#define PM3PCIFeedbackCount 0x0088
41#define PM3PCIAbortStatus 0x0090
42#define PM3PCIAbortAddress 0x0098
43
44#define PM3PCIPLLStatus 0x00f0
45
46#define PM3HostTextureAddress 0x0100
47#define PM3TextureDownloadControl 0x0108
48#define PM3TextureOperation 0x0110
49#define PM3LogicalTexturePage 0x0118
50#define PM3TexDMAAddress 0x0120
51#define PM3TexFIFOSpace 0x0128
52
53/**********************************************
54* GLINT Permedia3 Region 0 Bypass Controls *
55***********************************************/
56#define PM3ByAperture1Mode 0x0300
57 #define PM3ByApertureMode_BYTESWAP_ABCD (0<<0)
58 #define PM3ByApertureMode_BYTESWAP_BADC (1<<0)
59 #define PM3ByApertureMode_BYTESWAP_CDAB (2<<0)
60 #define PM3ByApertureMode_BYTESWAP_DCBA (3<<0)
61 #define PM3ByApertureMode_PATCH_DISABLE (0<<2)
62 #define PM3ByApertureMode_PATCH_ENABLE (1<<2)
63 #define PM3ByApertureMode_FORMAT_RAW (0<<3)
64 #define PM3ByApertureMode_FORMAT_YUYV (1<<3)
65 #define PM3ByApertureMode_FORMAT_UYVY (2<<3)
66 #define PM3ByApertureMode_PIXELSIZE_8BIT (0<<5)
67 #define PM3ByApertureMode_PIXELSIZE_16BIT (1<<5)
68 #define PM3ByApertureMode_PIXELSIZE_32BIT (2<<5)
69 #define PM3ByApertureMode_PIXELSIZE_MASK (3<<5)
70 #define PM3ByApertureMode_EFFECTIVE_STRIDE_1024 (0<<7)
71 #define PM3ByApertureMode_EFFECTIVE_STRIDE_2048 (1<<7)
72 #define PM3ByApertureMode_EFFECTIVE_STRIDE_4096 (2<<7)
73 #define PM3ByApertureMode_EFFECTIVE_STRIDE_8192 (3<<7)
74 #define PM3ByApertureMode_PATCH_OFFSET_X(off) (((off)&7f)<<9)
75 #define PM3ByApertureMode_PATCH_OFFSET_Y(off) (((off)&7f)<<16)
76 #define PM3ByApertureMode_FRAMEBUFFER (0<<21)
77 #define PM3ByApertureMode_LOCALBUFFER (1<<21)
78 #define PM3ByApertureMode_DOUBLE_WRITE_OFF (0<<22)
79 #define PM3ByApertureMode_DOUBLE_WRITE_1MB (1<<22)
80 #define PM3ByApertureMode_DOUBLE_WRITE_2MB (2<<22)
81 #define PM3ByApertureMode_DOUBLE_WRITE_4MB (3<<22)
82 #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4<<22)
83 #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5<<22)
84 #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6<<22)
85
86#define PM3ByAperture2Mode 0x0328
87
88/**********************************************
89* GLINT Permedia3 Memory Control (0x1000) *
90***********************************************/
91#define PM3MemCounter 0x1000
92#define PM3MemBypassWriteMask 0x1008
93#define PM3MemScratch 0x1010
94#define PM3LocalMemCaps 0x1018
95 #define PM3LocalMemCaps_NoWriteMask (1 << 28)
96#define PM3LocalMemTimings 0x1020
97#define PM3LocalMemControl 0x1028
98#define PM3LocalMemRefresh 0x1030
99#define PM3LocalMemPowerDown 0x1038
100#define PM3RemoteMemControl 0x1100
101
102/**********************************************
103* GLINT Permedia3 Video Control (0x3000) *
104***********************************************/
105
106#define PM3ScreenBase 0x3000
107#define PM3ScreenStride 0x3008
108#define PM3HTotal 0x3010
109#define PM3HgEnd 0x3018
110#define PM3HbEnd 0x3020
111#define PM3HsStart 0x3028
112#define PM3HsEnd 0x3030
113#define PM3VTotal 0x3038
114#define PM3VbEnd 0x3040
115#define PM3VsStart 0x3048
116#define PM3VsEnd 0x3050
117#define PM3VideoControl 0x3058
118 #define PM3VideoControl_DISABLE (0<<0)
119 #define PM3VideoControl_ENABLE (1<<0)
120 #define PM3VideoControl_BLANK_ACTIVE_HIGH (0<<1)
121 #define PM3VideoControl_BLANK_ACTIVE_LOW (1<<1)
122 #define PM3VideoControl_LINE_DOUBLE_OFF (0<<2)
123 #define PM3VideoControl_LINE_DOUBLE_ON (1<<2)
124 #define PM3VideoControl_HSYNC_FORCE_HIGH (0<<3)
125 #define PM3VideoControl_HSYNC_ACTIVE_HIGH (1<<3)
126 #define PM3VideoControl_HSYNC_FORCE_LOW (2<<3)
127 #define PM3VideoControl_HSYNC_ACTIVE_LOW (3<<3)
128 #define PM3VideoControl_HSYNC_MASK (3<<3)
129 #define PM3VideoControl_VSYNC_FORCE_HIGH (0<<5)
130 #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1<<5)
131 #define PM3VideoControl_VSYNC_FORCE_LOW (2<<5)
132 #define PM3VideoControl_VSYNC_ACTIVE_LOW (3<<5)
133 #define PM3VideoControl_VSYNC_MASK (3<<5)
134 #define PM3VideoControl_BYTE_DOUBLE_OFF (0<<7)
135 #define PM3VideoControl_BYTE_DOUBLE_ON (1<<7)
136 #define PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK (0<<9)
137 #define PM3VideoControl_BUFFER_SWAP_FREE_RUNNING (1<<9)
138 #define PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE (2<<9)
139 #define PM3VideoControl_STEREO_DISABLE (0<<11)
140 #define PM3VideoControl_STEREO_ENABLE (1<<11)
141 #define PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH (0<<12)
142 #define PM3VideoControl_RIGHT_EYE_ACTIVE_LOW (1<<12)
143 #define PM3VideoControl_VIDEO_EXT_LOW (0<<14)
144 #define PM3VideoControl_VIDEO_EXT_HIGH (1<<14)
145 #define PM3VideoControl_SYNC_MODE_INDEPENDENT (0<<16)
146 #define PM3VideoControl_SYNC_MODE_SYNCTO_VSA (1<<16)
147 #define PM3VideoControl_SYNC_MODE_SYNCTO_VSB (2<<16)
148 #define PM3VideoControl_PATCH_DISABLE (0<<18)
149 #define PM3VideoControl_PATCH_ENABLE (1<<18)
150 #define PM3VideoControl_PIXELSIZE_8BIT (0<<19)
151 #define PM3VideoControl_PIXELSIZE_16BIT (1<<19)
152 #define PM3VideoControl_PIXELSIZE_32BIT (2<<19)
153 #define PM3VideoControl_DISPLAY_DISABLE (0<<21)
154 #define PM3VideoControl_DISPLAY_ENABLE (1<<21)
155 #define PM3VideoControl_PATCH_OFFSET_X(off) (((off)&0x3f)<<22)
156 #define PM3VideoControl_PATCH_OFFSET_Y(off) (((off)&0x3f)<<28)
157#define PM3InterruptLine 0x3060
158#define PM3DisplayData 0x3068
159#define PM3VerticalLineCount 0x3070
160#define PM3FifoControl 0x3078
161#define PM3ScreenBaseRight 0x3080
162#define PM3MiscControl 0x3088
163
164#define PM3VideoOverlayUpdate 0x3100
165 #define PM3VideoOverlayUpdate_DISABLE (0<<0)
166 #define PM3VideoOverlayUpdate_ENABLE (1<<0)
167#define PM3VideoOverlayMode 0x3108
168 #define PM3VideoOverlayMode_DISABLE (0<<0)
169 #define PM3VideoOverlayMode_ENABLE (1<<0)
170 #define PM3VideoOverlayMode_BUFFERSYNC_MANUAL (0<<1)
171 #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA (1<<1)
172 #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB (2<<1)
173 #define PM3VideoOverlayMode_FIELDPOLARITY_NORMAL (0<<4)
174 #define PM3VideoOverlayMode_FIELDPOLARITY_INVERT (1<<4)
175 #define PM3VideoOverlayMode_PIXELSIZE_8BIT (0<<5)
176 #define PM3VideoOverlayMode_PIXELSIZE_16BIT (1<<5)
177 #define PM3VideoOverlayMode_PIXELSIZE_32BIT (2<<5)
178 #define PM3VideoOverlayMode_COLORFORMAT_RGB8888 ((0<<7)|(1<<12)|(2<<5))
179 #define PM3VideoOverlayMode_COLORFORMAT_RGB4444 ((1<<7)|(1<<12)|(1<<5))
180 #define PM3VideoOverlayMode_COLORFORMAT_RGB5551 ((2<<7)|(1<<12)|(1<<5))
181 #define PM3VideoOverlayMode_COLORFORMAT_RGB565 ((3<<7)|(1<<12)|(1<<5))
182 #define PM3VideoOverlayMode_COLORFORMAT_RGB332 ((4<<7)|(1<<12)|(0<<5))
183 #define PM3VideoOverlayMode_COLORFORMAT_BGR8888 ((0<<7)|(2<<5))
184 #define PM3VideoOverlayMode_COLORFORMAT_BGR4444 ((1<<7)|(1<<5))
185 #define PM3VideoOverlayMode_COLORFORMAT_BGR5551 ((2<<7)|(1<<5))
186 #define PM3VideoOverlayMode_COLORFORMAT_BGR565 ((3<<7)|(1<<5))
187 #define PM3VideoOverlayMode_COLORFORMAT_BGR332 ((4<<7)|(0<<5))
188 #define PM3VideoOverlayMode_COLORFORMAT_CI8 ((5<<7)|(1<<12)|(0<<5))
189 #define PM3VideoOverlayMode_COLORFORMAT_VUY444 ((2<<10)|(1<<12)|(2<<5))
190 #define PM3VideoOverlayMode_COLORFORMAT_YUV444 ((2<<10)|(2<<5))
191 #define PM3VideoOverlayMode_COLORFORMAT_VUY422 ((1<<10)|(1<<12)|(1<<5))
192 #define PM3VideoOverlayMode_COLORFORMAT_YUV422 ((1<<10)|(1<<5))
193 #define PM3VideoOverlayMode_COLORORDER_BGR (0<<12)
194 #define PM3VideoOverlayMode_COLORORDER_RGB (1<<12)
195 #define PM3VideoOverlayMode_LINEARCOLOREXT_OFF (0<<13)
196 #define PM3VideoOverlayMode_LINEARCOLOREXT_ON (1<<13)
197 #define PM3VideoOverlayMode_FILTER_MASK (3<<14)
198 #define PM3VideoOverlayMode_FILTER_OFF (0<<14)
199 #define PM3VideoOverlayMode_FILTER_FULL (1<<14)
200 #define PM3VideoOverlayMode_FILTER_PARTIAL (2<<14)
201 #define PM3VideoOverlayMode_DEINTERLACE_OFF (0<<16)
202 #define PM3VideoOverlayMode_DEINTERLACE_BOB (1<<16)
203 #define PM3VideoOverlayMode_PATCHMODE_OFF (0<<18)
204 #define PM3VideoOverlayMode_PATCHMODE_ON (1<<18)
205 #define PM3VideoOverlayMode_FLIP_VIDEO (0<<20)
206 #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMA (1<<20)
207 #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMB (2<<20)
208 #define PM3VideoOverlayMode_MIRROR_MASK (3<<23)
209 #define PM3VideoOverlayMode_MIRRORX_OFF (0<<23)
210 #define PM3VideoOverlayMode_MIRRORX_ON (1<<23)
211 #define PM3VideoOverlayMode_MIRRORY_OFF (0<<24)
212 #define PM3VideoOverlayMode_MIRRORY_ON (1<<24)
213#define PM3VideoOverlayFifoControl 0x3110
214#define PM3VideoOverlayIndex 0x3118
215#define PM3VideoOverlayBase0 0x3120
216#define PM3VideoOverlayBase1 0x3128
217#define PM3VideoOverlayBase2 0x3130
218#define PM3VideoOverlayStride 0x3138
219 #define PM3VideoOverlayStride_STRIDE(s) (((s)&0xfff)<<0)
220#define PM3VideoOverlayWidth 0x3140
221 #define PM3VideoOverlayWidth_WIDTH(w) (((w)&0xfff)<<0)
222#define PM3VideoOverlayHeight 0x3148
223 #define PM3VideoOverlayHeight_HEIGHT(h) (((h)&0xfff)<<0)
224#define PM3VideoOverlayOrigin 0x3150
225 #define PM3VideoOverlayOrigin_XORIGIN(x) (((x)&0xfff)<<0)
226 #define PM3VideoOverlayOrigin_YORIGIN(y) (((y)&0xfff)<<16)
227#define PM3VideoOverlayShrinkXDelta 0x3158
228 #define PM3VideoOverlayShrinkXDelta_NONE (1<<16)
229 #define PM3VideoOverlayShrinkXDelta_DELTA(s,d) \
230 ((((s)<<16)/(d))&0x0ffffff0)
231#define PM3VideoOverlayZoomXDelta 0x3160
232 #define PM3VideoOverlayZoomXDelta_NONE (1<<16)
233 #define PM3VideoOverlayZoomXDelta_DELTA(s,d) \
234 ((((s)<<16)/(d))&0x0001fff0)
235#define PM3VideoOverlayYDelta 0x3168
236 #define PM3VideoOverlayYDelta_NONE (1<<16)
237 #define PM3VideoOverlayYDelta_DELTA(s,d) \
238 ((((s)<<16)/(d))&0x0ffffff0)
239#define PM3VideoOverlayFieldOffset 0x3170
240#define PM3VideoOverlayStatus 0x3178
241
242/**********************************************
243* GLINT Permedia3 RAMDAC Registers (0x4000) *
244***********************************************/
245/* Direct Registers */
246#define PM3RD_PaletteWriteAddress 0x4000
247#define PM3RD_PaletteData 0x4008
248#define PM3RD_PixelMask 0x4010
249#define PM3RD_PaletteReadAddress 0x4018
250
251#define PM3RD_IndexLow 0x4020
252#define PM3RD_IndexHigh 0x4028
253#define PM3RD_IndexedData 0x4030
254#define PM3RD_IndexControl 0x4038
255 #define PM3RD_IndexControl_AUTOINCREMENT_ENABLE (1<<0)
256 #define PM3RD_IndexControl_AUTOINCREMENT_DISABLE (0<<0)
257
258/* Indirect Registers */
259#define PM3RD_MiscControl 0x000
260 #define PM3RD_MiscControl_HIGHCOLOR_RES_DISABLE (0<<0)
261 #define PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE (1<<0)
262 #define PM3RD_MiscControl_PIXELDOUBLE_DISABLE (0<<1)
263 #define PM3RD_MiscControl_PIXELDOUBLE_ENABLE (1<<1)
264 #define PM3RD_MiscControl_LASTREAD_ADDR_DISABLE (0<<2)
265 #define PM3RD_MiscControl_LASTREAD_ADDR_ENABLE (1<<2)
266 #define PM3RD_MiscControl_DIRECTCOLOR_DISABLE (0<<3)
267 #define PM3RD_MiscControl_DIRECTCOLOR_ENABLE (1<<3)
268 #define PM3RD_MiscControl_OVERLAY_DISABLE (0<<4)
269 #define PM3RD_MiscControl_OVERLAY_ENABLE (1<<4)
270 #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_DISABLE (0<<5)
271 #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE (1<<5)
272 #define PM3RD_MiscControl_VSB_OUTPUT_DISABLE (0<<6)
273 #define PM3RD_MiscControl_VSB_OUTPUT_ENABLE (1<<6)
274 #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_DISABLE (0<<7)
275 #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE (1<<7)
276#define PM3RD_SyncControl 0x001
277 #define PM3RD_SyncControl_HSYNC_ACTIVE_LOW (0<<0)
278 #define PM3RD_SyncControl_HSYNC_ACTIVE_HIGH (1<<0)
279 #define PM3RD_SyncControl_HSYNC_FORCE_ACTIVE (3<<0)
280 #define PM3RD_SyncControl_HSYNC_FORCE_INACTIVE (4<<0)
281 #define PM3RD_SyncControl_HSYNC_TRI_STATE (2<<0)
282 #define PM3RD_SyncControl_VSYNC_ACTIVE_LOW (0<<3)
283 #define PM3RD_SyncControl_VSYNC_ACTIVE_HIGH (1<<3)
284 #define PM3RD_SyncControl_VSYNC_TRI_STATE (2<<3)
285 #define PM3RD_SyncControl_VSYNC_FORCE_ACTIVE (3<<3)
286 #define PM3RD_SyncControl_VSYNC_FORCE_INACTIVE (4<<3)
287 #define PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC (0<<6)
288 #define PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH (1<<6)
289 #define PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC (0<<7)
290 #define PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH (1<<7)
291#define PM3RD_DACControl 0x002
292 #define PM3RD_DACControl_DAC_POWER_ON (0<<0)
293 #define PM3RD_DACControl_DAC_POWER_OFF (1<<0)
294 #define PM3RD_DACControl_SYNC_ON_GREEN_DISABLE (0<<3)
295 #define PM3RD_DACControl_SYNC_ON_GREEN_ENABLE (1<<3)
296 #define PM3RD_DACControl_BLANK_RED_DAC_DISABLE (0<<4)
297 #define PM3RD_DACControl_BLANK_RED_DAC_ENABLE (1<<4)
298 #define PM3RD_DACControl_BLANK_GREEN_DAC_DISABLE (0<<5)
299 #define PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE (1<<5)
300 #define PM3RD_DACControl_BLANK_BLUE_DAC_DISABLE (0<<6)
301 #define PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE (1<<6)
302 #define PM3RD_DACControl_BLANK_PEDESTAL_DISABLE (0<<7)
303 #define PM3RD_DACControl_BLANK_PEDESTAL_ENABLE (1<<7)
304#define PM3RD_PixelSize 0x003
305 #define PM3RD_PixelSize_24_BIT_PIXELS (4<<0)
306 #define PM3RD_PixelSize_32_BIT_PIXELS (2<<0)
307 #define PM3RD_PixelSize_16_BIT_PIXELS (1<<0)
308 #define PM3RD_PixelSize_8_BIT_PIXELS (0<<0)
309#define PM3RD_ColorFormat 0x004
310 #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE (1<<6)
311 #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_DISABLE (0<<6)
312 #define PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW (1<<5)
313 #define PM3RD_ColorFormat_COLOR_ORDER_RED_LOW (0<<5)
314 #define PM3RD_ColorFormat_COLOR_FORMAT_MASK (0x1f<<0)
315 #define PM3RD_ColorFormat_8888_COLOR (0<<0)
316 #define PM3RD_ColorFormat_5551_FRONT_COLOR (1<<0)
317 #define PM3RD_ColorFormat_4444_COLOR (2<<0)
318 #define PM3RD_ColorFormat_332_FRONT_COLOR (5<<0)
319 #define PM3RD_ColorFormat_332_BACK_COLOR (6<<0)
320 #define PM3RD_ColorFormat_2321_FRONT_COLOR (9<<0)
321 #define PM3RD_ColorFormat_2321_BACK_COLOR (10<<0)
322 #define PM3RD_ColorFormat_232_FRONTOFF_COLOR (11<<0)
323 #define PM3RD_ColorFormat_232_BACKOFF_COLOR (12<<0)
324 #define PM3RD_ColorFormat_5551_BACK_COLOR (13<<0)
325 #define PM3RD_ColorFormat_CI8_COLOR (14<<0)
326 #define PM3RD_ColorFormat_565_FRONT_COLOR (16<<0)
327 #define PM3RD_ColorFormat_565_BACK_COLOR (17<<0)
328#define PM3RD_CursorMode 0x005
329 #define PM3RD_CursorMode_CURSOR_DISABLE (0<<0)
330 #define PM3RD_CursorMode_CURSOR_ENABLE (1<<0)
331 #define PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123 (0<<2)
332 #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P0 (1<<2)
333 #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P1 (2<<2)
334 #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P2 (3<<2)
335 #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P3 (4<<2)
336 #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P01 (5<<2)
337 #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P23 (6<<2)
338 #define PM3RD_CursorMode_TYPE_MS (0<<4)
339 #define PM3RD_CursorMode_TYPE_X (1<<4)
340 #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_DISABLE (0<<6)
341 #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE (1<<6)
342 #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR (2<<6)
343 #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR (3<<6)
344#define PM3RD_CursorControl 0x006
345 #define PM3RD_CursorControl_DOUBLE_X_DISABLED (0<<0)
346 #define PM3RD_CursorControl_DOUBLE_X_ENABLED (1<<0)
347 #define PM3RD_CursorControl_DOUBLE_Y_DISABLED (0<<1)
348 #define PM3RD_CursorControl_DOUBLE_Y_ENABLED (1<<1)
349 #define PM3RD_CursorControl_READBACK_POS_DISABLED (0<<2)
350 #define PM3RD_CursorControl_READBACK_POS_ENABLED (1<<2)
351
352#define PM3RD_CursorXLow 0x007
353#define PM3RD_CursorXHigh 0x008
354#define PM3RD_CursorYLow 0x009
355#define PM3RD_CursorYHigh 0x00a
356#define PM3RD_CursorHotSpotX 0x00b
357#define PM3RD_CursorHotSpotY 0x00c
358#define PM3RD_OverlayKey 0x00d
359#define PM3RD_Pan 0x00e
360 #define PM3RD_Pan_DISABLE (0<<0)
361 #define PM3RD_Pan_ENABLE (1<<0)
362 #define PM3RD_Pan_GATE_DISABLE (0<<1)
363 #define PM3RD_Pan_GATE_ENABLE (1<<1)
364#define PM3RD_Sense 0x00f
365
366#define PM3RD_CheckControl 0x018
367 #define PM3RD_CheckControl_PIXEL_DISABLED (0<<0)
368 #define PM3RD_CheckControl_PIXEL_ENABLED (1<<0)
369 #define PM3RD_CheckControl_LUT_DISABLED (0<<1)
370 #define PM3RD_CheckControl_LUT_ENABLED (1<<1)
371#define PM3RD_CheckPixelRed 0x019
372#define PM3RD_CheckPixelGreen 0x01a
373#define PM3RD_CheckPixelBlue 0x01b
374#define PM3RD_CheckLUTRed 0x01c
375#define PM3RD_CheckLUTGreen 0x01d
376#define PM3RD_CheckLUTBlue 0x01e
377#define PM3RD_Scratch 0x01f
378
379#define PM3RD_VideoOverlayControl 0x020
380 #define PM3RD_VideoOverlayControl_DISABLE (0<<0)
381 #define PM3RD_VideoOverlayControl_ENABLE (1<<0)
382 #define PM3RD_VideoOverlayControl_MODE_MASK (3<<1)
383 #define PM3RD_VideoOverlayControl_MODE_MAINKEY (0<<1)
384 #define PM3RD_VideoOverlayControl_MODE_OVERLAYKEY (1<<1)
385 #define PM3RD_VideoOverlayControl_MODE_ALWAYS (2<<1)
386 #define PM3RD_VideoOverlayControl_MODE_BLEND (3<<1)
387 #define PM3RD_VideoOverlayControl_DIRECTCOLOR_DISABLED (0<<3)
388 #define PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED (1<<3)
389 #define PM3RD_VideoOverlayControl_BLENDSRC_MAIN (0<<4)
390 #define PM3RD_VideoOverlayControl_BLENDSRC_REGISTER (1<<4)
391 #define PM3RD_VideoOverlayControl_KEY_COLOR (0<<5)
392 #define PM3RD_VideoOverlayControl_KEY_ALPHA (1<<5)
393#define PM3RD_VideoOverlayXStartLow 0x021
394#define PM3RD_VideoOverlayXStartHigh 0x022
395#define PM3RD_VideoOverlayYStartLow 0x023
396#define PM3RD_VideoOverlayYStartHigh 0x024
397#define PM3RD_VideoOverlayXEndLow 0x025
398#define PM3RD_VideoOverlayXEndHigh 0x026
399#define PM3RD_VideoOverlayYEndLow 0x027
400#define PM3RD_VideoOverlayYEndHigh 0x028
401#define PM3RD_VideoOverlayKeyR 0x029
402#define PM3RD_VideoOverlayKeyG 0x02a
403#define PM3RD_VideoOverlayKeyB 0x02b
404#define PM3RD_VideoOverlayBlend 0x02c
405 #define PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT (0<<6)
406 #define PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT (1<<6)
407 #define PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT (2<<6)
408 #define PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT (3<<6)
409
410#define PM3RD_DClkSetup1 0x1f0
411#define PM3RD_DClkSetup2 0x1f1
412#define PM3RD_KClkSetup1 0x1f2
413#define PM3RD_KClkSetup2 0x1f3
414
415#define PM3RD_DClkControl 0x200
416 #define PM3RD_DClkControl_SOURCE_PLL (0<<4)
417 #define PM3RD_DClkControl_SOURCE_VSA (1<<4)
418 #define PM3RD_DClkControl_SOURCE_VSB (2<<4)
419 #define PM3RD_DClkControl_SOURCE_EXT (3<<4)
420 #define PM3RD_DClkControl_STATE_RUN (2<<2)
421 #define PM3RD_DClkControl_STATE_HIGH (1<<2)
422 #define PM3RD_DClkControl_STATE_LOW (0<<2)
423 #define PM3RD_DClkControl_LOCKED (1<<1)
424 #define PM3RD_DClkControl_NOT_LOCKED (0<<1)
425 #define PM3RD_DClkControl_ENABLE (1<<0)
426 #define PM3RD_DClkControl_DISABLE (0<<0)
427#define PM3RD_DClk0PreScale 0x201
428#define PM3RD_DClk0FeedbackScale 0x202
429#define PM3RD_DClk0PostScale 0x203
430 #define PM3_REF_CLOCK 14318
431#define PM3RD_DClk1PreScale 0x204
432#define PM3RD_DClk1FeedbackScale 0x205
433#define PM3RD_DClk1PostScale 0x206
434#define PM3RD_DClk2PreScale 0x207
435#define PM3RD_DClk2FeedbackScale 0x208
436#define PM3RD_DClk2PostScale 0x209
437#define PM3RD_DClk3PreScale 0x20a
438#define PM3RD_DClk3FeedbackScale 0x20b
439#define PM3RD_DClk3PostScale 0x20c
440#define PM3RD_KClkControl 0x20d
441 #define PM3RD_KClkControl_DISABLE (0<<0)
442 #define PM3RD_KClkControl_ENABLE (1<<0)
443 #define PM3RD_KClkControl_NOT_LOCKED (0<<1)
444 #define PM3RD_KClkControl_LOCKED (1<<1)
445 #define PM3RD_KClkControl_STATE_LOW (0<<2)
446 #define PM3RD_KClkControl_STATE_HIGH (1<<2)
447 #define PM3RD_KClkControl_STATE_RUN (2<<2)
448 #define PM3RD_KClkControl_STATE_LOW_POWER (3<<2)
449 #define PM3RD_KClkControl_SOURCE_PCLK (0<<4)
450 #define PM3RD_KClkControl_SOURCE_HALF_PCLK (1<<4)
451 #define PM3RD_KClkControl_SOURCE_PLL (2<<4)
452#define PM3RD_KClkPreScale 0x20e
453#define PM3RD_KClkFeedbackScale 0x20f
454#define PM3RD_KClkPostScale 0x210
455#define PM3RD_MClkControl 0x211
456 #define PM3RD_MClkControl_DISABLE (0<<0)
457 #define PM3RD_MClkControl_ENABLE (1<<0)
458 #define PM3RD_MClkControl_NOT_LOCKED (0<<1)
459 #define PM3RD_MClkControl_LOCKED (1<<1)
460 #define PM3RD_MClkControl_STATE_LOW (0<<2)
461 #define PM3RD_MClkControl_STATE_HIGH (1<<2)
462 #define PM3RD_MClkControl_STATE_RUN (2<<2)
463 #define PM3RD_MClkControl_STATE_LOW_POWER (3<<2)
464 #define PM3RD_MClkControl_SOURCE_PCLK (0<<4)
465 #define PM3RD_MClkControl_SOURCE_HALF_PCLK (1<<4)
466 #define PM3RD_MClkControl_SOURCE_HALF_EXT (3<<4)
467 #define PM3RD_MClkControl_SOURCE_EXT (4<<4)
468 #define PM3RD_MClkControl_SOURCE_HALF_KCLK (5<<4)
469 #define PM3RD_MClkControl_SOURCE_KCLK (6<<4)
470#define PM3RD_MClkPreScale 0x212
471#define PM3RD_MClkFeedbackScale 0x213
472#define PM3RD_MClkPostScale 0x214
473#define PM3RD_SClkControl 0x215
474 #define PM3RD_SClkControl_DISABLE (0<<0)
475 #define PM3RD_SClkControl_ENABLE (1<<0)
476 #define PM3RD_SClkControl_NOT_LOCKED (0<<1)
477 #define PM3RD_SClkControl_LOCKED (1<<1)
478 #define PM3RD_SClkControl_STATE_LOW (0<<2)
479 #define PM3RD_SClkControl_STATE_HIGH (1<<2)
480 #define PM3RD_SClkControl_STATE_RUN (2<<2)
481 #define PM3RD_SClkControl_STATE_LOW_POWER (3<<2)
482 #define PM3RD_SClkControl_SOURCE_PCLK (0<<4)
483 #define PM3RD_SClkControl_SOURCE_HALF_PCLK (1<<4)
484 #define PM3RD_SClkControl_SOURCE_HALF_EXT (3<<4)
485 #define PM3RD_SClkControl_SOURCE_EXT (4<<4)
486 #define PM3RD_SClkControl_SOURCE_HALF_KCLK (5<<4)
487 #define PM3RD_SClkControl_SOURCE_KCLK (6<<4)
488#define PM3RD_SClkPreScale 0x216
489#define PM3RD_SClkFeedbackScale 0x217
490#define PM3RD_SClkPostScale 0x218
491
492#define PM3RD_CursorPalette(p) (0x303+(p))
493#define PM3RD_CursorPattern(p) (0x400+(p))
494/******************************************************
495* GLINT Permedia3 Video Streaming Registers (0x5000) *
496*******************************************************/
497
498#define PM3VSConfiguration 0x5800
499
500/**********************************************
501* GLINT Permedia3 Core Registers (0x8000+) *
502***********************************************/
503#define PM3AALineWidth 0x94c0
504#define PM3AAPointsize 0x94a0
505#define PM3AlphaBlendAlphaMode 0xafa8
506#define PM3AlphaBlendAlphaModeAnd 0xad30
507#define PM3AlphaBlendAlphaModeOr 0xad38
508#define PM3AlphaBlendColorMode 0xafa0
509#define PM3AlphaBlendColorModeAnd 0xacb0
510#define PM3AlphaBlendColorModeOr 0xacb8
511#define PM3AlphaDestColor 0xaf88
512#define PM3AlphaSourceColor 0xaf80
513#define PM3AlphaTestMode 0x8800
514#define PM3AlphaTestModeAnd 0xabf0
515#define PM3AlphaTestModeOr 0xabf8
516#define PM3AntialiasMode 0x8808
517#define PM3AntialiasModeAnd 0xac00
518#define PM3AntialiasModeOr 0xac08
519/* ... */
520#define PM3BackgroundColor 0xb0c8
521/* ... */
522#define PM3ColorDDAMode 0x87e0
523#define PM3ColorDDAModeAnd 0xabe0
524#define PM3ColorDDAModeOr 0xabe8
525#define PM3CommandInterrupt 0xa990
526#define PM3ConstantColorDDA 0xafb0
527 #define PM3ConstantColorDDA_R(r) ((r)&0xff)
528 #define PM3ConstantColorDDA_G(g) (((g)&0xff)<<8)
529 #define PM3ConstantColorDDA_B(b) (((b)&0xff)<<16)
530 #define PM3ConstantColorDDA_A(a) (((a)&0xff)<<24)
531#define PM3ContextData 0x8dd0
532#define PM3ContextDump 0x8dc0
533#define PM3ContextRestore 0x8dc8
534#define PM3Continue 0x8058
535#define PM3ContinueNewDom 0x8048
536#define PM3ContinueNewLine 0x8040
537#define PM3ContinueNewSub 0x8050
538#define PM3Count 0x8030
539/* ... */
540#define PM3DeltaControl 0x9350
541#define PM3DeltaControlAnd 0xab20
542#define PM3DeltaControlOr 0xab28
543#define PM3DeltaMode 0x9300
544#define PM3DeltaModeAnd 0xaad0
545#define PM3DeltaModeOr 0xaad8
546/* ... */
547#define PM3DitherMode 0x8818
548#define PM3DitherModeAnd 0xacd0
549#define PM3DitherModeOr 0xacd8
550/* ... */
551#define PM3dXDom 0x8008
552#define PM3dXSub 0x8018
553#define PM3dY 0x8028
554/* ... */
555#define PM3FBBlockColor 0x8ac8
556#define PM3FBBlockColor0 0xb060
557#define PM3FBBlockColor1 0xb068
558#define PM3FBBlockColor2 0xb070
559#define PM3FBBlockColor3 0xb078
560#define PM3FBBlockColorBack 0xb0a0
561#define PM3FBBlockColorBack0 0xb080
562#define PM3FBBlockColorBack1 0xb088
563#define PM3FBBlockColorBack2 0xb090
564#define PM3FBBlockColorBack3 0xb098
565#define PM3FBColor 0x8a98
566#define PM3FBDestReadBufferAddr0 0xae80
567#define PM3FBDestReadBufferAddr1 0xae88
568#define PM3FBDestReadBufferAddr2 0xae90
569#define PM3FBDestReadBufferAddr3 0xae98
570#define PM3FBDestReadBufferOffset0 0xaea0
571#define PM3FBDestReadBufferOffset1 0xaea8
572#define PM3FBDestReadBufferOffset2 0xaeb0
573#define PM3FBDestReadBufferOffset3 0xaeb8
574 #define PM3FBDestReadBufferOffset_XOffset(x) ((x)&0xffff)
575 #define PM3FBDestReadBufferOffset_YOffset(y) (((y)&0xffff)<<16)
576#define PM3FBDestReadBufferWidth0 0xaec0
577#define PM3FBDestReadBufferWidth1 0xaec8
578#define PM3FBDestReadBufferWidth2 0xaed0
579#define PM3FBDestReadBufferWidth3 0xaed8
580 #define PM3FBDestReadBufferWidth_Width(w) ((w)&0x0fff)
581
582#define PM3FBDestReadEnables 0xaee8
583#define PM3FBDestReadEnablesAnd 0xad20
584#define PM3FBDestReadEnablesOr 0xad28
585 #define PM3FBDestReadEnables_E(e) ((e)&0xff)
586 #define PM3FBDestReadEnables_E0 1<<0
587 #define PM3FBDestReadEnables_E1 1<<1
588 #define PM3FBDestReadEnables_E2 1<<2
589 #define PM3FBDestReadEnables_E3 1<<3
590 #define PM3FBDestReadEnables_E4 1<<4
591 #define PM3FBDestReadEnables_E5 1<<5
592 #define PM3FBDestReadEnables_E6 1<<6
593 #define PM3FBDestReadEnables_E7 1<<7
594 #define PM3FBDestReadEnables_R(r) (((r)&0xff)<<8)
595 #define PM3FBDestReadEnables_R0 1<<8
596 #define PM3FBDestReadEnables_R1 1<<9
597 #define PM3FBDestReadEnables_R2 1<<10
598 #define PM3FBDestReadEnables_R3 1<<11
599 #define PM3FBDestReadEnables_R4 1<<12
600 #define PM3FBDestReadEnables_R5 1<<13
601 #define PM3FBDestReadEnables_R6 1<<14
602 #define PM3FBDestReadEnables_R7 1<<15
603 #define PM3FBDestReadEnables_ReferenceAlpha(a) (((a)&0xff)<<24)
604
605#define PM3FBDestReadMode 0xaee0
606#define PM3FBDestReadModeAnd 0xac90
607#define PM3FBDestReadModeOr 0xac98
608 #define PM3FBDestReadMode_ReadDisable 0<<0
609 #define PM3FBDestReadMode_ReadEnable 1<<0
610 #define PM3FBDestReadMode_StripePitch(sp) (((sp)&0x7)<<2
611 #define PM3FBDestReadMode_StripeHeight(sh) (((sh)&0x7)<<7
612 #define PM3FBDestReadMode_Enable0 1<<8
613 #define PM3FBDestReadMode_Enable1 1<<9
614 #define PM3FBDestReadMode_Enable2 1<<10
615 #define PM3FBDestReadMode_Enable3 1<<11
616 #define PM3FBDestReadMode_Layout0(l) (((l)&0x3)<<12
617 #define PM3FBDestReadMode_Layout1(l) (((l)&0x3)<<14
618 #define PM3FBDestReadMode_Layout2(l) (((l)&0x3)<<16
619 #define PM3FBDestReadMode_Layout3(l) (((l)&0x3)<<18
620 #define PM3FBDestReadMode_Origin0 1<<20
621 #define PM3FBDestReadMode_Origin1 1<<21
622 #define PM3FBDestReadMode_Origin2 1<<22
623 #define PM3FBDestReadMode_Origin3 1<<23
624 #define PM3FBDestReadMode_Blocking 1<<24
625 #define PM3FBDestReadMode_UseReadEnabled 1<<26
626 #define PM3FBDestReadMode_AlphaFiltering 1<<27
627
628#define PM3FBHardwareWriteMask 0x8ac0
629#define PM3FBSoftwareWriteMask 0x8820
630#define PM3FBData 0x8aa0
631#define PM3FBSourceData 0x8aa8
632#define PM3FBSourceReadBufferAddr 0xaf08
633#define PM3FBSourceReadBufferOffset 0xaf10
634 #define PM3FBSourceReadBufferOffset_XOffset(x) ((x)&0xffff)
635 #define PM3FBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16)
636#define PM3FBSourceReadBufferWidth 0xaf18
637 #define PM3FBSourceReadBufferWidth_Width(w) ((w)&0x0fff)
638#define PM3FBSourceReadMode 0xaf00
639#define PM3FBSourceReadModeAnd 0xaca0
640#define PM3FBSourceReadModeOr 0xaca8
641 #define PM3FBSourceReadMode_ReadDisable (0<<0)
642 #define PM3FBSourceReadMode_ReadEnable (1<<0)
643 #define PM3FBSourceReadMode_StripePitch(sp) (((sp)&0x7)<<2
644 #define PM3FBSourceReadMode_StripeHeight(sh) (((sh)&0x7)<<7
645 #define PM3FBSourceReadMode_Layout(l) (((l)&0x3)<<8
646 #define PM3FBSourceReadMode_Origin 1<<10
647 #define PM3FBSourceReadMode_Blocking 1<<11
648 #define PM3FBSourceReadMode_UserTexelCoord 1<<13
649 #define PM3FBSourceReadMode_WrapXEnable 1<<14
650 #define PM3FBSourceReadMode_WrapYEnable 1<<15
651 #define PM3FBSourceReadMode_WrapX(w) (((w)&0xf)<<16
652 #define PM3FBSourceReadMode_WrapY(w) (((w)&0xf)<<20
653 #define PM3FBSourceReadMode_ExternalSourceData 1<<24
654#define PM3FBWriteBufferAddr0 0xb000
655#define PM3FBWriteBufferAddr1 0xb008
656#define PM3FBWriteBufferAddr2 0xb010
657#define PM3FBWriteBufferAddr3 0xb018
658
659#define PM3FBWriteBufferOffset0 0xb020
660#define PM3FBWriteBufferOffset1 0xb028
661#define PM3FBWriteBufferOffset2 0xb030
662#define PM3FBWriteBufferOffset3 0xb038
663 #define PM3FBWriteBufferOffset_XOffset(x) ((x)&0xffff)
664 #define PM3FBWriteBufferOffset_YOffset(y) (((y)&0xffff)<<16)
665
666#define PM3FBWriteBufferWidth0 0xb040
667#define PM3FBWriteBufferWidth1 0xb048
668#define PM3FBWriteBufferWidth2 0xb050
669#define PM3FBWriteBufferWidth3 0xb058
670 #define PM3FBWriteBufferWidth_Width(w) ((w)&0x0fff)
671
672#define PM3FBWriteMode 0x8ab8
673#define PM3FBWriteModeAnd 0xacf0
674#define PM3FBWriteModeOr 0xacf8
675 #define PM3FBWriteMode_WriteDisable 0<<0
676 #define PM3FBWriteMode_WriteEnable 1<<0
677 #define PM3FBWriteMode_Replicate 1<<4
678 #define PM3FBWriteMode_OpaqueSpan 1<<5
679 #define PM3FBWriteMode_StripePitch(p) (((p)&0x7)<<6)
680 #define PM3FBWriteMode_StripeHeight(h) (((h)&0x7)<<9)
681 #define PM3FBWriteMode_Enable0 1<<12
682 #define PM3FBWriteMode_Enable1 1<<13
683 #define PM3FBWriteMode_Enable2 1<<14
684 #define PM3FBWriteMode_Enable3 1<<15
685 #define PM3FBWriteMode_Layout0(l) (((l)&0x3)<<16)
686 #define PM3FBWriteMode_Layout1(l) (((l)&0x3)<<18)
687 #define PM3FBWriteMode_Layout2(l) (((l)&0x3)<<20)
688 #define PM3FBWriteMode_Layout3(l) (((l)&0x3)<<22)
689 #define PM3FBWriteMode_Origin0 1<<24
690 #define PM3FBWriteMode_Origin1 1<<25
691 #define PM3FBWriteMode_Origin2 1<<26
692 #define PM3FBWriteMode_Origin3 1<<27
693#define PM3ForegroundColor 0xb0c0
694/* ... */
695#define PM3GIDMode 0xb538
696#define PM3GIDModeAnd 0xb5b0
697#define PM3GIDModeOr 0xb5b8
698/* ... */
699#define PM3LBDestReadBufferAddr 0xb510
700#define PM3LBDestReadBufferOffset 0xb518
701#define PM3LBDestReadEnables 0xb508
702#define PM3LBDestReadEnablesAnd 0xb590
703#define PM3LBDestReadEnablesOr 0xb598
704#define PM3LBDestReadMode 0xb500
705#define PM3LBDestReadModeAnd 0xb580
706#define PM3LBDestReadModeOr 0xb588
707 #define PM3LBDestReadMode_Disable 0<<0
708 #define PM3LBDestReadMode_Enable 1<<0
709 #define PM3LBDestReadMode_StripePitch(p) (((p)&0x7)<<2)
710 #define PM3LBDestReadMode_StripeHeight(h) (((h)&0x7)<<5)
711 #define PM3LBDestReadMode_Layout 1<<8
712 #define PM3LBDestReadMode_Origin 1<<9
713 #define PM3LBDestReadMode_UserReadEnables 1<<10
714 #define PM3LBDestReadMode_Packed16 1<<11
715 #define PM3LBDestReadMode_Width(w) (((w)&0xfff)<<12)
716#define PM3LBReadFormat 0x8888
717 #define PM3LBReadFormat_DepthWidth(w) (((w)&0x3)<<0)
718 #define PM3LBReadFormat_StencilWidth(w) (((w)&0xf)<<2)
719 #define PM3LBReadFormat_StencilPosition(p) (((p)&0x1f)<<6)
720 #define PM3LBReadFormat_FCPWidth(w) (((w)&0xf)<<11)
721 #define PM3LBReadFormat_FCPPosition(p) (((p)&0x1f)<<15)
722 #define PM3LBReadFormat_GIDWidth(w) (((w)&0x7)<<20)
723 #define PM3LBReadFormat_GIDPosition(p) (((p)&0x1f)<<23)
724#define PM3LBSourceReadBufferAddr 0xb528
725#define PM3LBSourceReadBufferOffset 0xb530
726#define PM3LBSourceReadMode 0xb520
727#define PM3LBSourceReadModeAnd 0xb5a0
728#define PM3LBSourceReadModeOr 0xb5a8
729 #define PM3LBSourceReadMode_Enable 1<<0
730 #define PM3LBSourceReadMode_StripePitch(p) (((p)&0x7)<<2)
731 #define PM3LBSourceReadMode_StripeHeight(h) (((h)&0x7)<<5)
732 #define PM3LBSourceReadMode_Layout 1<<8
733 #define PM3LBSourceReadMode_Origin 1<<9
734 #define PM3LBSourceReadMode_Packed16 1<<10
735 #define PM3LBSourceReadMode_Width(w) (((w)&0xfff)<<11)
736#define PM3LBStencil 0x88a8
737#define PM3LBWriteBufferAddr 0xb540
738#define PM3LBWriteBufferOffset 0xb548
739#define PM3LBWriteFormat 0x88c8
740 #define PM3LBWriteFormat_DepthWidth(w) (((w)&0x3)<<0)
741 #define PM3LBWriteFormat_StencilWidth(w) (((w)&0xf)<<2)
742 #define PM3LBWriteFormat_StencilPosition(p) (((p)&0x1f)<<6)
743 #define PM3LBWriteFormat_GIDWidth(w) (((w)&0x7)<<20)
744 #define PM3LBWriteFormat_GIDPosition(p) (((p)&0x1f)<<23)
745#define PM3LBWriteMode 0x88c0
746#define PM3LBWriteModeAnd 0xac80
747#define PM3LBWriteModeOr 0xac88
748 #define PM3LBWriteMode_WriteDisable 0<<0
749 #define PM3LBWriteMode_WriteEnable 1<<0
750 #define PM3LBWriteMode_StripePitch(p) (((p)&0x7)<<3)
751 #define PM3LBWriteMode_StripeHeight(h) (((h)&0x7)<<6)
752 #define PM3LBWriteMode_Layout 1<<9
753 #define PM3LBWriteMode_Origin 1<<10
754 #define PM3LBWriteMode_Packed16 1<<11
755 #define PM3LBWriteMode_Width(w) (((w)&0xfff)<<12)
756/* ... */
757#define PM3LineStippleMode 0x81a8
758#define PM3LineStippleModeAnd 0xabc0
759#define PM3LineStippleModeOr 0xabc8
760#define PM3LoadLineStippleCounters 0x81b0
761/* ... */
762#define PM3LogicalOpMode 0x8828
763#define PM3LogicalOpModeAnd 0xace0
764#define PM3LogicalOpModeOr 0xace8
765 #define PM3LogicalOpMode_Disable (0<<0)
766 #define PM3LogicalOpMode_Enable (1<<0)
767 #define PM3LogicalOpMode_LogicOp(op) (((op)&0xf)<<1)
768 #define PM3LogicalOpMode_UseConstantWriteData_Disable (0<<5)
769 #define PM3LogicalOpMode_UseConstantWriteData_Enable (1<<5)
770 #define PM3LogicalOpMode_Background_Disable (0<<6)
771 #define PM3LogicalOpMode_Background_Enable (1<<6)
772 #define PM3LogicalOpMode_Background_LogicOp(op) (((op)&0xf)<<7)
773 #define PM3LogicalOpMode_UseConstantSource_Disable (0<<11)
774 #define PM3LogicalOpMode_UseConstantSource_Enable (1<<11)
775
776/* ... */
777#define PM3LUT 0x8e80
778/* ... */
779#define PM3LUT 0x8e80
780#define PM3LUTAddress 0x84d0
781#define PM3LUTData 0x84c8
782#define PM3LUTIndex 0x84c0
783#define PM3LUTMode 0xb378
784#define PM3LUTModeAnd 0xad70
785#define PM3LUTModeOr 0xad78
786#define PM3LUTTransfer 0x84d8
787/* ... */
788#define PM3PixelSize 0x80c0
789 #define PM3PixelSize_GLOBAL_32BIT (0<<0)
790 #define PM3PixelSize_GLOBAL_16BIT (1<<0)
791 #define PM3PixelSize_GLOBAL_8BIT (2<<0)
792 #define PM3PixelSize_RASTERIZER_32BIT (0<<2)
793 #define PM3PixelSize_RASTERIZER_16BIT (1<<2)
794 #define PM3PixelSize_RASTERIZER_8BIT (2<<2)
795 #define PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT (0<<4)
796 #define PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT (1<<4)
797 #define PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT (2<<4)
798 #define PM3PixelSize_TEXTURE_32BIT (0<<6)
799 #define PM3PixelSize_TEXTURE_16BIT (1<<6)
800 #define PM3PixelSize_TEXTURE_8BIT (2<<6)
801 #define PM3PixelSize_LUT_32BIT (0<<8)
802 #define PM3PixelSize_LUT_16BIT (1<<8)
803 #define PM3PixelSize_LUT_8BIT (2<<8)
804 #define PM3PixelSize_FRAMEBUFFER_32BIT (0<<10)
805 #define PM3PixelSize_FRAMEBUFFER_16BIT (1<<10)
806 #define PM3PixelSize_FRAMEBUFFER_8BIT (2<<10)
807 #define PM3PixelSize_LOGICAL_OP_32BIT (0<<12)
808 #define PM3PixelSize_LOGICAL_OP_16BIT (1<<12)
809 #define PM3PixelSize_LOGICAL_OP_8BIT (2<<12)
810 #define PM3PixelSize_LOCALBUFFER_32BIT (0<<14)
811 #define PM3PixelSize_LOCALBUFFER_16BIT (1<<14)
812 #define PM3PixelSize_LOCALBUFFER_8BIT (2<<14)
813 #define PM3PixelSize_SETUP_32BIT (0<<16)
814 #define PM3PixelSize_SETUP_16BIT (1<<16)
815 #define PM3PixelSize_SETUP_8BIT (2<<16)
816 #define PM3PixelSize_GLOBAL (0<<31)
817 #define PM3PixelSize_INDIVIDUAL (1<<31)
818/* ... */
819#define PM3Render 0x8038
820 #define PM3Render_AreaStipple_Disable (0<<0)
821 #define PM3Render_AreaStipple_Enable (1<<0)
822 #define PM3Render_LineStipple_Disable (0<<1)
823 #define PM3Render_LineStipple_Enable (1<<1)
824 #define PM3Render_ResetLine_Disable (0<<2)
825 #define PM3Render_ResetLine_Enable (1<<2)
826 #define PM3Render_FastFill_Disable (0<<3)
827 #define PM3Render_FastFill_Enable (1<<3)
828 #define PM3Render_Primitive_Line (0<<6)
829 #define PM3Render_Primitive_Trapezoid (1<<6)
830 #define PM3Render_Primitive_Point (2<<6)
831 #define PM3Render_Antialias_Disable (0<<8)
832 #define PM3Render_Antialias_Enable (1<<8)
833 #define PM3Render_Antialias_SubPixelRes_4x4 (0<<9)
834 #define PM3Render_Antialias_SubPixelRes_8x8 (1<<9)
835 #define PM3Render_UsePointTable_Disable (0<<10)
836 #define PM3Render_UsePointTable_Enable (1<<10)
837 #define PM3Render_SyncOnbitMask_Disable (0<<11)
838 #define PM3Render_SyncOnBitMask_Enable (1<<11)
839 #define PM3Render_SyncOnHostData_Disable (0<<12)
840 #define PM3Render_SyncOnHostData_Enable (1<<12)
841 #define PM3Render_Texture_Disable (0<<13)
842 #define PM3Render_Texture_Enable (1<<13)
843 #define PM3Render_Fog_Disable (0<<14)
844 #define PM3Render_Fog_Enable (1<<14)
845 #define PM3Render_Coverage_Disable (0<<15)
846 #define PM3Render_Coverage_Enable (1<<15)
847 #define PM3Render_SubPixelCorrection_Disable (0<<16)
848 #define PM3Render_SubPixelCorrection_Enable (1<<16)
849 #define PM3Render_SpanOperation_Disable (0<<18)
850 #define PM3Render_SpanOperation_Enable (1<<18)
851 #define PM3Render_FBSourceRead_Disable (0<<27)
852 #define PM3Render_FBSourceRead_Enable (1<<27)
853#define PM3RasterizerMode 0x80a0
854#define PM3RasterizerModeAnd 0xaba0
855#define PM3RasterizerModeOr 0xabb8
856#define PM3RectangleHeight 0x94e0
857#define PM3Render 0x8038
858#define PM3RepeatLine 0x9328
859#define PM3ResetPickResult 0x8c20
860#define PM3RLEMask 0x8c48
861#define PM3RouterMode 0x8840
862#define PM3RStart 0x8780
863#define PM3S1Start 0x8400
864#define PM3aveLineStippleCounters 0x81c0
865#define PM3ScissorMaxXY 0x8190
866#define PM3ScissorMinXY 0x8188
867#define PM3ScissorMode 0x8180
868#define PM3ScissorModeAnd 0xabb0
869#define PM3ScissorModeOr 0xabb8
870#define PM3ScreenSize 0x8198
871#define PM3Security 0x8908
872#define PM3SetLogicalTexturePage 0xb360
873#define PM3SizeOfFramebuffer 0xb0a8
874#define PM3SStart 0x8388
875#define PM3StartXDom 0x8000
876#define PM3StartXSub 0x8010
877#define PM3StartY 0x8020
878/* ... */
879#define PM3SpanColorMask 0x8168
880/* ... */
881#define PM3TextureApplicationMode 0x8680
882#define PM3TextureApplicationModeAnd 0xac50
883#define PM3TextureApplicationModeOr 0xac58
884#define PM3TextureBaseAddr 0x8500
885#define PM3TextureCacheControl 0x8490
886#define PM3TextureChromaLower0 0x84f0
887#define PM3TextureChromaLower1 0x8608
888#define PM3TextureChromaUpper0 0x84e8
889#define PM3TextureChromaUpper1 0x8600
890#define PM3TextureCompositeAlphaMode0 0xb310
891#define PM3TextureCompositeAlphaMode0And 0xb390
892#define PM3TextureCompositeAlphaMode0Or 0xb398
893#define PM3TextureCompositeAlphaMode1 0xb320
894#define PM3TextureCompositeAlphaMode1And 0xb3b0
895#define PM3TextureCompositeAlphaMode1Or 0xb3b8
896#define PM3TextureCompositeColorMode0 0xb308
897#define PM3TextureCompositeColorMode0And 0xb380
898#define PM3TextureCompositeColorMode0Or 0xb388
899#define PM3TextureCompositeColorMode1 0xb318
900#define PM3TextureCompositeColorMode1And 0xb3a0
901#define PM3TextureCompositeColorMode1Or 0xb3a8
902#define PM3TextureCompositeFactor0 0xb328
903#define PM3TextureCompositeFactor1 0xb330
904#define PM3TextureCompositeMode 0xb300
905#define PM3TextureCoordMode 0x8380
906#define PM3TextureCoordModeAnd 0xac20
907#define PM3TextureCoordModeOr 0xac28
908#define PM3TextureData 0x88e8
909/*
910#define PM3TextureDownloadControl 0x0108
911*/
912#define PM3TextureDownloadOffset 0x88f0
913#define PM3TextureEnvColor 0x8688
914#define PM3TextureFilterMode 0x84e0
915#define PM3TextureFilterModeAnd 0xad50
916#define PM3TextureFilterModeOr 0xad58
917#define PM3TextureIndexMode0 0xb338
918#define PM3TextureIndexMode0And 0xb3c0
919#define PM3TextureIndexMode0Or 0xb3c8
920#define PM3TextureIndexMode1 0xb340
921#define PM3TextureIndexMode1And 0xb3d0
922#define PM3TextureIndexMode1Or 0xb3d8
923/* ... */
924#define PM3TextureMapSize 0xb428
925#define PM3TextureMapWidth0 0x8580
926#define PM3TextureMapWidth1 0x8588
927 #define PM3TextureMapWidth_Width(w) ((w&0xfff)<<0)
928 #define PM3TextureMapWidth_BorderLayout (1<<12)
929 #define PM3TextureMapWidth_Layout_Linear (0<<13)
930 #define PM3TextureMapWidth_Layout_Patch64 (1<<13)
931 #define PM3TextureMapWidth_Layout_Patch32_2 (2<<13)
932 #define PM3TextureMapWidth_Layout_Patch2 (3<<13)
933 #define PM3TextureMapWidth_HostTexture (1<<15)
934#define PM3TextureReadMode0 0xb400
935#define PM3TextureReadMode0And 0xac30
936#define PM3TextureReadMode0Or 0xac38
937#define PM3TextureReadMode1 0xb408
938#define PM3TextureReadMode1And 0xad40
939#define PM3TextureReadMode1Or 0xad48
940/* ... */
941#define PM3WaitForCompletion 0x80b8
942#define PM3Window 0x8980
943 #define PM3Window_ForceLBUpdate 1<<3
944 #define PM3Window_LBUpdateSource 1<<4
945 #define PM3Window_FrameCount(c) (((c)&0xff)<<9
946 #define PM3Window_StencilFCP 1<<17
947 #define PM3Window_DepthFCP 1<<18
948 #define PM3Window_OverrideWriteFiltering 1<<19
949#define PM3WindowAnd 0xab80
950#define PM3WindowOr 0xab88
951#define PM3WindowOrigin 0x81c8
952#define PM3XBias 0x9480
953#define PM3YBias 0x9488
954#define PM3YLimits 0x80a8
955#define PM3UVMode 0x8f00
956#define PM3ZFogBias 0x86b8
957#define PM3ZStart 0xadd8
958#define PM3ZStartL 0x89b8
959#define PM3ZStartU 0x89b0
960
961
962/**********************************************
963* GLINT Permedia3 2D setup Unit *
964***********************************************/
965#define PM3Config2D 0xb618
966 #define PM3Config2D_OpaqueSpan 1<<0
967 #define PM3Config2D_MultiRXBlit 1<<1
968 #define PM3Config2D_UserScissorEnable 1<<2
969 #define PM3Config2D_FBDestReadEnable 1<<3
970 #define PM3Config2D_AlphaBlendEnable 1<<4
971 #define PM3Config2D_DitherEnable 1<<5
972 #define PM3Config2D_ForegroundROPEnable 1<<6
973 #define PM3Config2D_ForegroundROP(rop) (((rop)&0xf)<<7)
974 #define PM3Config2D_BackgroundROPEnable 1<<11
975 #define PM3Config2D_BackgroundROP(rop) (((rop)&0xf)<<12)
976 #define PM3Config2D_UseConstantSource 1<<16
977 #define PM3Config2D_FBWriteEnable 1<<17
978 #define PM3Config2D_Blocking 1<<18
979 #define PM3Config2D_ExternalSourceData 1<<19
980 #define PM3Config2D_LUTModeEnable 1<<20
981#define PM3DownloadGlyphwidth 0xb658
982 #define PM3DownloadGlyphwidth_GlyphWidth(gw) ((gw)&0xffff)
983#define PM3DownloadTarget 0xb650
984 #define PM3DownloadTarget_TagName(tag) ((tag)&0x1fff)
985#define PM3GlyphData 0xb660
986#define PM3GlyphPosition 0xb608
987 #define PM3GlyphPosition_XOffset(x) ((x)&0xffff)
988 #define PM3GlyphPosition_YOffset(y) (((y)&0xffff)<<16)
989#define PM3Packed4Pixels 0xb668
990#define PM3Packed8Pixels 0xb630
991#define PM3Packed16Pixels 0xb638
992#define PM3RectanglePosition 0xb600
993 #define PM3RectanglePosition_XOffset(x) ((x)&0xffff)
994 #define PM3RectanglePosition_YOffset(y) (((y)&0xffff)<<16)
995#define PM3Render2D 0xb640
996 #define PM3Render2D_Width(w) ((w)&0x0fff)
997 #define PM3Render2D_Operation_Normal 0<<12
998 #define PM3Render2D_Operation_SyncOnHostData 1<<12
999 #define PM3Render2D_Operation_SyncOnBitMask 2<<12
1000 #define PM3Render2D_Operation_PatchOrderRendering 3<<12
1001 #define PM3Render2D_FBSourceReadEnable 1<<14
1002 #define PM3Render2D_SpanOperation 1<<15
1003 #define PM3Render2D_Height(h) (((h)&0x0fff)<<16)
1004 #define PM3Render2D_XPositive 1<<28
1005 #define PM3Render2D_YPositive 1<<29
1006 #define PM3Render2D_AreaStippleEnable 1<<30
1007 #define PM3Render2D_TextureEnable 1<<31
1008#define PM3Render2DGlyph 0xb648
1009 #define PM3Render2DGlyph_Width(w) ((w)&0x7f)
1010 #define PM3Render2DGlyph_Height(h) (((h)&0x7f)<<7)
1011 #define PM3Render2DGlyph_XOffset(x) (((x)&0x1ff)<<14)
1012 #define PM3Render2DGlyph_YOffset(y) (((y)&0x1ff)<<23)
1013#define PM3RenderPatchOffset 0xb610
1014 #define PM3RenderPatchOffset_XOffset(x) ((x)&0xffff)
1015 #define PM3RenderPatchOffset_YOffset(y) (((y)&0xffff)<<16)
1016#define PM3RLCount 0xb678
1017 #define PM3RLCount_Count(c) ((c)&0x0fff)
1018#define PM3RLData 0xb670
1019
1020/**********************************************
1021* GLINT Permedia3 Alias Register *
1022***********************************************/
1023#define PM3FillBackgroundColor 0x8330
1024#define PM3FillConfig2D0 0x8338
1025#define PM3FillConfig2D1 0x8360
1026 #define PM3FillConfig2D_OpaqueSpan 1<<0
1027 #define PM3FillConfig2D_MultiRXBlit 1<<1
1028 #define PM3FillConfig2D_UserScissorEnable 1<<2
1029 #define PM3FillConfig2D_FBDestReadEnable 1<<3
1030 #define PM3FillConfig2D_AlphaBlendEnable 1<<4
1031 #define PM3FillConfig2D_DitherEnable 1<<5
1032 #define PM3FillConfig2D_ForegroundROPEnable 1<<6
1033 #define PM3FillConfig2D_ForegroundROP(rop) (((rop)&0xf)<<7)
1034 #define PM3FillConfig2D_BackgroundROPEnable 1<<11
1035 #define PM3FillConfig2D_BackgroundROP(rop) (((rop)&0xf)<<12)
1036 #define PM3FillConfig2D_UseConstantSource 1<<16
1037 #define PM3FillConfig2D_FBWriteEnable 1<<17
1038 #define PM3FillConfig2D_Blocking 1<<18
1039 #define PM3FillConfig2D_ExternalSourceData 1<<19
1040 #define PM3FillConfig2D_LUTModeEnable 1<<20
1041#define PM3FillFBDestReadBufferAddr 0x8310
1042#define PM3FillFBSourceReadBufferAddr 0x8308
1043#define PM3FillFBSourceReadBufferOffset 0x8340
1044 #define PM3FillFBSourceReadBufferOffset_XOffset(x) ((x)&0xffff)
1045 #define PM3FillFBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16)
1046#define PM3FillFBWriteBufferAddr 0x8300
1047#define PM3FillForegroundColor0 0x8328
1048#define PM3FillForegroundColor1 0x8358
1049#define PM3FillGlyphPosition 0x8368
1050 #define PM3FillGlyphPosition_XOffset(x) ((x)&0xffff)
1051 #define PM3FillGlyphPosition_YOffset(y) (((y)&0xffff)<<16)
1052#define PM3FillRectanglePosition 0x8348
1053 #define PM3FillRectanglePosition_XOffset(x) ((x)&0xffff)
1054 #define PM3FillRectanglePosition_YOffset(y) (((y)&0xffff)<<16)
1055
1056#define PM3_REGS_SIZE 0x10000
1057#define PM3_MAX_PIXCLOCK 300000
1058/* a few more useful registers & regs value... */
1059#define PM3Sync 0x8c40
1060 #define PM3Sync_Tag 0x188
1061#define PM3FilterMode 0x8c00
1062 #define PM3FilterModeSync 0x400
1063#define PM3OutputFifo 0x2000
1064#define PM3StatisticMode 0x8c08
1065#define PM3AreaStippleMode 0x81a0
1066 #define AreaStipplePattern0 (0x8200)
1067 #define AreaStipplePattern1 (0x8208)
1068 #define AreaStipplePattern2 (0x8210)
1069 #define AreaStipplePattern3 (0x8218)
1070 #define AreaStipplePattern4 (0x8220)
1071 #define AreaStipplePattern5 (0x8228)
1072 #define AreaStipplePattern6 (0x8230)
1073 #define AreaStipplePattern7 (0x8238)
1074 #define AreaStipplePattern8 (0x8240)
1075 #define AreaStipplePattern9 (0x8248)
1076 #define AreaStipplePattern10 (0x8250)
1077 #define AreaStipplePattern11 (0x8258)
1078 #define AreaStipplePattern12 (0x8260)
1079 #define AreaStipplePattern13 (0x8268)
1080 #define AreaStipplePattern14 (0x8270)
1081 #define AreaStipplePattern15 (0x8278)
1082 #define AreaStipplePattern16 (0x8280)
1083 #define AreaStipplePattern17 (0x8288)
1084 #define AreaStipplePattern18 (0x8290)
1085 #define AreaStipplePattern19 (0x8298)
1086 #define AreaStipplePattern20 (0x82a0)
1087 #define AreaStipplePattern21 (0x82a8)
1088 #define AreaStipplePattern22 (0x82b0)
1089 #define AreaStipplePattern23 (0x82b8)
1090 #define AreaStipplePattern24 (0x82c0)
1091 #define AreaStipplePattern25 (0x82c8)
1092 #define AreaStipplePattern26 (0x82d0)
1093 #define AreaStipplePattern27 (0x82d8)
1094 #define AreaStipplePattern28 (0x82eo)
1095 #define AreaStipplePattern29 (0x82e8)
1096 #define AreaStipplePattern30 (0x82f0)
1097 #define AreaStipplePattern31 (0x82f8)
1098 #define AreaStipplePattern_indexed(i) (0x8200 + ((i) * 0x8))
1099
1100#define PM3DepthMode 0x89a0
1101#define PM3StencilMode 0x8988
1102#define PM3StencilData 0x8990
1103#define PM3TextureReadMode 0x8670
1104#define PM3FogMode 0x8690
1105#define PM3ChromaTestMode 0x8f18
1106#define PM3YUVMode 0x8f00
1107#define PM3BitMaskPattern 0x8068
1108
1109/* ***************************** */
1110/* ***** pm3fb IOCTL const ***** */
1111/* ***************************** */
1112/* debug-only IOCTL */
1113#define PM3FBIO_CLEARMEMORY 0x504D3300 /* 'PM3\000' */
1114#define PM3FBIO_CLEARCMAP 0x504D3301 /* 'PM3\001' */
1115/* common use IOCTL */
1116#define PM3FBIO_RESETCHIP 0x504D33FF /* 'PM3\377' */
1117
1118/* ***************************************** */
1119/* ***** pm3fb useful define and macro ***** */
1120/* ***************************************** */
1121
1122/* permedia3 -specific definitions */
1123#define PM3_SCALE_TO_CLOCK(pr, fe, po) ((2 * PM3_REF_CLOCK * fe) / (pr * (1 << (po))))
1124
1125/* in case it's not in linux/pci.h */
1126#ifndef PCI_DEVICE_ID_3DLABS_PERMEDIA3
1127#define PCI_DEVICE_ID_3DLABS_PERMEDIA3 0x000a
1128#endif
1129
1130/* max number of simultaneous board */
1131/* warning : make sure module array def's are coherent with PM3_MAX_BOARD */
1132#define PM3_MAX_BOARD 4
1133#define PM3_MAX_BOARD_MODULE_ARRAY_SHORT "1-4h"
1134#define PM3_MAX_BOARD_MODULE_ARRAY_STRING "1-4s"
1135
1136/* max size of options */
1137#define PM3_OPTIONS_SIZE 256
1138
1139/* max size of font name */
1140#define PM3_FONTNAME_SIZE 40
1141
1142/* do we want accelerated console */
1143#define PM3FB_USE_ACCEL 1
1144
1145/* useful ? */
1146#define CHAR_IS_NUM(a) ((((a) >= '0') && ((a) <= '9')) ? 1 : 0)
1147
1148/* for driver debugging ONLY */
1149/* 0 = assert only, 1 = error, 2 = info, 3+ = verbose */
1150/* define PM3FB_MASTER_DEBUG 1 */
1151#if defined(PM3FB_MASTER_DEBUG) && (PM3FB_MASTER_DEBUG >= 3)
1152#define PM3FB_TRACE
1153#endif /* defined(PM3FB_MASTER_DEBUG) && (PM3FB_MASTER_DEBUG >= 3) */
1154
1155#ifdef PM3FB_MASTER_DEBUG
1156#define DPRINTK(l,a,b...) do { if ((l) <= PM3FB_MASTER_DEBUG) printk("pm3fb: %s: " a, __FUNCTION__ , ## b); } while (0)
1157#define DASSERT(t,a,b...) do { if (!(t)) printk("pm3fb: _assert failed: %s: " a, __FUNCTION__ , ## b); } while (0)
1158#ifdef PM3FB_TRACE
1159#define DTRACE printk("pm3fb: _enter %s\n", __FUNCTION__)
1160#else /* PM3FB_TRACE */
1161#define DTRACE
1162#endif /* PM3FB_TRACE */
1163#else /* PM3FB_MASTER_DEBUG */
1164#define DPRINTK(l,a,b...)
1165#define DASSERT(t,a,b...)
1166#define DTRACE
1167#endif /* PM3FB_MASTER_DEBUG */
1168
1169#if defined(PM3FB_MASTER_DEBUG) && (PM3FB_MASTER_DEBUG >= 2)
1170#define PM3_SHOW_CUR_MODE pm3fb_show_cur_mode(l_fb_info)
1171#else
1172#define PM3_SHOW_CUR_MODE /* pm3fb_show_cur_mode() */
1173#endif
1174
1175/* ******************************************** */
1176/* ***** A bunch of register-access macro ***** */
1177/* ******************************************** */
1178
1179#define PM3_WRITE_REG(r, v) fb_writel(v, (l_fb_info->vIOBase + r))
1180#define PM3_READ_REG(r) fb_readl((l_fb_info->vIOBase + r))
1181
1182
1183#define depth2bpp(d) ((d + 7L) & ~7L)
1184#define depth2ByPP(d) (depth2bpp(d) / 8)
1185
1186#define depth_supported(d) ((d == 8) || (d == 12) || (d == 15) || (d == 16) || (d==32))
1187
1188
1189#define PM3_WAIT(n) \
1190do{ \
1191 while(PM3_READ_REG(PM3InFIFOSpace)<(n)); \
1192} while(0)
1193
1194#define PM3_DELAY(x) do { \
1195 int delay = x; \
1196 unsigned char tmp; \
1197 while(delay--){tmp = PM3_READ_REG(PM3InFIFOSpace);}; \
1198} while(0)
1199
1200#define PM3_SLOW_WRITE_REG(r,v) \
1201do{ \
1202 DASSERT((l_fb_info->vIOBase != (unsigned char*)(-1)), "l_fb_info->vIOBase mapped in slow write\n"); \
1203 mb(); \
1204 PM3_WAIT(1); \
1205 mb(); \
1206 PM3_WRITE_REG(r,v); \
1207} while(0)
1208
1209#define PM3_SET_INDEX(index) \
1210do{ \
1211 PM3_SLOW_WRITE_REG(PM3RD_IndexHigh,(((index)>>8)&0xff)); \
1212 PM3_SLOW_WRITE_REG(PM3RD_IndexLow,((index)&0xff)); \
1213} while(0)
1214
1215#define PM3_WRITE_DAC_REG(r, v) \
1216do { \
1217 DASSERT((l_fb_info->vIOBase != (unsigned char*)(-1)), "l_fb_info->vIOBase mapped in write dac reg\n"); \
1218 PM3_SET_INDEX(r); \
1219 mb(); \
1220 PM3_WRITE_REG(PM3RD_IndexedData, v); \
1221} while (0)
1222
1223/* next one is really a function, added as a macro to be consistent */
1224#define PM3_READ_DAC_REG(r) pm3fb_read_dac_reg(l_fb_info, r)
1225
1226
1227#define PM3_COLOR(c) \
1228do { \
1229 if (l_fb_info->current_par->depth == 8) \
1230 { \
1231 c = (c & 0xFF); \
1232 c = c | (c << 8); \
1233 } \
1234 if ((l_fb_info->current_par->depth == 8) || (depth2bpp(l_fb_info->current_par->depth) == 16)) \
1235 { \
1236 c = (c & 0xFFFF); \
1237 c = c | (c << 16); \
1238 } \
1239} while (0)
1240
1241#endif /* PM3FB_H */
diff --git a/include/video/pmag-ba-fb.h b/include/video/pmag-ba-fb.h
new file mode 100644
index 000000000000..cebef073b9a3
--- /dev/null
+++ b/include/video/pmag-ba-fb.h
@@ -0,0 +1,24 @@
1/*
2 * linux/drivers/video/pmag-ba-fb.h
3 *
4 * TurboChannel PMAG-BA framebuffer card support,
5 * Copyright (C) 1999,2000,2001 by
6 * Michael Engel <engel@unix-ag.org>,
7 * Karsten Merker <merker@linuxtag.org>
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 */
12
13/*
14 * Bt459 RAM DAC register base offset (rel. to TC slot base address)
15 */
16
17#define PMAG_BA_BT459_OFFSET 0x00200000
18
19/*
20 * Begin of PMAG-BA framebuffer memory relative to TC slot address,
21 * resolution is 1024x864x8
22 */
23
24#define PMAG_BA_ONBOARD_FBMEM_OFFSET 0x00000000
diff --git a/include/video/pmagb-b-fb.h b/include/video/pmagb-b-fb.h
new file mode 100644
index 000000000000..87b81a555139
--- /dev/null
+++ b/include/video/pmagb-b-fb.h
@@ -0,0 +1,32 @@
1/*
2 * linux/drivers/video/pmagb-b-fb.h
3 *
4 * TurboChannel PMAGB-B framebuffer card support,
5 * Copyright (C) 1999, 2000, 2001 by
6 * Michael Engel <engel@unix-ag.org> and
7 * Karsten Merker <merker@linuxtag.org>
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
11 */
12
13
14/*
15 * Bt459 RAM DAC register base offset (rel. to TC slot base address)
16 */
17#define PMAGB_B_BT459_OFFSET 0x001C0000
18
19/*
20 * Begin of PMAGB-B framebuffer memory, resolution is configurable:
21 * 1024x864x8 or 1280x1024x8, settable by jumper on the card
22 */
23#define PMAGB_B_ONBOARD_FBMEM_OFFSET 0x00201000
24
25/*
26 * Bt459 register offsets, byte-wide registers
27 */
28
29#define BT459_ADR_LOW BT459_OFFSET + 0x00 /* addr. low */
30#define BT459_ADR_HIGH BT459_OFFSET + 0x04 /* addr. high */
31#define BT459_DATA BT459_OFFSET + 0x08 /* r/w data */
32#define BT459_CMAP BT459_OFFSET + 0x0C /* color map */
diff --git a/include/video/radeon.h b/include/video/radeon.h
new file mode 100644
index 000000000000..83467e18f5e9
--- /dev/null
+++ b/include/video/radeon.h
@@ -0,0 +1,1985 @@
1#ifndef _RADEON_H
2#define _RADEON_H
3
4
5#define RADEON_REGSIZE 0x4000
6
7
8#define MM_INDEX 0x0000
9#define MM_DATA 0x0004
10#define BUS_CNTL 0x0030
11#define HI_STAT 0x004C
12#define BUS_CNTL1 0x0034
13#define I2C_CNTL_1 0x0094
14#define CONFIG_CNTL 0x00E0
15#define CONFIG_MEMSIZE 0x00F8
16#define CONFIG_APER_0_BASE 0x0100
17#define CONFIG_APER_1_BASE 0x0104
18#define CONFIG_APER_SIZE 0x0108
19#define CONFIG_REG_1_BASE 0x010C
20#define CONFIG_REG_APER_SIZE 0x0110
21#define PAD_AGPINPUT_DELAY 0x0164
22#define PAD_CTLR_STRENGTH 0x0168
23#define PAD_CTLR_UPDATE 0x016C
24#define PAD_CTLR_MISC 0x0aa0
25#define AGP_CNTL 0x0174
26#define BM_STATUS 0x0160
27#define CAP0_TRIG_CNTL 0x0950
28#define CAP1_TRIG_CNTL 0x09c0
29#define VIPH_CONTROL 0x0C40
30#define VENDOR_ID 0x0F00
31#define DEVICE_ID 0x0F02
32#define COMMAND 0x0F04
33#define STATUS 0x0F06
34#define REVISION_ID 0x0F08
35#define REGPROG_INF 0x0F09
36#define SUB_CLASS 0x0F0A
37#define BASE_CODE 0x0F0B
38#define CACHE_LINE 0x0F0C
39#define LATENCY 0x0F0D
40#define HEADER 0x0F0E
41#define BIST 0x0F0F
42#define REG_MEM_BASE 0x0F10
43#define REG_IO_BASE 0x0F14
44#define REG_REG_BASE 0x0F18
45#define ADAPTER_ID 0x0F2C
46#define BIOS_ROM 0x0F30
47#define CAPABILITIES_PTR 0x0F34
48#define INTERRUPT_LINE 0x0F3C
49#define INTERRUPT_PIN 0x0F3D
50#define MIN_GRANT 0x0F3E
51#define MAX_LATENCY 0x0F3F
52#define ADAPTER_ID_W 0x0F4C
53#define PMI_CAP_ID 0x0F50
54#define PMI_NXT_CAP_PTR 0x0F51
55#define PMI_PMC_REG 0x0F52
56#define PM_STATUS 0x0F54
57#define PMI_DATA 0x0F57
58#define AGP_CAP_ID 0x0F58
59#define AGP_STATUS 0x0F5C
60#define AGP_COMMAND 0x0F60
61#define AIC_CTRL 0x01D0
62#define AIC_STAT 0x01D4
63#define AIC_PT_BASE 0x01D8
64#define AIC_LO_ADDR 0x01DC
65#define AIC_HI_ADDR 0x01E0
66#define AIC_TLB_ADDR 0x01E4
67#define AIC_TLB_DATA 0x01E8
68#define DAC_CNTL 0x0058
69#define DAC_CNTL2 0x007c
70#define CRTC_GEN_CNTL 0x0050
71#define MEM_CNTL 0x0140
72#define MC_CNTL 0x0140
73#define EXT_MEM_CNTL 0x0144
74#define MC_TIMING_CNTL 0x0144
75#define MC_AGP_LOCATION 0x014C
76#define MEM_IO_CNTL_A0 0x0178
77#define MEM_REFRESH_CNTL 0x0178
78#define MEM_INIT_LATENCY_TIMER 0x0154
79#define MC_INIT_GFX_LAT_TIMER 0x0154
80#define MEM_SDRAM_MODE_REG 0x0158
81#define AGP_BASE 0x0170
82#define MEM_IO_CNTL_A1 0x017C
83#define MC_READ_CNTL_AB 0x017C
84#define MEM_IO_CNTL_B0 0x0180
85#define MC_INIT_MISC_LAT_TIMER 0x0180
86#define MEM_IO_CNTL_B1 0x0184
87#define MC_IOPAD_CNTL 0x0184
88#define MC_DEBUG 0x0188
89#define MC_STATUS 0x0150
90#define MEM_IO_OE_CNTL 0x018C
91#define MC_CHIP_IO_OE_CNTL_AB 0x018C
92#define MC_FB_LOCATION 0x0148
93#define HOST_PATH_CNTL 0x0130
94#define MEM_VGA_WP_SEL 0x0038
95#define MEM_VGA_RP_SEL 0x003C
96#define HDP_DEBUG 0x0138
97#define SW_SEMAPHORE 0x013C
98#define CRTC2_GEN_CNTL 0x03f8
99#define CRTC2_DISPLAY_BASE_ADDR 0x033c
100#define SURFACE_CNTL 0x0B00
101#define SURFACE0_LOWER_BOUND 0x0B04
102#define SURFACE1_LOWER_BOUND 0x0B14
103#define SURFACE2_LOWER_BOUND 0x0B24
104#define SURFACE3_LOWER_BOUND 0x0B34
105#define SURFACE4_LOWER_BOUND 0x0B44
106#define SURFACE5_LOWER_BOUND 0x0B54
107#define SURFACE6_LOWER_BOUND 0x0B64
108#define SURFACE7_LOWER_BOUND 0x0B74
109#define SURFACE0_UPPER_BOUND 0x0B08
110#define SURFACE1_UPPER_BOUND 0x0B18
111#define SURFACE2_UPPER_BOUND 0x0B28
112#define SURFACE3_UPPER_BOUND 0x0B38
113#define SURFACE4_UPPER_BOUND 0x0B48
114#define SURFACE5_UPPER_BOUND 0x0B58
115#define SURFACE6_UPPER_BOUND 0x0B68
116#define SURFACE7_UPPER_BOUND 0x0B78
117#define SURFACE0_INFO 0x0B0C
118#define SURFACE1_INFO 0x0B1C
119#define SURFACE2_INFO 0x0B2C
120#define SURFACE3_INFO 0x0B3C
121#define SURFACE4_INFO 0x0B4C
122#define SURFACE5_INFO 0x0B5C
123#define SURFACE6_INFO 0x0B6C
124#define SURFACE7_INFO 0x0B7C
125#define SURFACE_ACCESS_FLAGS 0x0BF8
126#define SURFACE_ACCESS_CLR 0x0BFC
127#define GEN_INT_CNTL 0x0040
128#define GEN_INT_STATUS 0x0044
129#define CRTC_EXT_CNTL 0x0054
130#define RB3D_CNTL 0x1C3C
131#define WAIT_UNTIL 0x1720
132#define ISYNC_CNTL 0x1724
133#define RBBM_GUICNTL 0x172C
134#define RBBM_STATUS 0x0E40
135#define RBBM_STATUS_alt_1 0x1740
136#define RBBM_CNTL 0x00EC
137#define RBBM_CNTL_alt_1 0x0E44
138#define RBBM_SOFT_RESET 0x00F0
139#define RBBM_SOFT_RESET_alt_1 0x0E48
140#define NQWAIT_UNTIL 0x0E50
141#define RBBM_DEBUG 0x0E6C
142#define RBBM_CMDFIFO_ADDR 0x0E70
143#define RBBM_CMDFIFO_DATAL 0x0E74
144#define RBBM_CMDFIFO_DATAH 0x0E78
145#define RBBM_CMDFIFO_STAT 0x0E7C
146#define CRTC_STATUS 0x005C
147#define GPIO_VGA_DDC 0x0060
148#define GPIO_DVI_DDC 0x0064
149#define GPIO_MONID 0x0068
150#define GPIO_CRT2_DDC 0x006c
151#define PALETTE_INDEX 0x00B0
152#define PALETTE_DATA 0x00B4
153#define PALETTE_30_DATA 0x00B8
154#define CRTC_H_TOTAL_DISP 0x0200
155#define CRTC_H_SYNC_STRT_WID 0x0204
156#define CRTC_V_TOTAL_DISP 0x0208
157#define CRTC_V_SYNC_STRT_WID 0x020C
158#define CRTC_VLINE_CRNT_VLINE 0x0210
159#define CRTC_CRNT_FRAME 0x0214
160#define CRTC_GUI_TRIG_VLINE 0x0218
161#define CRTC_DEBUG 0x021C
162#define CRTC_OFFSET_RIGHT 0x0220
163#define CRTC_OFFSET 0x0224
164#define CRTC_OFFSET_CNTL 0x0228
165#define CRTC_PITCH 0x022C
166#define OVR_CLR 0x0230
167#define OVR_WID_LEFT_RIGHT 0x0234
168#define OVR_WID_TOP_BOTTOM 0x0238
169#define DISPLAY_BASE_ADDR 0x023C
170#define SNAPSHOT_VH_COUNTS 0x0240
171#define SNAPSHOT_F_COUNT 0x0244
172#define N_VIF_COUNT 0x0248
173#define SNAPSHOT_VIF_COUNT 0x024C
174#define FP_CRTC_H_TOTAL_DISP 0x0250
175#define FP_CRTC_V_TOTAL_DISP 0x0254
176#define CRT_CRTC_H_SYNC_STRT_WID 0x0258
177#define CRT_CRTC_V_SYNC_STRT_WID 0x025C
178#define CUR_OFFSET 0x0260
179#define CUR_HORZ_VERT_POSN 0x0264
180#define CUR_HORZ_VERT_OFF 0x0268
181#define CUR_CLR0 0x026C
182#define CUR_CLR1 0x0270
183#define FP_HORZ_VERT_ACTIVE 0x0278
184#define CRTC_MORE_CNTL 0x027C
185#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
186#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
187#define DAC_EXT_CNTL 0x0280
188#define FP_GEN_CNTL 0x0284
189#define FP_HORZ_STRETCH 0x028C
190#define FP_VERT_STRETCH 0x0290
191#define FP_H_SYNC_STRT_WID 0x02C4
192#define FP_V_SYNC_STRT_WID 0x02C8
193#define AUX_WINDOW_HORZ_CNTL 0x02D8
194#define AUX_WINDOW_VERT_CNTL 0x02DC
195//#define DDA_CONFIG 0x02e0
196//#define DDA_ON_OFF 0x02e4
197#define DVI_I2C_CNTL_1 0x02e4
198#define GRPH_BUFFER_CNTL 0x02F0
199#define GRPH2_BUFFER_CNTL 0x03F0
200#define VGA_BUFFER_CNTL 0x02F4
201#define OV0_Y_X_START 0x0400
202#define OV0_Y_X_END 0x0404
203#define OV0_PIPELINE_CNTL 0x0408
204#define OV0_REG_LOAD_CNTL 0x0410
205#define OV0_SCALE_CNTL 0x0420
206#define OV0_V_INC 0x0424
207#define OV0_P1_V_ACCUM_INIT 0x0428
208#define OV0_P23_V_ACCUM_INIT 0x042C
209#define OV0_P1_BLANK_LINES_AT_TOP 0x0430
210#define OV0_P23_BLANK_LINES_AT_TOP 0x0434
211#define OV0_BASE_ADDR 0x043C
212#define OV0_VID_BUF0_BASE_ADRS 0x0440
213#define OV0_VID_BUF1_BASE_ADRS 0x0444
214#define OV0_VID_BUF2_BASE_ADRS 0x0448
215#define OV0_VID_BUF3_BASE_ADRS 0x044C
216#define OV0_VID_BUF4_BASE_ADRS 0x0450
217#define OV0_VID_BUF5_BASE_ADRS 0x0454
218#define OV0_VID_BUF_PITCH0_VALUE 0x0460
219#define OV0_VID_BUF_PITCH1_VALUE 0x0464
220#define OV0_AUTO_FLIP_CNTRL 0x0470
221#define OV0_DEINTERLACE_PATTERN 0x0474
222#define OV0_SUBMIT_HISTORY 0x0478
223#define OV0_H_INC 0x0480
224#define OV0_STEP_BY 0x0484
225#define OV0_P1_H_ACCUM_INIT 0x0488
226#define OV0_P23_H_ACCUM_INIT 0x048C
227#define OV0_P1_X_START_END 0x0494
228#define OV0_P2_X_START_END 0x0498
229#define OV0_P3_X_START_END 0x049C
230#define OV0_FILTER_CNTL 0x04A0
231#define OV0_FOUR_TAP_COEF_0 0x04B0
232#define OV0_FOUR_TAP_COEF_1 0x04B4
233#define OV0_FOUR_TAP_COEF_2 0x04B8
234#define OV0_FOUR_TAP_COEF_3 0x04BC
235#define OV0_FOUR_TAP_COEF_4 0x04C0
236#define OV0_FLAG_CNTRL 0x04DC
237#define OV0_SLICE_CNTL 0x04E0
238#define OV0_VID_KEY_CLR_LOW 0x04E4
239#define OV0_VID_KEY_CLR_HIGH 0x04E8
240#define OV0_GRPH_KEY_CLR_LOW 0x04EC
241#define OV0_GRPH_KEY_CLR_HIGH 0x04F0
242#define OV0_KEY_CNTL 0x04F4
243#define OV0_TEST 0x04F8
244#define SUBPIC_CNTL 0x0540
245#define SUBPIC_DEFCOLCON 0x0544
246#define SUBPIC_Y_X_START 0x054C
247#define SUBPIC_Y_X_END 0x0550
248#define SUBPIC_V_INC 0x0554
249#define SUBPIC_H_INC 0x0558
250#define SUBPIC_BUF0_OFFSET 0x055C
251#define SUBPIC_BUF1_OFFSET 0x0560
252#define SUBPIC_LC0_OFFSET 0x0564
253#define SUBPIC_LC1_OFFSET 0x0568
254#define SUBPIC_PITCH 0x056C
255#define SUBPIC_BTN_HLI_COLCON 0x0570
256#define SUBPIC_BTN_HLI_Y_X_START 0x0574
257#define SUBPIC_BTN_HLI_Y_X_END 0x0578
258#define SUBPIC_PALETTE_INDEX 0x057C
259#define SUBPIC_PALETTE_DATA 0x0580
260#define SUBPIC_H_ACCUM_INIT 0x0584
261#define SUBPIC_V_ACCUM_INIT 0x0588
262#define DISP_MISC_CNTL 0x0D00
263#define DAC_MACRO_CNTL 0x0D04
264#define DISP_PWR_MAN 0x0D08
265#define DISP_TEST_DEBUG_CNTL 0x0D10
266#define DISP_HW_DEBUG 0x0D14
267#define DAC_CRC_SIG1 0x0D18
268#define DAC_CRC_SIG2 0x0D1C
269#define OV0_LIN_TRANS_A 0x0D20
270#define OV0_LIN_TRANS_B 0x0D24
271#define OV0_LIN_TRANS_C 0x0D28
272#define OV0_LIN_TRANS_D 0x0D2C
273#define OV0_LIN_TRANS_E 0x0D30
274#define OV0_LIN_TRANS_F 0x0D34
275#define OV0_GAMMA_0_F 0x0D40
276#define OV0_GAMMA_10_1F 0x0D44
277#define OV0_GAMMA_20_3F 0x0D48
278#define OV0_GAMMA_40_7F 0x0D4C
279#define OV0_GAMMA_380_3BF 0x0D50
280#define OV0_GAMMA_3C0_3FF 0x0D54
281#define DISP_MERGE_CNTL 0x0D60
282#define DISP_OUTPUT_CNTL 0x0D64
283#define DISP_LIN_TRANS_GRPH_A 0x0D80
284#define DISP_LIN_TRANS_GRPH_B 0x0D84
285#define DISP_LIN_TRANS_GRPH_C 0x0D88
286#define DISP_LIN_TRANS_GRPH_D 0x0D8C
287#define DISP_LIN_TRANS_GRPH_E 0x0D90
288#define DISP_LIN_TRANS_GRPH_F 0x0D94
289#define DISP_LIN_TRANS_VID_A 0x0D98
290#define DISP_LIN_TRANS_VID_B 0x0D9C
291#define DISP_LIN_TRANS_VID_C 0x0DA0
292#define DISP_LIN_TRANS_VID_D 0x0DA4
293#define DISP_LIN_TRANS_VID_E 0x0DA8
294#define DISP_LIN_TRANS_VID_F 0x0DAC
295#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
296#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
297#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
298#define RMX_HORZ_PHASE 0x0DBC
299#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
300#define DAC_BROAD_PULSE 0x0DC4
301#define DAC_SKEW_CLKS 0x0DC8
302#define DAC_INCR 0x0DCC
303#define DAC_NEG_SYNC_LEVEL 0x0DD0
304#define DAC_POS_SYNC_LEVEL 0x0DD4
305#define DAC_BLANK_LEVEL 0x0DD8
306#define CLOCK_CNTL_INDEX 0x0008
307#define CLOCK_CNTL_DATA 0x000C
308#define CP_RB_CNTL 0x0704
309#define CP_RB_BASE 0x0700
310#define CP_RB_RPTR_ADDR 0x070C
311#define CP_RB_RPTR 0x0710
312#define CP_RB_WPTR 0x0714
313#define CP_RB_WPTR_DELAY 0x0718
314#define CP_IB_BASE 0x0738
315#define CP_IB_BUFSZ 0x073C
316#define SCRATCH_REG0 0x15E0
317#define GUI_SCRATCH_REG0 0x15E0
318#define SCRATCH_REG1 0x15E4
319#define GUI_SCRATCH_REG1 0x15E4
320#define SCRATCH_REG2 0x15E8
321#define GUI_SCRATCH_REG2 0x15E8
322#define SCRATCH_REG3 0x15EC
323#define GUI_SCRATCH_REG3 0x15EC
324#define SCRATCH_REG4 0x15F0
325#define GUI_SCRATCH_REG4 0x15F0
326#define SCRATCH_REG5 0x15F4
327#define GUI_SCRATCH_REG5 0x15F4
328#define SCRATCH_UMSK 0x0770
329#define SCRATCH_ADDR 0x0774
330#define DP_BRUSH_FRGD_CLR 0x147C
331#define DP_BRUSH_BKGD_CLR 0x1478
332#define DST_LINE_START 0x1600
333#define DST_LINE_END 0x1604
334#define SRC_OFFSET 0x15AC
335#define SRC_PITCH 0x15B0
336#define SRC_TILE 0x1704
337#define SRC_PITCH_OFFSET 0x1428
338#define SRC_X 0x1414
339#define SRC_Y 0x1418
340#define SRC_X_Y 0x1590
341#define SRC_Y_X 0x1434
342#define DST_Y_X 0x1438
343#define DST_WIDTH_HEIGHT 0x1598
344#define DST_HEIGHT_WIDTH 0x143c
345#define DST_OFFSET 0x1404
346#define SRC_CLUT_ADDRESS 0x1780
347#define SRC_CLUT_DATA 0x1784
348#define SRC_CLUT_DATA_RD 0x1788
349#define HOST_DATA0 0x17C0
350#define HOST_DATA1 0x17C4
351#define HOST_DATA2 0x17C8
352#define HOST_DATA3 0x17CC
353#define HOST_DATA4 0x17D0
354#define HOST_DATA5 0x17D4
355#define HOST_DATA6 0x17D8
356#define HOST_DATA7 0x17DC
357#define HOST_DATA_LAST 0x17E0
358#define DP_SRC_ENDIAN 0x15D4
359#define DP_SRC_FRGD_CLR 0x15D8
360#define DP_SRC_BKGD_CLR 0x15DC
361#define SC_LEFT 0x1640
362#define SC_RIGHT 0x1644
363#define SC_TOP 0x1648
364#define SC_BOTTOM 0x164C
365#define SRC_SC_RIGHT 0x1654
366#define SRC_SC_BOTTOM 0x165C
367#define DP_CNTL 0x16C0
368#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
369#define DP_DATATYPE 0x16C4
370#define DP_MIX 0x16C8
371#define DP_WRITE_MSK 0x16CC
372#define DP_XOP 0x17F8
373#define CLR_CMP_CLR_SRC 0x15C4
374#define CLR_CMP_CLR_DST 0x15C8
375#define CLR_CMP_CNTL 0x15C0
376#define CLR_CMP_MSK 0x15CC
377#define DSTCACHE_MODE 0x1710
378#define DSTCACHE_CTLSTAT 0x1714
379#define DEFAULT_PITCH_OFFSET 0x16E0
380#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
381#define DEFAULT_SC_TOP_LEFT 0x16EC
382#define SRC_PITCH_OFFSET 0x1428
383#define DST_PITCH_OFFSET 0x142C
384#define DP_GUI_MASTER_CNTL 0x146C
385#define SC_TOP_LEFT 0x16EC
386#define SC_BOTTOM_RIGHT 0x16F0
387#define SRC_SC_BOTTOM_RIGHT 0x16F4
388#define RB2D_DSTCACHE_MODE 0x3428
389#define RB2D_DSTCACHE_CTLSTAT 0x342C
390#define LVDS_GEN_CNTL 0x02d0
391#define LVDS_PLL_CNTL 0x02d4
392#define FP2_GEN_CNTL 0x0288
393#define TMDS_CNTL 0x0294
394#define TMDS_CRC 0x02a0
395#define TMDS_TRANSMITTER_CNTL 0x02a4
396#define MPP_TB_CONFIG 0x01c0
397#define PAMAC0_DLY_CNTL 0x0a94
398#define PAMAC1_DLY_CNTL 0x0a98
399#define PAMAC2_DLY_CNTL 0x0a9c
400#define FW_CNTL 0x0118
401#define FCP_CNTL 0x0910
402#define VGA_DDA_ON_OFF 0x02ec
403#define TV_MASTER_CNTL 0x0800
404
405//#define BASE_CODE 0x0f0b
406#define BIOS_0_SCRATCH 0x0010
407#define BIOS_1_SCRATCH 0x0014
408#define BIOS_2_SCRATCH 0x0018
409#define BIOS_3_SCRATCH 0x001c
410#define BIOS_4_SCRATCH 0x0020
411#define BIOS_5_SCRATCH 0x0024
412#define BIOS_6_SCRATCH 0x0028
413#define BIOS_7_SCRATCH 0x002c
414
415#define HDP_SOFT_RESET (1 << 26)
416
417#define TV_DAC_CNTL 0x088c
418#define GPIOPAD_MASK 0x0198
419#define GPIOPAD_A 0x019c
420#define GPIOPAD_EN 0x01a0
421#define GPIOPAD_Y 0x01a4
422#define ZV_LCDPAD_MASK 0x01a8
423#define ZV_LCDPAD_A 0x01ac
424#define ZV_LCDPAD_EN 0x01b0
425#define ZV_LCDPAD_Y 0x01b4
426
427/* PLL Registers */
428#define CLK_PIN_CNTL 0x0001
429#define PPLL_CNTL 0x0002
430#define PPLL_REF_DIV 0x0003
431#define PPLL_DIV_0 0x0004
432#define PPLL_DIV_1 0x0005
433#define PPLL_DIV_2 0x0006
434#define PPLL_DIV_3 0x0007
435#define VCLK_ECP_CNTL 0x0008
436#define HTOTAL_CNTL 0x0009
437#define M_SPLL_REF_FB_DIV 0x000a
438#define AGP_PLL_CNTL 0x000b
439#define SPLL_CNTL 0x000c
440#define SCLK_CNTL 0x000d
441#define MPLL_CNTL 0x000e
442#define MDLL_CKO 0x000f
443#define MDLL_RDCKA 0x0010
444#define MCLK_CNTL 0x0012
445#define AGP_PLL_CNTL 0x000b
446#define PLL_TEST_CNTL 0x0013
447#define CLK_PWRMGT_CNTL 0x0014
448#define PLL_PWRMGT_CNTL 0x0015
449#define MCLK_MISC 0x001f
450#define P2PLL_CNTL 0x002a
451#define P2PLL_REF_DIV 0x002b
452#define PIXCLKS_CNTL 0x002d
453#define SCLK_MORE_CNTL 0x0035
454
455/* MCLK_CNTL bit constants */
456#define FORCEON_MCLKA (1 << 16)
457#define FORCEON_MCLKB (1 << 17)
458#define FORCEON_YCLKA (1 << 18)
459#define FORCEON_YCLKB (1 << 19)
460#define FORCEON_MC (1 << 20)
461#define FORCEON_AIC (1 << 21)
462
463/* SCLK_CNTL bit constants */
464#define DYN_STOP_LAT_MASK 0x00007ff8
465#define CP_MAX_DYN_STOP_LAT 0x0008
466#define SCLK_FORCEON_MASK 0xffff8000
467
468/* SCLK_MORE_CNTL bit constants */
469#define SCLK_MORE_FORCEON 0x0700
470
471/* BUS_CNTL bit constants */
472#define BUS_DBL_RESYNC 0x00000001
473#define BUS_MSTR_RESET 0x00000002
474#define BUS_FLUSH_BUF 0x00000004
475#define BUS_STOP_REQ_DIS 0x00000008
476#define BUS_ROTATION_DIS 0x00000010
477#define BUS_MASTER_DIS 0x00000040
478#define BUS_ROM_WRT_EN 0x00000080
479#define BUS_DIS_ROM 0x00001000
480#define BUS_PCI_READ_RETRY_EN 0x00002000
481#define BUS_AGP_AD_STEPPING_EN 0x00004000
482#define BUS_PCI_WRT_RETRY_EN 0x00008000
483#define BUS_MSTR_RD_MULT 0x00100000
484#define BUS_MSTR_RD_LINE 0x00200000
485#define BUS_SUSPEND 0x00400000
486#define LAT_16X 0x00800000
487#define BUS_RD_DISCARD_EN 0x01000000
488#define BUS_RD_ABORT_EN 0x02000000
489#define BUS_MSTR_WS 0x04000000
490#define BUS_PARKING_DIS 0x08000000
491#define BUS_MSTR_DISCONNECT_EN 0x10000000
492#define BUS_WRT_BURST 0x20000000
493#define BUS_READ_BURST 0x40000000
494#define BUS_RDY_READ_DLY 0x80000000
495
496/* PIXCLKS_CNTL */
497#define PIX2CLK_SRC_SEL_MASK 0x03
498#define PIX2CLK_SRC_SEL_CPUCLK 0x00
499#define PIX2CLK_SRC_SEL_PSCANCLK 0x01
500#define PIX2CLK_SRC_SEL_BYTECLK 0x02
501#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
502#define PIX2CLK_ALWAYS_ONb (1<<6)
503#define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
504#define PIXCLK_TV_SRC_SEL (1 << 8)
505#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
506#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
507
508
509/* CLOCK_CNTL_INDEX bit constants */
510#define PLL_WR_EN 0x00000080
511
512/* CONFIG_CNTL bit constants */
513#define CFG_VGA_RAM_EN 0x00000100
514#define CFG_ATI_REV_ID_MASK (0xf << 16)
515#define CFG_ATI_REV_A11 (0 << 16)
516#define CFG_ATI_REV_A12 (1 << 16)
517#define CFG_ATI_REV_A13 (2 << 16)
518
519/* CRTC_EXT_CNTL bit constants */
520#define VGA_ATI_LINEAR 0x00000008
521#define VGA_128KAP_PAGING 0x00000010
522#define XCRT_CNT_EN (1 << 6)
523#define CRTC_HSYNC_DIS (1 << 8)
524#define CRTC_VSYNC_DIS (1 << 9)
525#define CRTC_DISPLAY_DIS (1 << 10)
526#define CRTC_CRT_ON (1 << 15)
527
528
529/* DSTCACHE_CTLSTAT bit constants */
530#define RB2D_DC_FLUSH (3 << 0)
531#define RB2D_DC_FLUSH_ALL 0xf
532#define RB2D_DC_BUSY (1 << 31)
533
534
535/* CRTC_GEN_CNTL bit constants */
536#define CRTC_DBL_SCAN_EN 0x00000001
537#define CRTC_CUR_EN 0x00010000
538#define CRTC_INTERLACE_EN (1 << 1)
539#define CRTC_BYPASS_LUT_EN (1 << 14)
540#define CRTC_EXT_DISP_EN (1 << 24)
541#define CRTC_EN (1 << 25)
542#define CRTC_DISP_REQ_EN_B (1 << 26)
543
544/* CRTC_STATUS bit constants */
545#define CRTC_VBLANK 0x00000001
546
547/* CRTC2_GEN_CNTL bit constants */
548#define CRT2_ON (1 << 7)
549#define CRTC2_DISPLAY_DIS (1 << 23)
550#define CRTC2_EN (1 << 25)
551#define CRTC2_DISP_REQ_EN_B (1 << 26)
552
553/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
554#define CUR_LOCK 0x80000000
555
556/* GPIO bit constants */
557#define GPIO_A_0 (1 << 0)
558#define GPIO_A_1 (1 << 1)
559#define GPIO_Y_0 (1 << 8)
560#define GPIO_Y_1 (1 << 9)
561#define GPIO_EN_0 (1 << 16)
562#define GPIO_EN_1 (1 << 17)
563#define GPIO_MASK_0 (1 << 24)
564#define GPIO_MASK_1 (1 << 25)
565#define VGA_DDC_DATA_OUTPUT GPIO_A_0
566#define VGA_DDC_CLK_OUTPUT GPIO_A_1
567#define VGA_DDC_DATA_INPUT GPIO_Y_0
568#define VGA_DDC_CLK_INPUT GPIO_Y_1
569#define VGA_DDC_DATA_OUT_EN GPIO_EN_0
570#define VGA_DDC_CLK_OUT_EN GPIO_EN_1
571
572
573/* FP bit constants */
574#define FP_CRTC_H_TOTAL_MASK 0x000003ff
575#define FP_CRTC_H_DISP_MASK 0x01ff0000
576#define FP_CRTC_V_TOTAL_MASK 0x00000fff
577#define FP_CRTC_V_DISP_MASK 0x0fff0000
578#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
579#define FP_H_SYNC_WID_MASK 0x003f0000
580#define FP_V_SYNC_STRT_MASK 0x00000fff
581#define FP_V_SYNC_WID_MASK 0x001f0000
582#define FP_CRTC_H_TOTAL_SHIFT 0x00000000
583#define FP_CRTC_H_DISP_SHIFT 0x00000010
584#define FP_CRTC_V_TOTAL_SHIFT 0x00000000
585#define FP_CRTC_V_DISP_SHIFT 0x00000010
586#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
587#define FP_H_SYNC_WID_SHIFT 0x00000010
588#define FP_V_SYNC_STRT_SHIFT 0x00000000
589#define FP_V_SYNC_WID_SHIFT 0x00000010
590
591/* FP_GEN_CNTL bit constants */
592#define FP_FPON (1 << 0)
593#define FP_TMDS_EN (1 << 2)
594#define FP_PANEL_FORMAT (1 << 3)
595#define FP_EN_TMDS (1 << 7)
596#define FP_DETECT_SENSE (1 << 8)
597#define R200_FP_SOURCE_SEL_MASK (3 << 10)
598#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
599#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
600#define R200_FP_SOURCE_SEL_RMX (2 << 10)
601#define R200_FP_SOURCE_SEL_TRANS (3 << 10)
602#define FP_SEL_CRTC1 (0 << 13)
603#define FP_SEL_CRTC2 (1 << 13)
604#define FP_USE_VGA_HSYNC (1 << 14)
605#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
606#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
607#define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
608#define FP_CRTC_USE_SHADOW_VEND (1 << 18)
609#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
610#define FP_DFP_SYNC_SEL (1 << 21)
611#define FP_CRTC_LOCK_8DOT (1 << 22)
612#define FP_CRT_SYNC_SEL (1 << 23)
613#define FP_USE_SHADOW_EN (1 << 24)
614#define FP_CRT_SYNC_ALT (1 << 26)
615
616/* FP2_GEN_CNTL bit constants */
617#define FP2_BLANK_EN (1 << 1)
618#define FP2_ON (1 << 2)
619#define FP2_PANEL_FORMAT (1 << 3)
620#define FP2_SOURCE_SEL_MASK (3 << 10)
621#define FP2_SOURCE_SEL_CRTC2 (1 << 10)
622#define FP2_SRC_SEL_MASK (3 << 13)
623#define FP2_SRC_SEL_CRTC2 (1 << 13)
624#define FP2_FP_POL (1 << 16)
625#define FP2_LP_POL (1 << 17)
626#define FP2_SCK_POL (1 << 18)
627#define FP2_LCD_CNTL_MASK (7 << 19)
628#define FP2_PAD_FLOP_EN (1 << 22)
629#define FP2_CRC_EN (1 << 23)
630#define FP2_CRC_READ_EN (1 << 24)
631#define FP2_DV0_EN (1 << 25)
632#define FP2_DV0_RATE_SEL_SDR (1 << 26)
633
634
635/* LVDS_GEN_CNTL bit constants */
636#define LVDS_ON (1 << 0)
637#define LVDS_DISPLAY_DIS (1 << 1)
638#define LVDS_PANEL_TYPE (1 << 2)
639#define LVDS_PANEL_FORMAT (1 << 3)
640#define LVDS_EN (1 << 7)
641#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
642#define LVDS_BL_MOD_LEVEL_SHIFT 8
643#define LVDS_BL_MOD_EN (1 << 16)
644#define LVDS_DIGON (1 << 18)
645#define LVDS_BLON (1 << 19)
646#define LVDS_SEL_CRTC2 (1 << 23)
647#define LVDS_STATE_MASK \
648 (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
649
650/* LVDS_PLL_CNTL bit constatns */
651#define HSYNC_DELAY_SHIFT 0x1c
652#define HSYNC_DELAY_MASK (0xf << 0x1c)
653
654/* TMDS_TRANSMITTER_CNTL bit constants */
655#define TMDS_PLL_EN (1 << 0)
656#define TMDS_PLLRST (1 << 1)
657#define TMDS_RAN_PAT_RST (1 << 7)
658#define TMDS_ICHCSEL (1 << 28)
659
660/* FP_HORZ_STRETCH bit constants */
661#define HORZ_STRETCH_RATIO_MASK 0xffff
662#define HORZ_STRETCH_RATIO_MAX 4096
663#define HORZ_PANEL_SIZE (0x1ff << 16)
664#define HORZ_PANEL_SHIFT 16
665#define HORZ_STRETCH_PIXREP (0 << 25)
666#define HORZ_STRETCH_BLEND (1 << 26)
667#define HORZ_STRETCH_ENABLE (1 << 25)
668#define HORZ_AUTO_RATIO (1 << 27)
669#define HORZ_FP_LOOP_STRETCH (0x7 << 28)
670#define HORZ_AUTO_RATIO_INC (1 << 31)
671
672
673/* FP_VERT_STRETCH bit constants */
674#define VERT_STRETCH_RATIO_MASK 0xfff
675#define VERT_STRETCH_RATIO_MAX 4096
676#define VERT_PANEL_SIZE (0xfff << 12)
677#define VERT_PANEL_SHIFT 12
678#define VERT_STRETCH_LINREP (0 << 26)
679#define VERT_STRETCH_BLEND (1 << 26)
680#define VERT_STRETCH_ENABLE (1 << 25)
681#define VERT_AUTO_RATIO_EN (1 << 27)
682#define VERT_FP_LOOP_STRETCH (0x7 << 28)
683#define VERT_STRETCH_RESERVED 0xf1000000
684
685/* DAC_CNTL bit constants */
686#define DAC_8BIT_EN 0x00000100
687#define DAC_4BPP_PIX_ORDER 0x00000200
688#define DAC_CRC_EN 0x00080000
689#define DAC_MASK_ALL (0xff << 24)
690#define DAC_PDWN (1 << 15)
691#define DAC_EXPAND_MODE (1 << 14)
692#define DAC_VGA_ADR_EN (1 << 13)
693#define DAC_RANGE_CNTL (3 << 0)
694#define DAC_RANGE_CNTL_MASK 0x03
695#define DAC_BLANKING (1 << 2)
696#define DAC_CMP_EN (1 << 3)
697#define DAC_CMP_OUTPUT (1 << 7)
698
699/* DAC_CNTL2 bit constants */
700#define DAC2_EXPAND_MODE (1 << 14)
701#define DAC2_CMP_EN (1 << 7)
702#define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
703
704/* DAC_EXT_CNTL bit constants */
705#define DAC_FORCE_BLANK_OFF_EN (1 << 4)
706#define DAC_FORCE_DATA_EN (1 << 5)
707#define DAC_FORCE_DATA_SEL_MASK (3 << 6)
708#define DAC_FORCE_DATA_MASK 0x0003ff00
709#define DAC_FORCE_DATA_SHIFT 8
710
711/* GEN_RESET_CNTL bit constants */
712#define SOFT_RESET_GUI 0x00000001
713#define SOFT_RESET_VCLK 0x00000100
714#define SOFT_RESET_PCLK 0x00000200
715#define SOFT_RESET_ECP 0x00000400
716#define SOFT_RESET_DISPENG_XCLK 0x00000800
717
718/* MEM_CNTL bit constants */
719#define MEM_CTLR_STATUS_IDLE 0x00000000
720#define MEM_CTLR_STATUS_BUSY 0x00100000
721#define MEM_SEQNCR_STATUS_IDLE 0x00000000
722#define MEM_SEQNCR_STATUS_BUSY 0x00200000
723#define MEM_ARBITER_STATUS_IDLE 0x00000000
724#define MEM_ARBITER_STATUS_BUSY 0x00400000
725#define MEM_REQ_UNLOCK 0x00000000
726#define MEM_REQ_LOCK 0x00800000
727#define MEM_NUM_CHANNELS_MASK 0x00000001
728#define MEM_USE_B_CH_ONLY 0x00000002
729#define RV100_MEM_HALF_MODE 0x00000008
730#define R300_MEM_NUM_CHANNELS_MASK 0x00000003
731#define R300_MEM_USE_CD_CH_ONLY 0x00000004
732
733
734/* RBBM_SOFT_RESET bit constants */
735#define SOFT_RESET_CP (1 << 0)
736#define SOFT_RESET_HI (1 << 1)
737#define SOFT_RESET_SE (1 << 2)
738#define SOFT_RESET_RE (1 << 3)
739#define SOFT_RESET_PP (1 << 4)
740#define SOFT_RESET_E2 (1 << 5)
741#define SOFT_RESET_RB (1 << 6)
742#define SOFT_RESET_HDP (1 << 7)
743
744/* SURFACE_CNTL bit consants */
745#define SURF_TRANSLATION_DIS (1 << 8)
746#define NONSURF_AP0_SWP_16BPP (1 << 20)
747#define NONSURF_AP0_SWP_32BPP (1 << 21)
748#define NONSURF_AP1_SWP_16BPP (1 << 22)
749#define NONSURF_AP1_SWP_32BPP (1 << 23)
750
751/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
752#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
753#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
754
755/* MM_INDEX bit constants */
756#define MM_APER 0x80000000
757
758/* CLR_CMP_CNTL bit constants */
759#define COMPARE_SRC_FALSE 0x00000000
760#define COMPARE_SRC_TRUE 0x00000001
761#define COMPARE_SRC_NOT_EQUAL 0x00000004
762#define COMPARE_SRC_EQUAL 0x00000005
763#define COMPARE_SRC_EQUAL_FLIP 0x00000007
764#define COMPARE_DST_FALSE 0x00000000
765#define COMPARE_DST_TRUE 0x00000100
766#define COMPARE_DST_NOT_EQUAL 0x00000400
767#define COMPARE_DST_EQUAL 0x00000500
768#define COMPARE_DESTINATION 0x00000000
769#define COMPARE_SOURCE 0x01000000
770#define COMPARE_SRC_AND_DST 0x02000000
771
772
773/* DP_CNTL bit constants */
774#define DST_X_RIGHT_TO_LEFT 0x00000000
775#define DST_X_LEFT_TO_RIGHT 0x00000001
776#define DST_Y_BOTTOM_TO_TOP 0x00000000
777#define DST_Y_TOP_TO_BOTTOM 0x00000002
778#define DST_X_MAJOR 0x00000000
779#define DST_Y_MAJOR 0x00000004
780#define DST_X_TILE 0x00000008
781#define DST_Y_TILE 0x00000010
782#define DST_LAST_PEL 0x00000020
783#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
784#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
785#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
786#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
787#define DST_BRES_SIGN 0x00000100
788#define DST_HOST_BIG_ENDIAN_EN 0x00000200
789#define DST_POLYLINE_NONLAST 0x00008000
790#define DST_RASTER_STALL 0x00010000
791#define DST_POLY_EDGE 0x00040000
792
793
794/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
795#define DST_X_MAJOR_S 0x00000000
796#define DST_Y_MAJOR_S 0x00000001
797#define DST_Y_BOTTOM_TO_TOP_S 0x00000000
798#define DST_Y_TOP_TO_BOTTOM_S 0x00008000
799#define DST_X_RIGHT_TO_LEFT_S 0x00000000
800#define DST_X_LEFT_TO_RIGHT_S 0x80000000
801
802
803/* DP_DATATYPE bit constants */
804#define DST_8BPP 0x00000002
805#define DST_15BPP 0x00000003
806#define DST_16BPP 0x00000004
807#define DST_24BPP 0x00000005
808#define DST_32BPP 0x00000006
809#define DST_8BPP_RGB332 0x00000007
810#define DST_8BPP_Y8 0x00000008
811#define DST_8BPP_RGB8 0x00000009
812#define DST_16BPP_VYUY422 0x0000000b
813#define DST_16BPP_YVYU422 0x0000000c
814#define DST_32BPP_AYUV444 0x0000000e
815#define DST_16BPP_ARGB4444 0x0000000f
816#define BRUSH_SOLIDCOLOR 0x00000d00
817#define SRC_MONO 0x00000000
818#define SRC_MONO_LBKGD 0x00010000
819#define SRC_DSTCOLOR 0x00030000
820#define BYTE_ORDER_MSB_TO_LSB 0x00000000
821#define BYTE_ORDER_LSB_TO_MSB 0x40000000
822#define DP_CONVERSION_TEMP 0x80000000
823#define HOST_BIG_ENDIAN_EN (1 << 29)
824
825
826/* DP_GUI_MASTER_CNTL bit constants */
827#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
828#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
829#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
830#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
831#define GMC_SRC_CLIP_DEFAULT 0x00000000
832#define GMC_SRC_CLIP_LEAVE 0x00000004
833#define GMC_DST_CLIP_DEFAULT 0x00000000
834#define GMC_DST_CLIP_LEAVE 0x00000008
835#define GMC_BRUSH_8x8MONO 0x00000000
836#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
837#define GMC_BRUSH_8x1MONO 0x00000020
838#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
839#define GMC_BRUSH_1x8MONO 0x00000040
840#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
841#define GMC_BRUSH_32x1MONO 0x00000060
842#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
843#define GMC_BRUSH_32x32MONO 0x00000080
844#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
845#define GMC_BRUSH_8x8COLOR 0x000000a0
846#define GMC_BRUSH_8x1COLOR 0x000000b0
847#define GMC_BRUSH_1x8COLOR 0x000000c0
848#define GMC_BRUSH_SOLID_COLOR 0x000000d0
849#define GMC_DST_8BPP 0x00000200
850#define GMC_DST_15BPP 0x00000300
851#define GMC_DST_16BPP 0x00000400
852#define GMC_DST_24BPP 0x00000500
853#define GMC_DST_32BPP 0x00000600
854#define GMC_DST_8BPP_RGB332 0x00000700
855#define GMC_DST_8BPP_Y8 0x00000800
856#define GMC_DST_8BPP_RGB8 0x00000900
857#define GMC_DST_16BPP_VYUY422 0x00000b00
858#define GMC_DST_16BPP_YVYU422 0x00000c00
859#define GMC_DST_32BPP_AYUV444 0x00000e00
860#define GMC_DST_16BPP_ARGB4444 0x00000f00
861#define GMC_SRC_MONO 0x00000000
862#define GMC_SRC_MONO_LBKGD 0x00001000
863#define GMC_SRC_DSTCOLOR 0x00003000
864#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
865#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
866#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
867#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
868#define GMC_DP_SRC_RECT 0x02000000
869#define GMC_DP_SRC_HOST 0x03000000
870#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
871#define GMC_3D_FCN_EN_CLR 0x00000000
872#define GMC_3D_FCN_EN_SET 0x08000000
873#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
874#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
875#define GMC_AUX_CLIP_LEAVE 0x00000000
876#define GMC_AUX_CLIP_CLEAR 0x20000000
877#define GMC_WRITE_MASK_LEAVE 0x00000000
878#define GMC_WRITE_MASK_SET 0x40000000
879#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
880#define GMC_SRC_DATATYPE_COLOR (3 << 12)
881#define ROP3_S 0x00cc0000
882#define ROP3_SRCCOPY 0x00cc0000
883#define ROP3_P 0x00f00000
884#define ROP3_PATCOPY 0x00f00000
885#define DP_SRC_SOURCE_MASK (7 << 24)
886#define GMC_BRUSH_NONE (15 << 4)
887#define DP_SRC_SOURCE_MEMORY (2 << 24)
888#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
889
890/* DP_MIX bit constants */
891#define DP_SRC_RECT 0x00000200
892#define DP_SRC_HOST 0x00000300
893#define DP_SRC_HOST_BYTEALIGN 0x00000400
894
895/* MPLL_CNTL bit constants */
896#define MPLL_RESET 0x00000001
897
898/* MDLL_CKO bit constants */
899#define MCKOA_SLEEP 0x00000001
900#define MCKOA_RESET 0x00000002
901#define MCKOA_REF_SKEW_MASK 0x00000700
902#define MCKOA_FB_SKEW_MASK 0x00007000
903
904/* MDLL_RDCKA bit constants */
905#define MRDCKA0_SLEEP 0x00000001
906#define MRDCKA0_RESET 0x00000002
907#define MRDCKA1_SLEEP 0x00010000
908#define MRDCKA1_RESET 0x00020000
909
910/* VCLK_ECP_CNTL constants */
911#define VCLK_SRC_SEL_MASK 0x03
912#define VCLK_SRC_SEL_CPUCLK 0x00
913#define VCLK_SRC_SEL_PSCANCLK 0x01
914#define VCLK_SRC_SEL_BYTECLK 0x02
915#define VCLK_SRC_SEL_PPLLCLK 0x03
916#define PIXCLK_ALWAYS_ONb 0x00000040
917#define PIXCLK_DAC_ALWAYS_ONb 0x00000080
918
919/* BUS_CNTL1 constants */
920#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
921#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
922#define BUS_CNTL1_AGPCLK_VALID 0x80000000
923
924/* PLL_PWRMGT_CNTL constants */
925#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
926#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
927#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
928#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
929#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
930#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
931#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
932
933/* TV_DAC_CNTL constants */
934#define TV_DAC_CNTL_BGSLEEP 0x00000040
935#define TV_DAC_CNTL_DETECT 0x00000010
936#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
937#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
938#define TV_DAC_CNTL_BGADJ__SHIFT 16
939#define TV_DAC_CNTL_DACADJ__SHIFT 20
940#define TV_DAC_CNTL_RDACPD 0x01000000
941#define TV_DAC_CNTL_GDACPD 0x02000000
942#define TV_DAC_CNTL_BDACPD 0x04000000
943
944/* DISP_MISC_CNTL constants */
945#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
946#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
947#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
948#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
949#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
950#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
951#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
952#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
953#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
954#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
955#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
956#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
957
958/* DISP_PWR_MAN constants */
959#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
960#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
961#define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
962#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
963#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
964#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
965#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
966#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
967#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
968#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
969#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
970#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
971#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
972
973/* masks */
974
975#define CONFIG_MEMSIZE_MASK 0x1f000000
976#define MEM_CFG_TYPE 0x40000000
977#define DST_OFFSET_MASK 0x003fffff
978#define DST_PITCH_MASK 0x3fc00000
979#define DEFAULT_TILE_MASK 0xc0000000
980#define PPLL_DIV_SEL_MASK 0x00000300
981#define PPLL_RESET 0x00000001
982#define PPLL_SLEEP 0x00000002
983#define PPLL_ATOMIC_UPDATE_EN 0x00010000
984#define PPLL_REF_DIV_MASK 0x000003ff
985#define PPLL_FB3_DIV_MASK 0x000007ff
986#define PPLL_POST3_DIV_MASK 0x00070000
987#define PPLL_ATOMIC_UPDATE_R 0x00008000
988#define PPLL_ATOMIC_UPDATE_W 0x00008000
989#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
990#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
991#define R300_PPLL_REF_DIV_ACC_SHIFT 18
992
993#define GUI_ACTIVE 0x80000000
994
995
996#define MC_IND_INDEX 0x01F8
997#define MC_IND_DATA 0x01FC
998
999/* PAD_CTLR_STRENGTH */
1000#define PAD_MANUAL_OVERRIDE 0x80000000
1001
1002// pllCLK_PIN_CNTL
1003#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
1004#define CLK_PIN_CNTL__OSC_EN 0x00000001L
1005#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
1006#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
1007#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
1008#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
1009#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
1010#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
1011#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
1012#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
1013#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
1014#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
1015#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
1016#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
1017#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
1018#define CLK_PIN_CNTL__CG_SPARE 0x00004000L
1019#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
1020#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
1021#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
1022#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
1023#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
1024#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
1025#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
1026#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
1027
1028// pllCLK_PWRMGT_CNTL
1029#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
1030#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
1031#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
1032#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
1033#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
1034#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
1035#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
1036#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
1037#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
1038#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
1039#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
1040#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
1041#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
1042#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
1043#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
1044#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
1045#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
1046#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
1047#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
1048#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
1049#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
1050#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
1051#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
1052
1053// pllP2PLL_CNTL
1054#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
1055#define P2PLL_CNTL__P2PLL_RESET 0x00000001L
1056#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
1057#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
1058#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
1059#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
1060#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
1061#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
1062#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
1063#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
1064#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
1065#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
1066#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
1067#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
1068#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
1069#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
1070#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
1071#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
1072#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
1073#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
1074#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
1075#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
1076#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
1077
1078// pllPIXCLKS_CNTL
1079#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
1080#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
1081#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
1082#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
1083#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
1084#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
1085#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
1086#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
1087#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
1088#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
1089#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
1090
1091
1092// pllPIXCLKS_CNTL
1093#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
1094#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
1095#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
1096#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
1097#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
1098#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
1099#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
1100#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
1101#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
1102#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
1103#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
1104#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1105#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
1106#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
1107#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
1108#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
1109#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
1110#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
1111#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1112
1113
1114// pllP2PLL_DIV_0
1115#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
1116#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
1117#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
1118#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
1119#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
1120#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
1121
1122// pllSCLK_CNTL
1123#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
1124#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
1125#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
1126#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
1127#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
1128#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
1129#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
1130#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
1131#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
1132#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
1133#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
1134#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
1135#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
1136#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
1137#define SCLK_CNTL__FORCE_DISP2 0x00008000L
1138#define SCLK_CNTL__FORCE_CP 0x00010000L
1139#define SCLK_CNTL__FORCE_HDP 0x00020000L
1140#define SCLK_CNTL__FORCE_DISP1 0x00040000L
1141#define SCLK_CNTL__FORCE_TOP 0x00080000L
1142#define SCLK_CNTL__FORCE_E2 0x00100000L
1143#define SCLK_CNTL__FORCE_SE 0x00200000L
1144#define SCLK_CNTL__FORCE_IDCT 0x00400000L
1145#define SCLK_CNTL__FORCE_VIP 0x00800000L
1146#define SCLK_CNTL__FORCE_RE 0x01000000L
1147#define SCLK_CNTL__FORCE_PB 0x02000000L
1148#define SCLK_CNTL__FORCE_TAM 0x04000000L
1149#define SCLK_CNTL__FORCE_TDM 0x08000000L
1150#define SCLK_CNTL__FORCE_RB 0x10000000L
1151#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
1152#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
1153#define SCLK_CNTL__FORCE_OV0 0x80000000L
1154#define SCLK_CNTL__R300_FORCE_VAP (1<<21)
1155#define SCLK_CNTL__R300_FORCE_SR (1<<25)
1156#define SCLK_CNTL__R300_FORCE_PX (1<<26)
1157#define SCLK_CNTL__R300_FORCE_TX (1<<27)
1158#define SCLK_CNTL__R300_FORCE_US (1<<28)
1159#define SCLK_CNTL__R300_FORCE_SU (1<<30)
1160#define SCLK_CNTL__FORCEON_MASK 0xffff8000L
1161
1162// pllSCLK_CNTL2
1163#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
1164#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
1165#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
1166#define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
1167#define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
1168#define SCLK_CNTL2__R300_FORCE_GA (1<<15)
1169
1170// SCLK_MORE_CNTL
1171#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
1172#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
1173#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
1174#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
1175#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
1176#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
1177#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
1178#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
1179#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
1180#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
1181#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
1182#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
1183#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
1184#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
1185#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
1186#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
1187#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
1188#define SCLK_MORE_CNTL__FORCEON 0x00000700L
1189
1190// MCLK_CNTL
1191#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
1192#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
1193#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
1194#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
1195#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
1196#define MCLK_CNTL__FORCE_MCLKA 0x00010000L
1197#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
1198#define MCLK_CNTL__FORCE_MCLKB 0x00020000L
1199#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
1200#define MCLK_CNTL__FORCE_YCLKA 0x00040000L
1201#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
1202#define MCLK_CNTL__FORCE_YCLKB 0x00080000L
1203#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
1204#define MCLK_CNTL__FORCE_MC 0x00100000L
1205#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
1206#define MCLK_CNTL__FORCE_AIC 0x00200000L
1207#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
1208#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
1209#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
1210#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
1211#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
1212#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
1213
1214// MCLK_MISC
1215#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
1216#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
1217#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
1218#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
1219#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
1220#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
1221#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
1222#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
1223#define MCLK_MISC__DLL_READY_LAT 0x00000100L
1224#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
1225#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
1226#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
1227#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
1228#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
1229#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
1230#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
1231#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
1232#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
1233#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
1234#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
1235#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
1236#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
1237#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
1238#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
1239#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
1240#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
1241#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
1242#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
1243
1244// VCLK_ECP_CNTL
1245#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
1246#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
1247#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
1248#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
1249#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
1250#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
1251#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
1252#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
1253#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1254
1255// PLL_PWRMGT_CNTL
1256#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
1257#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
1258#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
1259#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
1260#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
1261#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
1262#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
1263#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
1264#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
1265#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
1266#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
1267#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
1268#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
1269#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
1270#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
1271#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
1272#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
1273#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
1274#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
1275#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
1276#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
1277#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
1278#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
1279#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
1280#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
1281#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
1282#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
1283#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
1284#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
1285#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
1286#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
1287#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
1288
1289// CLK_PWRMGT_CNTL
1290#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
1291#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
1292#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
1293#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
1294#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
1295#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
1296#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
1297#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
1298#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
1299#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
1300#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
1301#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
1302#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
1303#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
1304#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
1305#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
1306#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
1307#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
1308#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
1309#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
1310#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
1311#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
1312#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
1313#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
1314#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
1315#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
1316#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
1317#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
1318#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
1319#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
1320#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
1321#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
1322#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
1323#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
1324#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
1325#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
1326#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
1327#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
1328#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
1329#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
1330#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
1331#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
1332#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
1333
1334// BUS_CNTL1
1335#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
1336#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
1337#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
1338#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
1339#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
1340#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
1341#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
1342#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
1343#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
1344#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
1345#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
1346#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
1347#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
1348#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
1349#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
1350#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
1351#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
1352#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
1353#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
1354#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
1355#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
1356#define BUS_CNTL1__AGPCLK_VALID 0x80000000L
1357
1358// BUS_CNTL1
1359#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
1360#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
1361#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
1362#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
1363#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
1364#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
1365#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
1366#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
1367#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
1368#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
1369#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
1370#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
1371
1372// CRTC_OFFSET_CNTL
1373#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
1374#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
1375#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
1376#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
1377#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
1378#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
1379#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
1380#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
1381#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
1382#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
1383#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
1384#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
1385#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
1386#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
1387#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
1388#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
1389#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
1390#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
1391#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
1392#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
1393#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
1394#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
1395#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
1396
1397// CRTC_GEN_CNTL
1398#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
1399#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
1400#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
1401#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
1402#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
1403#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
1404#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
1405#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
1406#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
1407#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
1408#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
1409#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
1410#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
1411#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
1412#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
1413#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
1414#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
1415#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
1416#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
1417
1418// CRTC2_GEN_CNTL
1419#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
1420#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
1421#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
1422#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
1423#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
1424#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
1425#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
1426#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
1427#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
1428#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
1429#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
1430#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
1431#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
1432#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
1433#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
1434#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
1435#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
1436#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
1437#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
1438#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
1439#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
1440#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
1441#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
1442#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
1443#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
1444#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
1445#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
1446#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
1447#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
1448#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
1449
1450// AGP_CNTL
1451#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
1452#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
1453#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
1454#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
1455#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
1456#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
1457#define AGP_CNTL__EN_2X_STBB 0x00000400L
1458#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
1459#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
1460#define AGP_CNTL__SBA_DIS_MASK 0x00001000L
1461#define AGP_CNTL__SBA_DIS 0x00001000L
1462#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
1463#define AGP_CNTL__AGP_REV_ID 0x00002000L
1464#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
1465#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
1466#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
1467#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
1468#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
1469#define AGP_CNTL__FORCE_INT_VREF 0x00010000L
1470#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
1471#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
1472#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
1473#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
1474#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
1475#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
1476#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
1477#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
1478#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
1479#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
1480#define AGP_CNTL__EN_RBFCALM 0x00800000L
1481#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
1482#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
1483#define AGP_CNTL__DIS_RBF_MASK 0x02000000L
1484#define AGP_CNTL__DIS_RBF 0x02000000L
1485#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
1486#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
1487#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
1488#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
1489
1490// AGP_CNTL
1491#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
1492#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
1493#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
1494#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
1495#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
1496#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
1497#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
1498#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
1499#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
1500#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
1501#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
1502#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
1503#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
1504#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
1505#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
1506#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
1507#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
1508#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
1509#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
1510#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
1511#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
1512
1513// DISP_MISC_CNTL
1514#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
1515#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
1516#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
1517#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
1518#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
1519#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
1520#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
1521#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
1522#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
1523#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
1524#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
1525#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
1526#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
1527#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
1528#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
1529#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
1530#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
1531#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
1532#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
1533#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
1534#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
1535#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
1536#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
1537#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
1538#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
1539#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
1540#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
1541#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
1542#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
1543#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
1544
1545// DISP_PWR_MAN
1546#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
1547#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
1548#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
1549#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
1550#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
1551#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
1552#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
1553#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
1554#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
1555#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
1556#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
1557#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
1558#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
1559#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
1560#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
1561#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
1562#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
1563#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
1564#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
1565#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
1566#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
1567#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
1568#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
1569#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
1570#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
1571#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
1572#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
1573
1574// MC_IND_INDEX
1575#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
1576#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
1577#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
1578
1579// MC_IND_DATA
1580#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
1581
1582// MC_CHP_IO_CNTL_A1
1583#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
1584#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
1585#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
1586#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
1587#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
1588#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
1589#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
1590#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
1591#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
1592#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
1593#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
1594#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
1595#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
1596#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
1597#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
1598#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
1599#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
1600#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
1601#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
1602#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
1603#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
1604#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
1605#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
1606
1607// MC_CHP_IO_CNTL_B1
1608#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
1609#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
1610#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
1611#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
1612#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
1613#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
1614#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
1615#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
1616#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
1617#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
1618#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
1619#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
1620#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
1621#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
1622#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
1623#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
1624#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
1625#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
1626#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
1627#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
1628#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
1629#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
1630#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
1631
1632// MC_CHP_IO_CNTL_A1
1633#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
1634#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
1635#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
1636#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
1637#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
1638#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
1639#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
1640#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
1641#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
1642#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
1643#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
1644#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
1645#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
1646#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
1647#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
1648#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
1649#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
1650#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
1651#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
1652#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
1653#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
1654#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
1655#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
1656#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
1657#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
1658#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
1659#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
1660#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
1661#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
1662#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
1663#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
1664#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
1665#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
1666#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
1667#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
1668#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
1669#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
1670#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
1671#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
1672
1673// MC_CHP_IO_CNTL_B1
1674#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
1675#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
1676#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
1677#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
1678#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
1679#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
1680#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
1681#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
1682#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
1683#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
1684#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
1685#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
1686#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
1687#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
1688#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
1689#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
1690#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
1691#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
1692#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
1693#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
1694#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
1695#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
1696#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
1697#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
1698#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
1699#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
1700#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
1701#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
1702#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
1703#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
1704#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
1705#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
1706#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
1707#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
1708#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
1709#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
1710#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
1711#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
1712#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
1713
1714// MEM_SDRAM_MODE_REG
1715#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
1716#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
1717#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
1718#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
1719#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
1720#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
1721#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
1722#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
1723#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
1724#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
1725#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
1726#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
1727#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
1728#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
1729#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
1730#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
1731#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
1732#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
1733#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
1734#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
1735#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
1736
1737// MEM_SDRAM_MODE_REG
1738#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
1739#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
1740#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
1741#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
1742#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
1743#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
1744#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
1745#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
1746#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
1747#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
1748#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
1749#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
1750
1751// MEM_REFRESH_CNTL
1752#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
1753#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
1754#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
1755#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
1756#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
1757#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
1758#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
1759#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
1760#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
1761#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
1762#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
1763#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
1764#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
1765#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
1766#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
1767#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
1768#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
1769#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
1770#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
1771#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
1772#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
1773#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
1774#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
1775#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
1776#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
1777#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
1778#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
1779#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
1780
1781// MC_STATUS
1782#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
1783#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
1784#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
1785#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
1786#define MC_STATUS__MC_IDLE_MASK 0x00000004L
1787#define MC_STATUS__MC_IDLE 0x00000004L
1788#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
1789#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
1790#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
1791#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
1792#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
1793#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
1794#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
1795#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
1796#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
1797#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
1798
1799// MDLL_CKO
1800#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
1801#define MDLL_CKO__MCKOA_SLEEP 0x00000001L
1802#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
1803#define MDLL_CKO__MCKOA_RESET 0x00000002L
1804#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
1805#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
1806#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
1807#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
1808#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
1809#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
1810#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
1811#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
1812#define MDLL_CKO__MCKOB_SLEEP 0x00010000L
1813#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
1814#define MDLL_CKO__MCKOB_RESET 0x00020000L
1815#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
1816#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
1817#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
1818#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
1819#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
1820#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
1821#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
1822
1823// MDLL_RDCKA
1824#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
1825#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
1826#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
1827#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
1828#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
1829#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
1830#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
1831#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
1832#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
1833#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
1834#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
1835#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
1836#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
1837#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
1838#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
1839#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
1840#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
1841#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
1842#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
1843#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
1844#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
1845#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
1846#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
1847#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
1848#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
1849#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
1850
1851// MDLL_RDCKB
1852#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
1853#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
1854#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
1855#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
1856#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
1857#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
1858#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
1859#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
1860#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
1861#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
1862#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
1863#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
1864#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
1865#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
1866#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
1867#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
1868#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
1869#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
1870#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
1871#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
1872#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
1873#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
1874#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
1875#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
1876#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
1877#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
1878
1879#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
1880#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
1881#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
1882#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
1883#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
1884#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
1885#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
1886#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
1887
1888#define pllCLK_PIN_CNTL 0x0001
1889#define pllPPLL_CNTL 0x0002
1890#define pllPPLL_REF_DIV 0x0003
1891#define pllPPLL_DIV_0 0x0004
1892#define pllPPLL_DIV_1 0x0005
1893#define pllPPLL_DIV_2 0x0006
1894#define pllPPLL_DIV_3 0x0007
1895#define pllVCLK_ECP_CNTL 0x0008
1896#define pllHTOTAL_CNTL 0x0009
1897#define pllM_SPLL_REF_FB_DIV 0x000A
1898#define pllAGP_PLL_CNTL 0x000B
1899#define pllSPLL_CNTL 0x000C
1900#define pllSCLK_CNTL 0x000D
1901#define pllMPLL_CNTL 0x000E
1902#define pllMDLL_CKO 0x000F
1903#define pllMDLL_RDCKA 0x0010
1904#define pllMDLL_RDCKB 0x0011
1905#define pllMCLK_CNTL 0x0012
1906#define pllPLL_TEST_CNTL 0x0013
1907#define pllCLK_PWRMGT_CNTL 0x0014
1908#define pllPLL_PWRMGT_CNTL 0x0015
1909#define pllCG_TEST_MACRO_RW_WRITE 0x0016
1910#define pllCG_TEST_MACRO_RW_READ 0x0017
1911#define pllCG_TEST_MACRO_RW_DATA 0x0018
1912#define pllCG_TEST_MACRO_RW_CNTL 0x0019
1913#define pllDISP_TEST_MACRO_RW_WRITE 0x001A
1914#define pllDISP_TEST_MACRO_RW_READ 0x001B
1915#define pllDISP_TEST_MACRO_RW_DATA 0x001C
1916#define pllDISP_TEST_MACRO_RW_CNTL 0x001D
1917#define pllSCLK_CNTL2 0x001E
1918#define pllMCLK_MISC 0x001F
1919#define pllTV_PLL_FINE_CNTL 0x0020
1920#define pllTV_PLL_CNTL 0x0021
1921#define pllTV_PLL_CNTL1 0x0022
1922#define pllTV_DTO_INCREMENTS 0x0023
1923#define pllSPLL_AUX_CNTL 0x0024
1924#define pllMPLL_AUX_CNTL 0x0025
1925#define pllP2PLL_CNTL 0x002A
1926#define pllP2PLL_REF_DIV 0x002B
1927#define pllP2PLL_DIV_0 0x002C
1928#define pllPIXCLKS_CNTL 0x002D
1929#define pllHTOTAL2_CNTL 0x002E
1930#define pllSSPLL_CNTL 0x0030
1931#define pllSSPLL_REF_DIV 0x0031
1932#define pllSSPLL_DIV_0 0x0032
1933#define pllSS_INT_CNTL 0x0033
1934#define pllSS_TST_CNTL 0x0034
1935#define pllSCLK_MORE_CNTL 0x0035
1936
1937#define ixMC_PERF_CNTL 0x0000
1938#define ixMC_PERF_SEL 0x0001
1939#define ixMC_PERF_REGION_0 0x0002
1940#define ixMC_PERF_REGION_1 0x0003
1941#define ixMC_PERF_COUNT_0 0x0004
1942#define ixMC_PERF_COUNT_1 0x0005
1943#define ixMC_PERF_COUNT_2 0x0006
1944#define ixMC_PERF_COUNT_3 0x0007
1945#define ixMC_PERF_COUNT_MEMCH_A 0x0008
1946#define ixMC_PERF_COUNT_MEMCH_B 0x0009
1947#define ixMC_IMP_CNTL 0x000A
1948#define ixMC_CHP_IO_CNTL_A0 0x000B
1949#define ixMC_CHP_IO_CNTL_A1 0x000C
1950#define ixMC_CHP_IO_CNTL_B0 0x000D
1951#define ixMC_CHP_IO_CNTL_B1 0x000E
1952#define ixMC_IMP_CNTL_0 0x000F
1953#define ixTC_MISMATCH_1 0x0010
1954#define ixTC_MISMATCH_2 0x0011
1955#define ixMC_BIST_CTRL 0x0012
1956#define ixREG_COLLAR_WRITE 0x0013
1957#define ixREG_COLLAR_READ 0x0014
1958#define ixR300_MC_IMP_CNTL 0x0018
1959#define ixR300_MC_CHP_IO_CNTL_A0 0x0019
1960#define ixR300_MC_CHP_IO_CNTL_A1 0x001a
1961#define ixR300_MC_CHP_IO_CNTL_B0 0x001b
1962#define ixR300_MC_CHP_IO_CNTL_B1 0x001c
1963#define ixR300_MC_CHP_IO_CNTL_C0 0x001d
1964#define ixR300_MC_CHP_IO_CNTL_C1 0x001e
1965#define ixR300_MC_CHP_IO_CNTL_D0 0x001f
1966#define ixR300_MC_CHP_IO_CNTL_D1 0x0020
1967#define ixR300_MC_IMP_CNTL_0 0x0021
1968#define ixR300_MC_ELPIDA_CNTL 0x0022
1969#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
1970#define ixR300_MC_READ_CNTL_CD 0x0024
1971#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
1972#define ixR300_MC_DEBUG_CNTL 0x0026
1973#define ixR300_MC_BIST_CNTL_0 0x0028
1974#define ixR300_MC_BIST_CNTL_1 0x0029
1975#define ixR300_MC_BIST_CNTL_2 0x002a
1976#define ixR300_MC_BIST_CNTL_3 0x002b
1977#define ixR300_MC_BIST_CNTL_4 0x002c
1978#define ixR300_MC_BIST_CNTL_5 0x002d
1979#define ixR300_MC_IMP_STATUS 0x002e
1980#define ixR300_MC_DLL_CNTL 0x002f
1981#define NB_TOM 0x15C
1982
1983
1984#endif /* _RADEON_H */
1985
diff --git a/include/video/s1d13xxxfb.h b/include/video/s1d13xxxfb.h
new file mode 100644
index 000000000000..f06cc88607f5
--- /dev/null
+++ b/include/video/s1d13xxxfb.h
@@ -0,0 +1,166 @@
1/* drivers/video/s1d3xxxfb.h
2 *
3 * (c) 2004 Simtec Electronics
4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 *
6 * Header file for Epson S1D13XXX driver code
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive for
10 * more details.
11 */
12
13#ifndef S1D13XXXFB_H
14#define S1D13XXXFB_H
15
16#define S1D_PALETTE_SIZE 256
17#define S1D_CHIP_REV 7 /* expected chip revision number for s1d13806 */
18#define S1D_FBID "S1D13806"
19#define S1D_DEVICENAME "s1d13806fb"
20
21/* register definitions (tested on s1d13896) */
22#define S1DREG_REV_CODE 0x0000 /* Revision Code Register */
23#define S1DREG_MISC 0x0001 /* Miscellaneous Register */
24#define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
25#define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
26#define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
27#define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
28#define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
29#define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
30#define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */
31#define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */
32#define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */
33#define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */
34#define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */
35#define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */
36#define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */
37#define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */
38#define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */
39#define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */
40#define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */
41#define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */
42#define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */
43#define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
44#define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
45#define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
46#define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */
47#define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */
48#define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
49#define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
50#define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */
51#define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
52#define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
53#define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
54#define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
55#define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
56#define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */
57#define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
58#define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
59#define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */
60#define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
61#define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */
62#define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
63#define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */
64#define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */
65#define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
66#define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */
67#define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */
68#define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */
69#define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
70#define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
71#define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
72#define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
73#define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
74#define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
75#define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */
76#define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */
77#define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */
78#define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */
79#define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
80#define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */
81#define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */
82#define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */
83#define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */
84#define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */
85#define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */
86#define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */
87#define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */
88#define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */
89#define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */
90#define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */
91#define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */
92#define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
93#define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */
94#define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */
95#define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */
96#define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */
97#define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */
98#define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */
99#define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */
100#define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */
101#define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */
102#define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */
103#define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */
104#define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */
105#define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */
106#define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */
107#define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */
108#define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
109#define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
110#define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
111#define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
112#define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
113#define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
114#define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
115#define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
116#define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */
117#define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */
118#define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */
119#define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */
120#define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */
121#define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */
122#define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */
123#define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */
124#define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
125#define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
126#define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
127#define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */
128#define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */
129#define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
130#define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
131
132#define S1DREG_DELAYOFF 0xFFFE
133#define S1DREG_DELAYON 0xFFFF
134
135/* Note: all above defines should go in separate header files
136 when implementing other S1D13xxx chip support. */
137
138struct s1d13xxxfb_regval {
139 u16 addr;
140 u8 value;
141};
142
143
144struct s1d13xxxfb_par {
145 void __iomem *regs;
146 unsigned char display;
147
148 unsigned int pseudo_palette[16];
149#ifdef CONFIG_PM
150 void *regs_save; /* pm saves all registers here */
151 void *disp_save; /* pm saves entire screen here */
152#endif
153};
154
155struct s1d13xxxfb_pdata {
156 const struct s1d13xxxfb_regval *initregs;
157 const unsigned int initregssize;
158 void (*platform_init_video)(void);
159#ifdef CONFIG_PM
160 int (*platform_suspend_video)(void);
161 int (*platform_resume_video)(void);
162#endif
163};
164
165#endif
166
diff --git a/include/video/s3blit.h b/include/video/s3blit.h
new file mode 100644
index 000000000000..b1db63187b4e
--- /dev/null
+++ b/include/video/s3blit.h
@@ -0,0 +1,79 @@
1#ifndef _VIDEO_S3BLIT_H
2#define _VIDEO_S3BLIT_H
3
4/* s3 commands */
5#define S3_BITBLT 0xc011
6#define S3_TWOPOINTLINE 0x2811
7#define S3_FILLEDRECT 0x40b1
8
9#define S3_FIFO_EMPTY 0x0400
10#define S3_HDW_BUSY 0x0200
11
12/* Enhanced register mapping (MMIO mode) */
13
14#define S3_READ_SEL 0xbee8 /* offset f */
15#define S3_MULT_MISC 0xbee8 /* offset e */
16#define S3_ERR_TERM 0x92e8
17#define S3_FRGD_COLOR 0xa6e8
18#define S3_BKGD_COLOR 0xa2e8
19#define S3_PIXEL_CNTL 0xbee8 /* offset a */
20#define S3_FRGD_MIX 0xbae8
21#define S3_BKGD_MIX 0xb6e8
22#define S3_CUR_Y 0x82e8
23#define S3_CUR_X 0x86e8
24#define S3_DESTY_AXSTP 0x8ae8
25#define S3_DESTX_DIASTP 0x8ee8
26#define S3_MIN_AXIS_PCNT 0xbee8 /* offset 0 */
27#define S3_MAJ_AXIS_PCNT 0x96e8
28#define S3_CMD 0x9ae8
29#define S3_GP_STAT 0x9ae8
30#define S3_ADVFUNC_CNTL 0x4ae8
31#define S3_WRT_MASK 0xaae8
32#define S3_RD_MASK 0xaee8
33
34/* Enhanced register mapping (Packed MMIO mode, write only) */
35#define S3_ALT_CURXY 0x8100
36#define S3_ALT_CURXY2 0x8104
37#define S3_ALT_STEP 0x8108
38#define S3_ALT_STEP2 0x810c
39#define S3_ALT_ERR 0x8110
40#define S3_ALT_CMD 0x8118
41#define S3_ALT_MIX 0x8134
42#define S3_ALT_PCNT 0x8148
43#define S3_ALT_PAT 0x8168
44
45/* Drawing modes */
46#define S3_NOTCUR 0x0000
47#define S3_LOGICALZERO 0x0001
48#define S3_LOGICALONE 0x0002
49#define S3_LEAVEASIS 0x0003
50#define S3_NOTNEW 0x0004
51#define S3_CURXORNEW 0x0005
52#define S3_NOT_CURXORNEW 0x0006
53#define S3_NEW 0x0007
54#define S3_NOTCURORNOTNEW 0x0008
55#define S3_CURORNOTNEW 0x0009
56#define S3_NOTCURORNEW 0x000a
57#define S3_CURORNEW 0x000b
58#define S3_CURANDNEW 0x000c
59#define S3_NOTCURANDNEW 0x000d
60#define S3_CURANDNOTNEW 0x000e
61#define S3_NOTCURANDNOTNEW 0x000f
62
63#define S3_CRTC_ADR 0x03d4
64#define S3_CRTC_DATA 0x03d5
65
66#define S3_REG_LOCK2 0x39
67#define S3_HGC_MODE 0x45
68
69#define S3_HWGC_ORGX_H 0x46
70#define S3_HWGC_ORGX_L 0x47
71#define S3_HWGC_ORGY_H 0x48
72#define S3_HWGC_ORGY_L 0x49
73#define S3_HWGC_DX 0x4e
74#define S3_HWGC_DY 0x4f
75
76
77#define S3_LAW_CTL 0x58
78
79#endif /* _VIDEO_S3BLIT_H */
diff --git a/include/video/sgivw.h b/include/video/sgivw.h
new file mode 100644
index 000000000000..55f2a7c024af
--- /dev/null
+++ b/include/video/sgivw.h
@@ -0,0 +1,682 @@
1/*
2 * linux/drivers/video/sgivw.h -- SGI DBE frame buffer device header
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Jeffrey Newquist, newquist@engr.sgi.som
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#ifndef __SGIVWFB_H__
13#define __SGIVWFB_H__
14
15#define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->reg)
16#define DBE_SETREG(reg, src) DBE_REG_BASE->reg = (src)
17#define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->reg[idx])
18#define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->reg[idx] = (src))
19
20#define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
21#define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
22#define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
23
24#define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
25#define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
26
27/* NOTE: All loads/stores must be 32 bits and uncached */
28
29#define DBE_REG_PHYS 0xd0000000
30#define DBE_REG_SIZE 0x01000000
31
32struct asregs {
33 volatile u32 ctrlstat; /* 0x000000 general control */
34 volatile u32 dotclock; /* 0x000004 dot clock PLL control */
35 volatile u32 i2c; /* 0x000008 crt I2C control */
36 volatile u32 sysclk; /* 0x00000c system clock PLL control */
37 volatile u32 i2cfp; /* 0x000010 flat panel I2C control */
38 volatile u32 id; /* 0x000014 device id/chip revision */
39 volatile u32 config; /* 0x000018 power on configuration */
40 volatile u32 bist; /* 0x00001c internal bist status */
41
42 char _pad0[ 0x010000 - 0x000020 ];
43
44 volatile u32 vt_xy; /* 0x010000 current dot coords */
45 volatile u32 vt_xymax; /* 0x010004 maximum dot coords */
46 volatile u32 vt_vsync; /* 0x010008 vsync on/off */
47 volatile u32 vt_hsync; /* 0x01000c hsync on/off */
48 volatile u32 vt_vblank; /* 0x010010 vblank on/off */
49 volatile u32 vt_hblank; /* 0x010014 hblank on/off */
50 volatile u32 vt_flags; /* 0x010018 polarity of vt signals */
51 volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */
52 volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */
53 volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */
54 volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */
55 volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */
56 volatile u32 fp_de; /* 0x010030 flat panel de on/off */
57 volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/
58 volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */
59 volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */
60 volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */
61 volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */
62 volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */
63 volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */
64
65 char _pad1[ 0x020000 - 0x010050 ];
66
67 volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */
68 volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */
69 volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */
70
71 char _pad2[ 0x030000 - 0x02000C ];
72
73 volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */
74 volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */
75 volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */
76 volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */
77
78 char _pad3[ 0x040000 - 0x030010 ];
79
80 volatile u32 did_inhwctrl; /* 0x040000 DID control */
81 volatile u32 did_control; /* 0x040004 DID shadow */
82
83 char _pad4[ 0x048000 - 0x040008 ];
84
85 volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */
86
87 char _pad5[ 0x050000 - 0x048080 ];
88
89 volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */
90
91 char _pad6[ 0x058000 - 0x056000 ];
92
93 volatile u32 cm_fifo; /* 0x058000 color map fifo status */
94
95 char _pad7[ 0x060000 - 0x058004 ];
96
97 volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */
98
99 char _pad8[ 0x068000 - 0x060400 ];
100
101 volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */
102
103 char _pad9[ 0x070000 - 0x069000 ];
104
105 volatile u32 crs_pos; /* 0x070000 cusror control 0 */
106 volatile u32 crs_ctl; /* 0x070004 cusror control 1 */
107 volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */
108
109 char _pad10[ 0x078000 - 0x070014 ];
110
111 volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */
112
113 char _pad11[ 0x080000 - 0x078100 ];
114
115 volatile u32 vc_0; /* 0x080000 video capture crtl 0 */
116 volatile u32 vc_1; /* 0x080004 video capture crtl 1 */
117 volatile u32 vc_2; /* 0x080008 video capture crtl 2 */
118 volatile u32 vc_3; /* 0x08000c video capture crtl 3 */
119 volatile u32 vc_4; /* 0x080010 video capture crtl 3 */
120 volatile u32 vc_5; /* 0x080014 video capture crtl 3 */
121 volatile u32 vc_6; /* 0x080018 video capture crtl 3 */
122 volatile u32 vc_7; /* 0x08001c video capture crtl 3 */
123 volatile u32 vc_8; /* 0x08000c video capture crtl 3 */
124};
125
126/* Bit mask information */
127
128#define DBE_CTRLSTAT_CHIPID_MSB 3
129#define DBE_CTRLSTAT_CHIPID_LSB 0
130#define DBE_CTRLSTAT_SENSE_N_MSB 4
131#define DBE_CTRLSTAT_SENSE_N_LSB 4
132#define DBE_CTRLSTAT_PCLKSEL_MSB 29
133#define DBE_CTRLSTAT_PCLKSEL_LSB 28
134
135#define DBE_DOTCLK_M_MSB 7
136#define DBE_DOTCLK_M_LSB 0
137#define DBE_DOTCLK_N_MSB 13
138#define DBE_DOTCLK_N_LSB 8
139#define DBE_DOTCLK_P_MSB 15
140#define DBE_DOTCLK_P_LSB 14
141#define DBE_DOTCLK_RUN_MSB 20
142#define DBE_DOTCLK_RUN_LSB 20
143
144#define DBE_VT_XY_VT_FREEZE_MSB 31
145#define DBE_VT_XY_VT_FREEZE_LSB 31
146
147#define DBE_FP_VDRV_FP_VDRV_ON_MSB 23
148#define DBE_FP_VDRV_FP_VDRV_ON_LSB 12
149#define DBE_FP_VDRV_FP_VDRV_OFF_MSB 11
150#define DBE_FP_VDRV_FP_VDRV_OFF_LSB 0
151
152#define DBE_FP_HDRV_FP_HDRV_ON_MSB 23
153#define DBE_FP_HDRV_FP_HDRV_ON_LSB 12
154#define DBE_FP_HDRV_FP_HDRV_OFF_MSB 11
155#define DBE_FP_HDRV_FP_HDRV_OFF_LSB 0
156
157#define DBE_FP_DE_FP_DE_ON_MSB 23
158#define DBE_FP_DE_FP_DE_ON_LSB 12
159#define DBE_FP_DE_FP_DE_OFF_MSB 11
160#define DBE_FP_DE_FP_DE_OFF_LSB 0
161
162#define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23
163#define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12
164#define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11
165#define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0
166
167#define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23
168#define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12
169#define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11
170#define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0
171
172#define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23
173#define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12
174#define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11
175#define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0
176
177#define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23
178#define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12
179#define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11
180#define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0
181
182#define DBE_VT_FLAGS_VDRV_INVERT_MSB 0
183#define DBE_VT_FLAGS_VDRV_INVERT_LSB 0
184#define DBE_VT_FLAGS_HDRV_INVERT_MSB 2
185#define DBE_VT_FLAGS_HDRV_INVERT_LSB 2
186
187#define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23
188#define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12
189#define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11
190#define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0
191
192#define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23
193#define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12
194#define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11
195#define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0
196
197#define DBE_VT_XYMAX_VT_MAXX_MSB 11
198#define DBE_VT_XYMAX_VT_MAXX_LSB 0
199#define DBE_VT_XYMAX_VT_MAXY_MSB 23
200#define DBE_VT_XYMAX_VT_MAXY_LSB 12
201
202#define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23
203#define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12
204#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11
205#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0
206
207#define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23
208#define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12
209#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11
210#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0
211
212#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0
213#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0
214
215#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0
216#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0
217
218#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13
219#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13
220
221#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0
222#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0
223#define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31
224#define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9
225#define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1
226#define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1
227
228#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0
229#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0
230
231#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12
232#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5
233#define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4
234#define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0
235#define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14
236#define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13
237#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15
238#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15
239
240#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31
241#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16
242
243#define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0
244#define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0
245#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0
246#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0
247
248#define DBE_DID_START_XY_DID_STARTY_MSB 23
249#define DBE_DID_START_XY_DID_STARTY_LSB 12
250#define DBE_DID_START_XY_DID_STARTX_MSB 11
251#define DBE_DID_START_XY_DID_STARTX_LSB 0
252
253#define DBE_CRS_START_XY_CRS_STARTY_MSB 23
254#define DBE_CRS_START_XY_CRS_STARTY_LSB 12
255#define DBE_CRS_START_XY_CRS_STARTX_MSB 11
256#define DBE_CRS_START_XY_CRS_STARTX_LSB 0
257
258#define DBE_WID_TYP_MSB 4
259#define DBE_WID_TYP_LSB 2
260#define DBE_WID_BUF_MSB 1
261#define DBE_WID_BUF_LSB 0
262
263#define DBE_VC_START_XY_VC_STARTY_MSB 23
264#define DBE_VC_START_XY_VC_STARTY_LSB 12
265#define DBE_VC_START_XY_VC_STARTX_MSB 11
266#define DBE_VC_START_XY_VC_STARTX_LSB 0
267
268/* Constants */
269
270#define DBE_FRM_DEPTH_8 0
271#define DBE_FRM_DEPTH_16 1
272#define DBE_FRM_DEPTH_32 2
273
274#define DBE_CMODE_I8 0
275#define DBE_CMODE_I12 1
276#define DBE_CMODE_RG3B2 2
277#define DBE_CMODE_RGB4 3
278#define DBE_CMODE_ARGB5 4
279#define DBE_CMODE_RGB8 5
280#define DBE_CMODE_RGBA5 6
281#define DBE_CMODE_RGB10 7
282
283#define DBE_BMODE_BOTH 3
284
285#define DBE_CRS_MAGIC 54
286
287#define DBE_CLOCK_REF_KHZ 27000
288
289/* Config Register (DBE Only) Definitions */
290
291#define DBE_CONFIG_VDAC_ENABLE 0x00000001
292#define DBE_CONFIG_VDAC_GSYNC 0x00000002
293#define DBE_CONFIG_VDAC_PBLANK 0x00000004
294#define DBE_CONFIG_FPENABLE 0x00000008
295#define DBE_CONFIG_LENDIAN 0x00000020
296#define DBE_CONFIG_TILEHIST 0x00000040
297#define DBE_CONFIG_EXT_ADDR 0x00000080
298
299#define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \
300 DBE_CONFIG_VDAC_GSYNC | \
301 DBE_CONFIG_VDAC_PBLANK | \
302 DBE_CONFIG_LENDIAN | \
303 DBE_CONFIG_EXT_ADDR )
304
305/*
306 * Available Video Timings and Corresponding Indices
307 */
308
309typedef enum {
310 DBE_VT_640_480_60,
311
312 DBE_VT_800_600_60,
313 DBE_VT_800_600_75,
314 DBE_VT_800_600_120,
315
316 DBE_VT_1024_768_50,
317 DBE_VT_1024_768_60,
318 DBE_VT_1024_768_75,
319 DBE_VT_1024_768_85,
320 DBE_VT_1024_768_120,
321
322 DBE_VT_1280_1024_50,
323 DBE_VT_1280_1024_60,
324 DBE_VT_1280_1024_75,
325 DBE_VT_1280_1024_85,
326
327 DBE_VT_1600_1024_53,
328 DBE_VT_1600_1024_60,
329
330 DBE_VT_1600_1200_50,
331 DBE_VT_1600_1200_60,
332 DBE_VT_1600_1200_75,
333
334 DBE_VT_1920_1080_50,
335 DBE_VT_1920_1080_60,
336 DBE_VT_1920_1080_72,
337
338 DBE_VT_1920_1200_50,
339 DBE_VT_1920_1200_60,
340 DBE_VT_1920_1200_66,
341
342 DBE_VT_UNKNOWN
343} dbe_timing_t;
344
345
346
347/*
348 * Crime Video Timing Data Structure
349 */
350
351struct dbe_timing_info
352{
353 dbe_timing_t type;
354 int flags;
355 short width; /* Monitor resolution */
356 short height;
357 int fields_sec; /* fields/sec (Hz -3 dec. places */
358 int cfreq; /* pixel clock frequency (MHz -3 dec. places) */
359 short htotal; /* Horizontal total pixels */
360 short hblank_start; /* Horizontal blank start */
361 short hblank_end; /* Horizontal blank end */
362 short hsync_start; /* Horizontal sync start */
363 short hsync_end; /* Horizontal sync end */
364 short vtotal; /* Vertical total lines */
365 short vblank_start; /* Vertical blank start */
366 short vblank_end; /* Vertical blank end */
367 short vsync_start; /* Vertical sync start */
368 short vsync_end; /* Vertical sync end */
369 short pll_m; /* PLL M parameter */
370 short pll_n; /* PLL P parameter */
371 short pll_p; /* PLL N parameter */
372};
373
374/* Defines for dbe_vof_info_t flags */
375
376#define DBE_VOF_UNKNOWNMON 1
377#define DBE_VOF_STEREO 2
378#define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */
379#define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */
380#define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */
381#define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */
382
383/*
384 * DBE Timing Tables
385 */
386
387#ifdef INCLUDE_TIMING_TABLE_DATA
388struct dbe_timing_info dbeVTimings[] = {
389 {
390 DBE_VT_640_480_60,
391 /* flags, width, height, fields_sec, cfreq */
392 0, 640, 480, 59940, 25175,
393 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
394 800, 640, 800, 656, 752,
395 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
396 525, 480, 525, 490, 492,
397 /* pll_m, pll_n, pll_p */
398 15, 2, 3
399 },
400
401 {
402 DBE_VT_800_600_60,
403 /* flags, width, height, fields_sec, cfreq */
404 0, 800, 600, 60317, 40000,
405 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
406 1056, 800, 1056, 840, 968,
407 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
408 628, 600, 628, 601, 605,
409 /* pll_m, pll_n, pll_p */
410 3, 1, 1
411 },
412
413 {
414 DBE_VT_800_600_75,
415 /* flags, width, height, fields_sec, cfreq */
416 0, 800, 600, 75000, 49500,
417 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
418 1056, 800, 1056, 816, 896,
419 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
420 625, 600, 625, 601, 604,
421 /* pll_m, pll_n, pll_p */
422 11, 3, 1
423 },
424
425 {
426 DBE_VT_800_600_120,
427 /* flags, width, height, fields_sec, cfreq */
428 DBE_VOF_STEREO, 800, 600, 119800, 82978,
429 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
430 1040, 800, 1040, 856, 976,
431 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
432 666, 600, 666, 637, 643,
433 /* pll_m, pll_n, pll_p */
434 31, 5, 1
435 },
436
437 {
438 DBE_VT_1024_768_50,
439 /* flags, width, height, fields_sec, cfreq */
440 0, 1024, 768, 50000, 54163,
441 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
442 1344, 1024, 1344, 1048, 1184,
443 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
444 806, 768, 806, 771, 777,
445 /* pll_m, pll_n, pll_p */
446 4, 1, 1
447 },
448
449 {
450 DBE_VT_1024_768_60,
451 /* flags, width, height, fields_sec, cfreq */
452 0, 1024, 768, 60004, 65000,
453 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
454 1344, 1024, 1344, 1048, 1184,
455 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
456 806, 768, 806, 771, 777,
457 /* pll_m, pll_n, pll_p */
458 12, 5, 0
459 },
460
461 {
462 DBE_VT_1024_768_75,
463 /* flags, width, height, fields_sec, cfreq */
464 0, 1024, 768, 75029, 78750,
465 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
466 1312, 1024, 1312, 1040, 1136,
467 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
468 800, 768, 800, 769, 772,
469 /* pll_m, pll_n, pll_p */
470 29, 5, 1
471 },
472
473 {
474 DBE_VT_1024_768_85,
475 /* flags, width, height, fields_sec, cfreq */
476 0, 1024, 768, 84997, 94500,
477 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
478 1376, 1024, 1376, 1072, 1168,
479 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
480 808, 768, 808, 769, 772,
481 /* pll_m, pll_n, pll_p */
482 7, 2, 0
483 },
484
485 {
486 DBE_VT_1024_768_120,
487 /* flags, width, height, fields_sec, cfreq */
488 DBE_VOF_STEREO, 1024, 768, 119800, 133195,
489 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
490 1376, 1024, 1376, 1072, 1168,
491 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
492 808, 768, 808, 769, 772,
493 /* pll_m, pll_n, pll_p */
494 5, 1, 0
495 },
496
497 {
498 DBE_VT_1280_1024_50,
499 /* flags, width, height, fields_sec, cfreq */
500 0, 1280, 1024, 50000, 89460,
501 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
502 1680, 1280, 1680, 1360, 1480,
503 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
504 1065, 1024, 1065, 1027, 1030,
505 /* pll_m, pll_n, pll_p */
506 10, 3, 0
507 },
508
509 {
510 DBE_VT_1280_1024_60,
511 /* flags, width, height, fields_sec, cfreq */
512 0, 1280, 1024, 60020, 108000,
513 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
514 1688, 1280, 1688, 1328, 1440,
515 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
516 1066, 1024, 1066, 1025, 1028,
517 /* pll_m, pll_n, pll_p */
518 4, 1, 0
519 },
520
521 {
522 DBE_VT_1280_1024_75,
523 /* flags, width, height, fields_sec, cfreq */
524 0, 1280, 1024, 75025, 135000,
525 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
526 1688, 1280, 1688, 1296, 1440,
527 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
528 1066, 1024, 1066, 1025, 1028,
529 /* pll_m, pll_n, pll_p */
530 5, 1, 0
531 },
532
533 {
534 DBE_VT_1280_1024_85,
535 /* flags, width, height, fields_sec, cfreq */
536 0, 1280, 1024, 85024, 157500,
537 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
538 1728, 1280, 1728, 1344, 1504,
539 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
540 1072, 1024, 1072, 1025, 1028,
541 /* pll_m, pll_n, pll_p */
542 29, 5, 0
543 },
544
545 {
546 DBE_VT_1600_1024_53,
547 /* flags, width, height, fields_sec, cfreq */
548 DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY,
549 1600, 1024, 53000, 107447,
550 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
551 1900, 1600, 1900, 1630, 1730,
552 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
553 1067, 1024, 1067, 1027, 1030,
554 /* pll_m, pll_n, pll_p */
555 4, 1, 0
556 },
557
558 {
559 DBE_VT_1600_1024_60,
560 /* flags, width, height, fields_sec, cfreq */
561 DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913,
562 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
563 1670, 1600, 1670, 1630, 1650,
564 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
565 1067, 1024, 1067, 1027, 1030,
566 /* pll_m, pll_n, pll_p */
567 4, 1, 0
568 },
569
570 {
571 DBE_VT_1600_1200_50,
572 /* flags, width, height, fields_sec, cfreq */
573 0, 1600, 1200, 50000, 130500,
574 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
575 2088, 1600, 2088, 1644, 1764,
576 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
577 1250, 1200, 1250, 1205, 1211,
578 /* pll_m, pll_n, pll_p */
579 24, 5, 0
580 },
581
582 {
583 DBE_VT_1600_1200_60,
584 /* flags, width, height, fields_sec, cfreq */
585 0, 1600, 1200, 59940, 162000,
586 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
587 2160, 1600, 2160, 1644, 1856,
588 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
589 1250, 1200, 1250, 1201, 1204,
590 /* pll_m, pll_n, pll_p */
591 6, 1, 0
592 },
593
594 {
595 DBE_VT_1600_1200_75,
596 /* flags, width, height, fields_sec, cfreq */
597 0, 1600, 1200, 75000, 202500,
598 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
599 2160, 1600, 2160, 1644, 1856,
600 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
601 1250, 1200, 1250, 1201, 1204,
602 /* pll_m, pll_n, pll_p */
603 15, 2, 0
604 },
605
606 {
607 DBE_VT_1920_1080_50,
608 /* flags, width, height, fields_sec, cfreq */
609 0, 1920, 1080, 50000, 133200,
610 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
611 2368, 1920, 2368, 1952, 2096,
612 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
613 1125, 1080, 1125, 1083, 1086,
614 /* pll_m, pll_n, pll_p */
615 5, 1, 0
616 },
617
618 {
619 DBE_VT_1920_1080_60,
620 /* flags, width, height, fields_sec, cfreq */
621 0, 1920, 1080, 59940, 159840,
622 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
623 2368, 1920, 2368, 1952, 2096,
624 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
625 1125, 1080, 1125, 1083, 1086,
626 /* pll_m, pll_n, pll_p */
627 6, 1, 0
628 },
629
630 {
631 DBE_VT_1920_1080_72,
632 /* flags, width, height, fields_sec, cfreq */
633 0, 1920, 1080, 72000, 216023,
634 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
635 2560, 1920, 2560, 1968, 2184,
636 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
637 1172, 1080, 1172, 1083, 1086,
638 /* pll_m, pll_n, pll_p */
639 8, 1, 0
640 },
641
642 {
643 DBE_VT_1920_1200_50,
644 /* flags, width, height, fields_sec, cfreq */
645 0, 1920, 1200, 50000, 161500,
646 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
647 2584, 1920, 2584, 1984, 2240,
648 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
649 1250, 1200, 1250, 1203, 1206,
650 /* pll_m, pll_n, pll_p */
651 6, 1, 0
652 },
653
654 {
655 DBE_VT_1920_1200_60,
656 /* flags, width, height, fields_sec, cfreq */
657 0, 1920, 1200, 59940, 193800,
658 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
659 2584, 1920, 2584, 1984, 2240,
660 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
661 1250, 1200, 1250, 1203, 1206,
662 /* pll_m, pll_n, pll_p */
663 29, 4, 0
664 },
665
666 {
667 DBE_VT_1920_1200_66,
668 /* flags, width, height, fields_sec, cfreq */
669 0, 1920, 1200, 66000, 213180,
670 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
671 2584, 1920, 2584, 1984, 2240,
672 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
673 1250, 1200, 1250, 1203, 1206,
674 /* pll_m, pll_n, pll_p */
675 8, 1, 0
676 }
677};
678
679#define DBE_VT_SIZE (sizeof(dbeVTimings)/sizeof(dbeVTimings[0]))
680#endif // INCLUDE_TIMING_TABLE_DATA
681
682#endif // ! __SGIVWFB_H__
diff --git a/include/video/sisfb.h b/include/video/sisfb.h
new file mode 100644
index 000000000000..136bf791643d
--- /dev/null
+++ b/include/video/sisfb.h
@@ -0,0 +1,198 @@
1/*
2 * Copyright (C) 2001-2004 by Thomas Winischhofer, Vienna, Austria.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the named License,
7 * or any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
17 */
18
19#ifndef _LINUX_SISFB
20#define _LINUX_SISFB
21
22#include <asm/ioctl.h>
23#include <asm/types.h>
24
25/**********************************************/
26/* PUBLIC */
27/**********************************************/
28
29/* vbflags */
30#define CRT2_DEFAULT 0x00000001
31#define CRT2_LCD 0x00000002 /* TW: Never change the order of the CRT2_XXX entries */
32#define CRT2_TV 0x00000004 /* (see SISCycleCRT2Type()) */
33#define CRT2_VGA 0x00000008
34#define TV_NTSC 0x00000010
35#define TV_PAL 0x00000020
36#define TV_HIVISION 0x00000040
37#define TV_YPBPR 0x00000080
38#define TV_AVIDEO 0x00000100
39#define TV_SVIDEO 0x00000200
40#define TV_SCART 0x00000400
41#define VB_CONEXANT 0x00000800 /* 661 series only */
42#define VB_TRUMPION VB_CONEXANT /* 300 series only */
43#define TV_PALM 0x00001000
44#define TV_PALN 0x00002000
45#define TV_NTSCJ 0x00001000
46#define VB_302ELV 0x00004000
47#define TV_CHSCART 0x00008000
48#define TV_CHYPBPR525I 0x00010000
49#define CRT1_VGA 0x00000000
50#define CRT1_LCDA 0x00020000
51#define VGA2_CONNECTED 0x00040000
52#define VB_DISPTYPE_CRT1 0x00080000 /* CRT1 connected and used */
53#define VB_301 0x00100000 /* Video bridge type */
54#define VB_301B 0x00200000
55#define VB_302B 0x00400000
56#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */
57#define VB_LVDS 0x01000000
58#define VB_CHRONTEL 0x02000000
59#define VB_301LV 0x04000000
60#define VB_302LV 0x08000000
61#define VB_301C 0x10000000
62#define VB_SINGLE_MODE 0x20000000 /* CRT1 or CRT2; determined by DISPTYPE_CRTx */
63#define VB_MIRROR_MODE 0x40000000 /* CRT1 + CRT2 identical (mirror mode) */
64#define VB_DUALVIEW_MODE 0x80000000 /* CRT1 + CRT2 independent (dual head mode) */
65
66/* Aliases: */
67#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA)
68#define TV_STANDARD (TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ)
69#define TV_INTERFACE (TV_AVIDEO|TV_SVIDEO|TV_SCART|TV_HIVISION|TV_YPBPR|TV_CHSCART|TV_CHYPBPR525I)
70
71/* Only if TV_YPBPR is set: */
72#define TV_YPBPR525I TV_NTSC
73#define TV_YPBPR525P TV_PAL
74#define TV_YPBPR750P TV_PALM
75#define TV_YPBPR1080I TV_PALN
76#define TV_YPBPRALL (TV_YPBPR525I | TV_YPBPR525P | TV_YPBPR750P | TV_YPBPR1080I)
77
78#define VB_SISBRIDGE (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV)
79#define VB_SISTVBRIDGE (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV)
80#define VB_VIDEOBRIDGE (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT)
81
82#define VB_DISPTYPE_DISP2 CRT2_ENABLE
83#define VB_DISPTYPE_CRT2 CRT2_ENABLE
84#define VB_DISPTYPE_DISP1 VB_DISPTYPE_CRT1
85#define VB_DISPMODE_SINGLE VB_SINGLE_MODE
86#define VB_DISPMODE_MIRROR VB_MIRROR_MODE
87#define VB_DISPMODE_DUAL VB_DUALVIEW_MODE
88#define VB_DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE)
89
90/* Structure argument for SISFB_GET_INFO ioctl */
91typedef struct _SISFB_INFO sisfb_info, *psisfb_info;
92
93struct _SISFB_INFO {
94 __u32 sisfb_id; /* for identifying sisfb */
95#ifndef SISFB_ID
96#define SISFB_ID 0x53495346 /* Identify myself with 'SISF' */
97#endif
98 __u32 chip_id; /* PCI-ID of detected chip */
99 __u32 memory; /* video memory in KB which sisfb manages */
100 __u32 heapstart; /* heap start (= sisfb "mem" argument) in KB */
101 __u8 fbvidmode; /* current sisfb mode */
102
103 __u8 sisfb_version;
104 __u8 sisfb_revision;
105 __u8 sisfb_patchlevel;
106
107 __u8 sisfb_caps; /* sisfb capabilities */
108
109 __u32 sisfb_tqlen; /* turbo queue length (in KB) */
110
111 __u32 sisfb_pcibus; /* The card's PCI ID */
112 __u32 sisfb_pcislot;
113 __u32 sisfb_pcifunc;
114
115 __u8 sisfb_lcdpdc; /* PanelDelayCompensation */
116
117 __u8 sisfb_lcda; /* Detected status of LCDA for low res/text modes */
118
119 __u32 sisfb_vbflags;
120 __u32 sisfb_currentvbflags;
121
122 __u32 sisfb_scalelcd;
123 __u32 sisfb_specialtiming;
124
125 __u8 sisfb_haveemi;
126 __u8 sisfb_emi30,sisfb_emi31,sisfb_emi32,sisfb_emi33;
127 __u8 sisfb_haveemilcd;
128
129 __u8 sisfb_lcdpdca; /* PanelDelayCompensation for LCD-via-CRT1 */
130
131 __u16 sisfb_tvxpos, sisfb_tvypos; /* Warning: Values + 32 ! */
132
133 __u8 reserved[208]; /* for future use */
134};
135
136/* Addtional IOCTLs for communication sisfb <> X driver */
137/* If changing this, vgatypes.h must also be changed (for X driver) */
138
139/* ioctl for identifying and giving some info (esp. memory heap start) */
140#define SISFB_GET_INFO_SIZE _IOR(0xF3,0x00,__u32)
141#define SISFB_GET_INFO _IOR(0xF3,0x01,struct _SISFB_INFO)
142
143/* ioctrl to get current vertical retrace status */
144#define SISFB_GET_VBRSTATUS _IOR(0xF3,0x02,__u32)
145
146/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */
147#define SISFB_GET_AUTOMAXIMIZE _IOR(0xF3,0x03,__u32)
148#define SISFB_SET_AUTOMAXIMIZE _IOW(0xF3,0x03,__u32)
149
150/* ioctls to relocate TV output (x=D[31:16], y=D[15:0], + 32)*/
151#define SISFB_GET_TVPOSOFFSET _IOR(0xF3,0x04,__u32)
152#define SISFB_SET_TVPOSOFFSET _IOW(0xF3,0x04,__u32)
153
154/* ioctl for locking sisfb (no register access during lock) */
155/* As of now, only used to avoid register access during
156 * the ioctls listed above.
157 */
158#define SISFB_SET_LOCK _IOW(0xF3,0x06,__u32)
159
160/* more to come soon */
161
162/* ioctls 0xF3 up to 0x3F reserved for sisfb */
163
164/****************************************************************/
165/* The following are deprecated and should not be used anymore: */
166/****************************************************************/
167/* ioctl for identifying and giving some info (esp. memory heap start) */
168#define SISFB_GET_INFO_OLD _IOR('n',0xF8,__u32)
169/* ioctrl to get current vertical retrace status */
170#define SISFB_GET_VBRSTATUS_OLD _IOR('n',0xF9,__u32)
171/* ioctl to enable/disable panning auto-maximize (like nomax parameter) */
172#define SISFB_GET_AUTOMAXIMIZE_OLD _IOR('n',0xFA,__u32)
173#define SISFB_SET_AUTOMAXIMIZE_OLD _IOW('n',0xFA,__u32)
174/****************************************************************/
175/* End of deprecated ioctl numbers */
176/****************************************************************/
177
178/* For fb memory manager (FBIO_ALLOC, FBIO_FREE) */
179struct sis_memreq {
180 __u32 offset;
181 __u32 size;
182};
183
184/**********************************************/
185/* PRIVATE */
186/* (for IN-KERNEL usage only) */
187/**********************************************/
188
189#ifdef __KERNEL__
190#define UNKNOWN_VGA 0
191#define SIS_300_VGA 1
192#define SIS_315_VGA 2
193
194extern void sis_malloc(struct sis_memreq *req);
195extern void sis_free(u32 base);
196#endif
197
198#endif
diff --git a/include/video/sstfb.h b/include/video/sstfb.h
new file mode 100644
index 000000000000..0d77b5205372
--- /dev/null
+++ b/include/video/sstfb.h
@@ -0,0 +1,354 @@
1/*
2 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
3 *
4 * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr>
5 *
6 * Created 28 Aug 2001 by Ghozlane Toumi
7 */
8
9
10#ifndef _SSTFB_H_
11#define _SSTFB_H_
12
13/*
14 *
15 * Debug Stuff
16 *
17 */
18
19#ifdef SST_DEBUG
20# define dprintk(X...) printk("sstfb: " X)
21# define SST_DEBUG_REG 1
22# define SST_DEBUG_FUNC 1
23# define SST_DEBUG_VAR 1
24#else
25# define dprintk(X...)
26# define SST_DEBUG_REG 0
27# define SST_DEBUG_FUNC 0
28# define SST_DEBUG_VAR 0
29#endif
30
31#if (SST_DEBUG_REG > 0)
32# define r_dprintk(X...) dprintk(X)
33#else
34# define r_dprintk(X...)
35#endif
36#if (SST_DEBUG_REG > 1)
37# define r_ddprintk(X...) dprintk(" " X)
38#else
39# define r_ddprintk(X...)
40#endif
41
42#if (SST_DEBUG_FUNC > 0)
43# define f_dprintk(X...) dprintk(X)
44#else
45# define f_dprintk(X...)
46#endif
47#if (SST_DEBUG_FUNC > 1)
48# define f_ddprintk(X...) dprintk(" " X)
49#else
50# define f_ddprintk(X...)
51#endif
52#if (SST_DEBUG_FUNC > 2)
53# define f_dddprintk(X...) dprintk(" " X)
54#else
55# define f_dddprintk(X...)
56#endif
57
58#if (SST_DEBUG_VAR > 0)
59# define v_dprintk(X...) dprintk(X)
60# define print_var(V, X...) \
61 { \
62 dprintk(X); \
63 printk(" :\n"); \
64 sst_dbg_print_var(V); \
65 }
66#else
67# define v_dprintk(X...)
68# define print_var(X,Y...)
69#endif
70
71#define eprintk(X...) printk(KERN_ERR "sstfb: " X)
72#define iprintk(X...) printk(KERN_INFO "sstfb: " X)
73#define wprintk(X...) printk(KERN_WARNING "sstfb: " X)
74
75#define BIT(x) (1ul<<(x))
76#define POW2(x) (1ul<<(x))
77
78/*
79 *
80 * Const
81 *
82 */
83
84/* pci stuff */
85#define PCI_INIT_ENABLE 0x40
86# define PCI_EN_INIT_WR BIT(0)
87# define PCI_EN_FIFO_WR BIT(1)
88# define PCI_REMAP_DAC BIT(2)
89#define PCI_VCLK_ENABLE 0xc0 /* enable video */
90#define PCI_VCLK_DISABLE 0xe0
91
92/* register offsets from memBaseAddr */
93#define STATUS 0x0000
94# define STATUS_FBI_BUSY BIT(7)
95#define FBZMODE 0x0110
96# define EN_CLIPPING BIT(0) /* enable clipping */
97# define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
98# define EN_ALPHA_WRITE BIT(10)
99# define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
100#define LFBMODE 0x0114
101# define LFB_565 0 /* bits 3:0 .16 bits RGB */
102# define LFB_888 4 /* 24 bits RGB */
103# define LFB_8888 5 /* 32 bits ARGB */
104# define WR_BUFF_FRONT 0 /* write buf select (front) */
105# define WR_BUFF_BACK (1 << 4) /* back */
106# define RD_BUFF_FRONT 0 /* read buff select (front) */
107# define RD_BUFF_BACK (1 << 6) /* back */
108# define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
109# define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
110# define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
111# define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */
112# define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
113# define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
114#define CLIP_LEFT_RIGHT 0x0118
115#define CLIP_LOWY_HIGHY 0x011c
116#define NOPCMD 0x0120
117#define FASTFILLCMD 0x0124
118#define SWAPBUFFCMD 0x0128
119#define FBIINIT4 0x0200 /* misc controls */
120# define FAST_PCI_READS 0 /* 1 waitstate */
121# define SLOW_PCI_READS BIT(0) /* 2 ws */
122# define LFB_READ_AHEAD BIT(1)
123#define BACKPORCH 0x0208
124#define VIDEODIMENSIONS 0x020c
125#define FBIINIT0 0x0210 /* misc+fifo controls */
126# define EN_VGA_PASSTHROUGH BIT(0)
127# define FBI_RESET BIT(1)
128# define FIFO_RESET BIT(2)
129#define FBIINIT1 0x0214 /* PCI + video controls */
130# define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/
131# define FAST_PCI_WRITES 0 /* 0 ws */
132# define SLOW_PCI_WRITES BIT(1) /* 1 ws */
133# define EN_LFB_READ BIT(3)
134# define TILES_IN_X_SHIFT 4
135# define VIDEO_RESET BIT(8)
136# define EN_BLANKING BIT(12)
137# define EN_DATA_OE BIT(13)
138# define EN_BLANK_OE BIT(14)
139# define EN_HVSYNC_OE BIT(15)
140# define EN_DCLK_OE BIT(16)
141# define SEL_INPUT_VCLK_2X 0 /* bit 17 */
142# define SEL_INPUT_VCLK_SLAVE BIT(17)
143# define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */
144# define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20)
145# define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20)
146# define EN_24BPP BIT(22)
147# define TILES_IN_X_MSB_SHIFT 24 /* v2 */
148# define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */
149# define VCLK_DEL_SHIFT 29 /* vclk in delay */
150#define FBIINIT2 0x0218 /* Dram controls */
151# define EN_FAST_RAS_READ BIT(5)
152# define EN_DRAM_OE BIT(6)
153# define EN_FAST_RD_AHEAD_WR BIT(7)
154# define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */
155# define SWAP_DACVSYNC 0
156# define SWAP_DACDATA0 (1 << 9)
157# define SWAP_FIFO_STALL (2 << 9)
158# define EN_RD_AHEAD_FIFO BIT(21)
159# define EN_DRAM_REFRESH BIT(22)
160# define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */
161#define DAC_READ FBIINIT2 /* in remap mode */
162#define FBIINIT3 0x021c /* fbi controls */
163# define DISABLE_TEXTURE BIT(6)
164# define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap substraction value */
165#define HSYNC 0x0220
166#define VSYNC 0x0224
167#define DAC_DATA 0x022c
168# define DAC_READ_CMD BIT(11) /* set read dacreg mode */
169#define FBIINIT5 0x0244 /* v2 specific */
170# define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/
171# define HDOUBLESCAN BIT(20)
172# define VDOUBLESCAN BIT(21)
173# define HSYNC_HIGH BIT(23)
174# define VSYNC_HIGH BIT(24)
175# define INTERLACE BIT(26)
176#define FBIINIT6 0x0248 /* v2 specific */
177# define TILES_IN_X_LSB_SHIFT 30 /* v2 */
178#define FBIINIT7 0x024c /* v2 specific */
179
180#define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
181#define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */
182#define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
183#define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
184#define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */
185#define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */
186#define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */
187#define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
188#define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */
189#define BLTSIZE 0x02e8 /* BitBLT width and height */
190#define BLTROP 0x02ec /* BitBLT Raster operations */
191# define BLTROP_COPY 0x0cccc
192# define BLTROP_INVERT 0x05555
193# define BLTROP_XOR 0x06666
194#define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */
195#define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */
196# define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
197# define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
198# define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */
199# define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
200#define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
201# define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */
202
203/* Dac Registers */
204#define DACREG_WMA 0x0 /* pixel write mode address */
205#define DACREG_LUT 0x01 /* color value */
206#define DACREG_RMR 0x02 /* pixel mask */
207#define DACREG_RMA 0x03 /* pixel read mode address */
208/*Dac registers in indexed mode (TI, ATT dacs) */
209#define DACREG_ADDR_I DACREG_WMA
210#define DACREG_DATA_I DACREG_RMR
211#define DACREG_RMR_I 0x00
212#define DACREG_CR0_I 0x01
213# define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */
214# define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */
215# define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */
216# define DACREG_CR0_16BPP 0x30 /* mode 3 */
217# define DACREG_CR0_24BPP 0x50 /* mode 5 */
218#define DACREG_CR1_I 0x05
219#define DACREG_CC_I 0x06
220# define DACREG_CC_CLKA BIT(7) /* clk A controled by regs */
221# define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */
222# define DACREG_CC_CLKB BIT(3) /* clk B controled by regs */
223# define DACREG_CC_CLKB_D 3 /* clkB uses reg D */
224#define DACREG_AC0_I 0x48 /* clock A reg C */
225#define DACREG_AC1_I 0x49
226#define DACREG_BD0_I 0x6c /* clock B reg D */
227#define DACREG_BD1_I 0x6d
228
229/* identification constants */
230#define DACREG_MIR_TI 0x97
231#define DACREG_DIR_TI 0x09
232#define DACREG_MIR_ATT 0x84
233#define DACREG_DIR_ATT 0x09
234/* ics dac specific registers */
235#define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */
236#define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */
237#define DACREG_ICS_CMD 0x06 /* command */
238# define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
239# define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
240# define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */
241#define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */
242/*
243 * pll parameter register:
244 * indexed : write addr to PLLWMA, write data in PLLDATA.
245 * for reads use PLLRMA .
246 * 8 freq registers (0-7) for video clock (CLK0)
247 * 2 freq registers (a-b) for graphic clock (CLK1)
248 */
249#define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
250#define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */
251#define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */
252#define DACREG_ICS_PLL_CTRL 0x0e
253# define DACREG_ICS_CLK0 BIT(5)
254# define DACREG_ICS_CLK0_0 0
255# define DACREG_ICS_CLK1_A 0 /* bit4 */
256
257/* sst default init registers */
258#define FBIINIT0_DEFAULT EN_VGA_PASSTHROUGH
259
260#define FBIINIT1_DEFAULT \
261 ( \
262 FAST_PCI_WRITES \
263/* SLOW_PCI_WRITES*/ \
264 | VIDEO_RESET \
265 | 10 << TILES_IN_X_SHIFT\
266 | SEL_SOURCE_VCLK_2X_SEL\
267 | EN_LFB_READ \
268 )
269
270#define FBIINIT2_DEFAULT \
271 ( \
272 SWAP_DACVSYNC \
273 | EN_DRAM_OE \
274 | DRAM_REFRESH_16 \
275 | EN_DRAM_REFRESH \
276 | EN_FAST_RAS_READ \
277 | EN_RD_AHEAD_FIFO \
278 | EN_FAST_RD_AHEAD_WR \
279 )
280
281#define FBIINIT3_DEFAULT \
282 ( DISABLE_TEXTURE )
283
284#define FBIINIT4_DEFAULT \
285 ( \
286 FAST_PCI_READS \
287/* SLOW_PCI_READS*/ \
288 | LFB_READ_AHEAD \
289 )
290/* Careful with this one : writing back the data just read will trash the DAC
291 reading some fields give logic value on pins, but setting this field will
292 set the source signal driving the pin. conclusion : just use the default
293 as a base before writing back .
294*/
295#define FBIINIT6_DEFAULT (0x0)
296
297/*
298 *
299 * Misc Const
300 *
301 */
302
303/* used to know witch clock to set */
304enum {
305 VID_CLOCK=0,
306 GFX_CLOCK=1,
307};
308
309/* freq max */
310#define DAC_FREF 14318 /* DAC reference freq (Khz) */
311#define VCO_MAX 260000
312
313/*
314 * driver structs
315 */
316
317struct pll_timing {
318 unsigned int m;
319 unsigned int n;
320 unsigned int p;
321};
322
323struct dac_switch {
324 char * name;
325 int (*detect) (struct fb_info *info);
326 int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock);
327 void (*set_vidmod) (struct fb_info *info, const int bpp);
328};
329
330struct sst_spec {
331 char * name;
332 int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */
333 int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */
334};
335
336struct sstfb_par {
337 unsigned int yDim;
338 unsigned int hSyncOn; /* hsync_len */
339 unsigned int hSyncOff; /* left_margin + xres + right_margin */
340 unsigned int hBackPorch;/* left_margin */
341 unsigned int vSyncOn;
342 unsigned int vSyncOff;
343 unsigned int vBackPorch;
344 struct pll_timing pll;
345 unsigned int tiles_in_X;/* num of tiles in X res */
346 u8 __iomem *mmio_vbase;
347 struct dac_switch dac_sw; /* dac specific functions */
348 struct pci_dev *dev;
349 int type;
350 u8 revision;
351 int gfx_clock; /* status */
352};
353
354#endif /* _SSTFB_H_ */
diff --git a/include/video/tdfx.h b/include/video/tdfx.h
new file mode 100644
index 000000000000..a896e4442060
--- /dev/null
+++ b/include/video/tdfx.h
@@ -0,0 +1,192 @@
1#ifndef _TDFX_H
2#define _TDFX_H
3
4/* membase0 register offsets */
5#define STATUS 0x00
6#define PCIINIT0 0x04
7#define SIPMONITOR 0x08
8#define LFBMEMORYCONFIG 0x0c
9#define MISCINIT0 0x10
10#define MISCINIT1 0x14
11#define DRAMINIT0 0x18
12#define DRAMINIT1 0x1c
13#define AGPINIT 0x20
14#define TMUGBEINIT 0x24
15#define VGAINIT0 0x28
16#define VGAINIT1 0x2c
17#define DRAMCOMMAND 0x30
18#define DRAMDATA 0x34
19/* reserved 0x38 */
20/* reserved 0x3c */
21#define PLLCTRL0 0x40
22#define PLLCTRL1 0x44
23#define PLLCTRL2 0x48
24#define DACMODE 0x4c
25#define DACADDR 0x50
26#define DACDATA 0x54
27#define RGBMAXDELTA 0x58
28#define VIDPROCCFG 0x5c
29#define HWCURPATADDR 0x60
30#define HWCURLOC 0x64
31#define HWCURC0 0x68
32#define HWCURC1 0x6c
33#define VIDINFORMAT 0x70
34#define VIDINSTATUS 0x74
35#define VIDSERPARPORT 0x78
36#define VIDINXDELTA 0x7c
37#define VIDININITERR 0x80
38#define VIDINYDELTA 0x84
39#define VIDPIXBUFTHOLD 0x88
40#define VIDCHRMIN 0x8c
41#define VIDCHRMAX 0x90
42#define VIDCURLIN 0x94
43#define VIDSCREENSIZE 0x98
44#define VIDOVRSTARTCRD 0x9c
45#define VIDOVRENDCRD 0xa0
46#define VIDOVRDUDX 0xa4
47#define VIDOVRDUDXOFF 0xa8
48#define VIDOVRDVDY 0xac
49/* ... */
50#define VIDOVRDVDYOFF 0xe0
51#define VIDDESKSTART 0xe4
52#define VIDDESKSTRIDE 0xe8
53#define VIDINADDR0 0xec
54#define VIDINADDR1 0xf0
55#define VIDINADDR2 0xf4
56#define VIDINSTRIDE 0xf8
57#define VIDCUROVRSTART 0xfc
58
59#define INTCTRL (0x00100000 + 0x04)
60#define CLIP0MIN (0x00100000 + 0x08)
61#define CLIP0MAX (0x00100000 + 0x0c)
62#define DSTBASE (0x00100000 + 0x10)
63#define DSTFORMAT (0x00100000 + 0x14)
64#define SRCBASE (0x00100000 + 0x34)
65#define COMMANDEXTRA_2D (0x00100000 + 0x38)
66#define CLIP1MIN (0x00100000 + 0x4c)
67#define CLIP1MAX (0x00100000 + 0x50)
68#define SRCFORMAT (0x00100000 + 0x54)
69#define SRCSIZE (0x00100000 + 0x58)
70#define SRCXY (0x00100000 + 0x5c)
71#define COLORBACK (0x00100000 + 0x60)
72#define COLORFORE (0x00100000 + 0x64)
73#define DSTSIZE (0x00100000 + 0x68)
74#define DSTXY (0x00100000 + 0x6c)
75#define COMMAND_2D (0x00100000 + 0x70)
76#define LAUNCH_2D (0x00100000 + 0x80)
77
78#define COMMAND_3D (0x00200000 + 0x120)
79
80/* register bitfields (not all, only as needed) */
81
82#define BIT(x) (1UL << (x))
83
84/* COMMAND_2D reg. values */
85#define TDFX_ROP_COPY 0xcc // src
86#define TDFX_ROP_INVERT 0x55 // NOT dst
87#define TDFX_ROP_XOR 0x66 // src XOR dst
88
89#define AUTOINC_DSTX BIT(10)
90#define AUTOINC_DSTY BIT(11)
91#define COMMAND_2D_FILLRECT 0x05
92#define COMMAND_2D_S2S_BITBLT 0x01 // screen to screen
93#define COMMAND_2D_H2S_BITBLT 0x03 // host to screen
94
95#define COMMAND_3D_NOP 0x00
96#define STATUS_RETRACE BIT(6)
97#define STATUS_BUSY BIT(9)
98#define MISCINIT1_CLUT_INV BIT(0)
99#define MISCINIT1_2DBLOCK_DIS BIT(15)
100#define DRAMINIT0_SGRAM_NUM BIT(26)
101#define DRAMINIT0_SGRAM_TYPE BIT(27)
102#define DRAMINIT1_MEM_SDRAM BIT(30)
103#define VGAINIT0_VGA_DISABLE BIT(0)
104#define VGAINIT0_EXT_TIMING BIT(1)
105#define VGAINIT0_8BIT_DAC BIT(2)
106#define VGAINIT0_EXT_ENABLE BIT(6)
107#define VGAINIT0_WAKEUP_3C3 BIT(8)
108#define VGAINIT0_LEGACY_DISABLE BIT(9)
109#define VGAINIT0_ALT_READBACK BIT(10)
110#define VGAINIT0_FAST_BLINK BIT(11)
111#define VGAINIT0_EXTSHIFTOUT BIT(12)
112#define VGAINIT0_DECODE_3C6 BIT(13)
113#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22)
114#define VGAINIT1_MASK 0x1fffff
115#define VIDCFG_VIDPROC_ENABLE BIT(0)
116#define VIDCFG_CURS_X11 BIT(1)
117#define VIDCFG_INTERLACE BIT(3)
118#define VIDCFG_HALF_MODE BIT(4)
119#define VIDCFG_DESK_ENABLE BIT(7)
120#define VIDCFG_CLUT_BYPASS BIT(10)
121#define VIDCFG_2X BIT(26)
122#define VIDCFG_HWCURSOR_ENABLE BIT(27)
123#define VIDCFG_PIXFMT_SHIFT 18
124#define DACMODE_2X BIT(0)
125
126/* VGA rubbish, need to change this for multihead support */
127#define MISC_W 0x3c2
128#define MISC_R 0x3cc
129#define SEQ_I 0x3c4
130#define SEQ_D 0x3c5
131#define CRT_I 0x3d4
132#define CRT_D 0x3d5
133#define ATT_IW 0x3c0
134#define IS1_R 0x3da
135#define GRA_I 0x3ce
136#define GRA_D 0x3cf
137
138#ifdef __KERNEL__
139
140struct banshee_reg {
141 /* VGA rubbish */
142 unsigned char att[21];
143 unsigned char crt[25];
144 unsigned char gra[ 9];
145 unsigned char misc[1];
146 unsigned char seq[ 5];
147
148 /* Banshee extensions */
149 unsigned char ext[2];
150 unsigned long vidcfg;
151 unsigned long vidpll;
152 unsigned long mempll;
153 unsigned long gfxpll;
154 unsigned long dacmode;
155 unsigned long vgainit0;
156 unsigned long vgainit1;
157 unsigned long screensize;
158 unsigned long stride;
159 unsigned long cursloc;
160 unsigned long curspataddr;
161 unsigned long cursc0;
162 unsigned long cursc1;
163 unsigned long startaddr;
164 unsigned long clip0min;
165 unsigned long clip0max;
166 unsigned long clip1min;
167 unsigned long clip1max;
168 unsigned long srcbase;
169 unsigned long dstbase;
170 unsigned long miscinit0;
171};
172
173struct tdfx_par {
174 u32 max_pixclock;
175
176 void __iomem *regbase_virt;
177 unsigned long iobase;
178 u32 baseline;
179
180 struct {
181 int w,u,d;
182 unsigned long enable,disable;
183 struct timer_list timer;
184 } hwcursor;
185
186 spinlock_t DAClock;
187};
188
189#endif /* __KERNEL__ */
190
191#endif /* _TDFX_H */
192
diff --git a/include/video/tgafb.h b/include/video/tgafb.h
new file mode 100644
index 000000000000..be2b3e94e251
--- /dev/null
+++ b/include/video/tgafb.h
@@ -0,0 +1,238 @@
1/*
2 * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
5 *
6 * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive for
10 * more details.
11 */
12
13#ifndef TGAFB_H
14#define TGAFB_H
15
16/*
17 * TGA hardware description (minimal)
18 */
19
20#define TGA_TYPE_8PLANE 0
21#define TGA_TYPE_24PLANE 1
22#define TGA_TYPE_24PLUSZ 3
23
24/*
25 * Offsets within Memory Space
26 */
27
28#define TGA_ROM_OFFSET 0x0000000
29#define TGA_REGS_OFFSET 0x0100000
30#define TGA_8PLANE_FB_OFFSET 0x0200000
31#define TGA_24PLANE_FB_OFFSET 0x0804000
32#define TGA_24PLUSZ_FB_OFFSET 0x1004000
33
34#define TGA_FOREGROUND_REG 0x0020
35#define TGA_BACKGROUND_REG 0x0024
36#define TGA_PLANEMASK_REG 0x0028
37#define TGA_PIXELMASK_ONESHOT_REG 0x002c
38#define TGA_MODE_REG 0x0030
39#define TGA_RASTEROP_REG 0x0034
40#define TGA_PIXELSHIFT_REG 0x0038
41#define TGA_DEEP_REG 0x0050
42#define TGA_PIXELMASK_REG 0x005c
43#define TGA_CURSOR_BASE_REG 0x0060
44#define TGA_HORIZ_REG 0x0064
45#define TGA_VERT_REG 0x0068
46#define TGA_BASE_ADDR_REG 0x006c
47#define TGA_VALID_REG 0x0070
48#define TGA_CURSOR_XY_REG 0x0074
49#define TGA_INTR_STAT_REG 0x007c
50#define TGA_DATA_REG 0x0080
51#define TGA_RAMDAC_SETUP_REG 0x00c0
52#define TGA_BLOCK_COLOR0_REG 0x0140
53#define TGA_BLOCK_COLOR1_REG 0x0144
54#define TGA_BLOCK_COLOR2_REG 0x0148
55#define TGA_BLOCK_COLOR3_REG 0x014c
56#define TGA_BLOCK_COLOR4_REG 0x0150
57#define TGA_BLOCK_COLOR5_REG 0x0154
58#define TGA_BLOCK_COLOR6_REG 0x0158
59#define TGA_BLOCK_COLOR7_REG 0x015c
60#define TGA_COPY64_SRC 0x0160
61#define TGA_COPY64_DST 0x0164
62#define TGA_CLOCK_REG 0x01e8
63#define TGA_RAMDAC_REG 0x01f0
64#define TGA_CMD_STAT_REG 0x01f8
65
66
67/*
68 * Useful defines for managing the registers
69 */
70
71#define TGA_HORIZ_ODD 0x80000000
72#define TGA_HORIZ_POLARITY 0x40000000
73#define TGA_HORIZ_ACT_MSB 0x30000000
74#define TGA_HORIZ_BP 0x0fe00000
75#define TGA_HORIZ_SYNC 0x001fc000
76#define TGA_HORIZ_FP 0x00007c00
77#define TGA_HORIZ_ACT_LSB 0x000001ff
78
79#define TGA_VERT_SE 0x80000000
80#define TGA_VERT_POLARITY 0x40000000
81#define TGA_VERT_RESERVED 0x30000000
82#define TGA_VERT_BP 0x0fc00000
83#define TGA_VERT_SYNC 0x003f0000
84#define TGA_VERT_FP 0x0000f800
85#define TGA_VERT_ACTIVE 0x000007ff
86
87#define TGA_VALID_VIDEO 0x01
88#define TGA_VALID_BLANK 0x02
89#define TGA_VALID_CURSOR 0x04
90
91#define TGA_MODE_SBM_8BPP 0x000
92#define TGA_MODE_SBM_24BPP 0x300
93
94#define TGA_MODE_SIMPLE 0x00
95#define TGA_MODE_SIMPLEZ 0x10
96#define TGA_MODE_OPAQUE_STIPPLE 0x01
97#define TGA_MODE_OPAQUE_FILL 0x21
98#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
99#define TGA_MODE_TRANSPARENT_FILL 0x23
100#define TGA_MODE_BLOCK_STIPPLE 0x0d
101#define TGA_MODE_BLOCK_FILL 0x2d
102#define TGA_MODE_COPY 0x07
103#define TGA_MODE_DMA_READ_COPY_ND 0x17
104#define TGA_MODE_DMA_READ_COPY_D 0x37
105#define TGA_MODE_DMA_WRITE_COPY 0x1f
106
107
108/*
109 * Useful defines for managing the ICS1562 PLL clock
110 */
111
112#define TGA_PLL_BASE_FREQ 14318 /* .18 */
113#define TGA_PLL_MAX_FREQ 230000
114
115
116/*
117 * Useful defines for managing the BT485 on the 8-plane TGA
118 */
119
120#define BT485_READ_BIT 0x01
121#define BT485_WRITE_BIT 0x00
122
123#define BT485_ADDR_PAL_WRITE 0x00
124#define BT485_DATA_PAL 0x02
125#define BT485_PIXEL_MASK 0x04
126#define BT485_ADDR_PAL_READ 0x06
127#define BT485_ADDR_CUR_WRITE 0x08
128#define BT485_DATA_CUR 0x0a
129#define BT485_CMD_0 0x0c
130#define BT485_ADDR_CUR_READ 0x0e
131#define BT485_CMD_1 0x10
132#define BT485_CMD_2 0x12
133#define BT485_STATUS 0x14
134#define BT485_CMD_3 0x14
135#define BT485_CUR_RAM 0x16
136#define BT485_CUR_LOW_X 0x18
137#define BT485_CUR_HIGH_X 0x1a
138#define BT485_CUR_LOW_Y 0x1c
139#define BT485_CUR_HIGH_Y 0x1e
140
141
142/*
143 * Useful defines for managing the BT463 on the 24-plane TGAs
144 */
145
146#define BT463_ADDR_LO 0x0
147#define BT463_ADDR_HI 0x1
148#define BT463_REG_ACC 0x2
149#define BT463_PALETTE 0x3
150
151#define BT463_CUR_CLR_0 0x0100
152#define BT463_CUR_CLR_1 0x0101
153
154#define BT463_CMD_REG_0 0x0201
155#define BT463_CMD_REG_1 0x0202
156#define BT463_CMD_REG_2 0x0203
157
158#define BT463_READ_MASK_0 0x0205
159#define BT463_READ_MASK_1 0x0206
160#define BT463_READ_MASK_2 0x0207
161#define BT463_READ_MASK_3 0x0208
162
163#define BT463_BLINK_MASK_0 0x0209
164#define BT463_BLINK_MASK_1 0x020a
165#define BT463_BLINK_MASK_2 0x020b
166#define BT463_BLINK_MASK_3 0x020c
167
168#define BT463_WINDOW_TYPE_BASE 0x0300
169
170/*
171 * The framebuffer driver private data.
172 */
173
174struct tga_par {
175 /* PCI device. */
176 struct pci_dev *pdev;
177
178 /* Device dependent information. */
179 void __iomem *tga_mem_base;
180 void __iomem *tga_fb_base;
181 void __iomem *tga_regs_base;
182 u8 tga_type; /* TGA_TYPE_XXX */
183 u8 tga_chip_rev; /* dc21030 revision */
184
185 /* Remember blank mode. */
186 u8 vesa_blanked;
187
188 /* Define the video mode. */
189 u32 xres, yres; /* resolution in pixels */
190 u32 htimings; /* horizontal timing register */
191 u32 vtimings; /* vertical timing register */
192 u32 pll_freq; /* pixclock in mhz */
193 u32 bits_per_pixel; /* bits per pixel */
194 u32 sync_on_green; /* set if sync is on green */
195};
196
197
198/*
199 * Macros for reading/writing TGA and RAMDAC registers
200 */
201
202static inline void
203TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
204{
205 writel(v, par->tga_regs_base +r);
206}
207
208static inline u32
209TGA_READ_REG(struct tga_par *par, u32 r)
210{
211 return readl(par->tga_regs_base +r);
212}
213
214static inline void
215BT485_WRITE(struct tga_par *par, u8 v, u8 r)
216{
217 TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
218 TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
219}
220
221static inline void
222BT463_LOAD_ADDR(struct tga_par *par, u16 a)
223{
224 TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
225 TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
226 TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
227 TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
228}
229
230static inline void
231BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
232{
233 BT463_LOAD_ADDR(par, a);
234 TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
235 TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
236}
237
238#endif /* TGAFB_H */
diff --git a/include/video/trident.h b/include/video/trident.h
new file mode 100644
index 000000000000..200be2551681
--- /dev/null
+++ b/include/video/trident.h
@@ -0,0 +1,175 @@
1
2#ifndef TRIDENTFB_DEBUG
3#define TRIDENTFB_DEBUG 0
4#endif
5
6#if TRIDENTFB_DEBUG
7#define debug(f,a...) printk("%s:" f, __FUNCTION__ , ## a);mdelay(1000);
8#else
9#define debug(f,a...)
10#endif
11
12#define output(f, a...) pr_info("tridentfb: " f, ## a)
13
14#define Kb (1024)
15#define Mb (Kb*Kb)
16
17/* PCI IDS of supported cards temporarily here */
18
19#define CYBER9320 0x9320
20#define CYBER9388 0x9388
21#define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
22#define CYBER9385 0x9385 /* ditto */
23#define CYBER9397 0x9397
24#define CYBER9397DVD 0x939A
25#define CYBER9520 0x9520
26#define CYBER9525DVD 0x9525
27#define TGUI9660 0x9660
28#define IMAGE975 0x9750
29#define IMAGE985 0x9850
30#define BLADE3D 0x9880
31#define CYBERBLADEE4 0x9540
32#define CYBERBLADEi7 0x8400
33#define CYBERBLADEi7D 0x8420
34#define CYBERBLADEi1 0x8500
35#define CYBERBLADEi1D 0x8520
36#define CYBERBLADEAi1 0x8600
37#define CYBERBLADEAi1D 0x8620
38#define CYBERBLADEXPAi1 0x8820
39#define CYBERBLADEXPm8 0x9910
40#define CYBERBLADEXPm16 0x9930
41
42/* acceleration families */
43#define IMAGE 0
44#define BLADE 1
45#define XP 2
46
47#define is_image(id)
48#define is_xp(id) ((id == CYBERBLADEXPAi1) ||\
49 (id == CYBERBLADEXPm8) ||\
50 (id == CYBERBLADEXPm16))
51
52#define is_blade(id) ((id == BLADE3D) ||\
53 (id == CYBERBLADEE4) ||\
54 (id == CYBERBLADEi7) ||\
55 (id == CYBERBLADEi7D) ||\
56 (id == CYBERBLADEi1) ||\
57 (id == CYBERBLADEi1D) ||\
58 (id == CYBERBLADEAi1) ||\
59 (id == CYBERBLADEAi1D))
60
61/* these defines are for 'lcd' variable */
62#define LCD_STRETCH 0
63#define LCD_CENTER 1
64#define LCD_BIOS 2
65
66/* display types */
67#define DISPLAY_CRT 0
68#define DISPLAY_FP 1
69
70#define flatpanel (displaytype == DISPLAY_FP)
71
72/* General Registers */
73#define SPR 0x1F /* Software Programming Register (videoram) */
74
75/* 3C4 */
76#define RevisionID 0x09
77#define OldOrNew 0x0B
78#define ConfPort1 0x0C
79#define ConfPort2 0x0C
80#define NewMode2 0x0D
81#define NewMode1 0x0E
82#define Protection 0x11
83#define MCLKLow 0x16
84#define MCLKHigh 0x17
85#define ClockLow 0x18
86#define ClockHigh 0x19
87#define SSetup 0x20
88#define SKey 0x37
89#define SPKey 0x57
90
91/* 0x3x4 */
92#define CRTHTotal 0x00
93#define CRTHDispEnd 0x01
94#define CRTHBlankStart 0x02
95#define CRTHBlankEnd 0x03
96#define CRTHSyncStart 0x04
97#define CRTHSyncEnd 0x05
98
99#define CRTVTotal 0x06
100#define CRTVDispEnd 0x12
101#define CRTVBlankStart 0x15
102#define CRTVBlankEnd 0x16
103#define CRTVSyncStart 0x10
104#define CRTVSyncEnd 0x11
105
106#define CRTOverflow 0x07
107#define CRTPRowScan 0x08
108#define CRTMaxScanLine 0x09
109#define CRTModeControl 0x17
110#define CRTLineCompare 0x18
111
112/* 3x4 */
113#define StartAddrHigh 0x0C
114#define StartAddrLow 0x0D
115#define Offset 0x13
116#define Underline 0x14
117#define CRTCMode 0x17
118#define CRTCModuleTest 0x1E
119#define FIFOControl 0x20
120#define LinearAddReg 0x21
121#define DRAMTiming 0x23
122#define New32 0x23
123#define RAMDACTiming 0x25
124#define CRTHiOrd 0x27
125#define AddColReg 0x29
126#define InterfaceSel 0x2A
127#define HorizOverflow 0x2B
128#define GETest 0x2D
129#define Performance 0x2F
130#define GraphEngReg 0x36
131#define I2C 0x37
132#define PixelBusReg 0x38
133#define PCIReg 0x39
134#define DRAMControl 0x3A
135#define MiscContReg 0x3C
136#define CursorXLow 0x40
137#define CursorXHigh 0x41
138#define CursorYLow 0x42
139#define CursorYHigh 0x43
140#define CursorLocLow 0x44
141#define CursorLocHigh 0x45
142#define CursorXOffset 0x46
143#define CursorYOffset 0x47
144#define CursorFG1 0x48
145#define CursorFG2 0x49
146#define CursorFG3 0x4A
147#define CursorFG4 0x4B
148#define CursorBG1 0x4C
149#define CursorBG2 0x4D
150#define CursorBG3 0x4E
151#define CursorBG4 0x4F
152#define CursorControl 0x50
153#define PCIRetry 0x55
154#define PreEndControl 0x56
155#define PreEndFetch 0x57
156#define PCIMaster 0x60
157#define Enhancement0 0x62
158#define NewEDO 0x64
159#define TVinterface 0xC0
160#define TVMode 0xC1
161#define ClockControl 0xCF
162
163
164/* 3CE */
165#define MiscExtFunc 0x0F
166#define PowerStatus 0x23
167#define MiscIntContReg 0x2F
168#define CyberControl 0x30
169#define CyberEnhance 0x31
170#define FPConfig 0x33
171#define VertStretch 0x52
172#define HorStretch 0x53
173#define BiosMode 0x5c
174#define BiosReg 0x5d
175
diff --git a/include/video/tx3912.h b/include/video/tx3912.h
new file mode 100644
index 000000000000..6b6d006038c2
--- /dev/null
+++ b/include/video/tx3912.h
@@ -0,0 +1,62 @@
1/*
2 * linux/include/video/tx3912.h
3 *
4 * Copyright (C) 2001 Steven Hill (sjhill@realitydiluted.com)
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Includes for TMPR3912/05 and PR31700 LCD controller registers
11 */
12#include <asm/tx3912.h>
13
14#define VidCtrl1 REG_AT(0x028)
15#define VidCtrl2 REG_AT(0x02C)
16#define VidCtrl3 REG_AT(0x030)
17#define VidCtrl4 REG_AT(0x034)
18#define VidCtrl5 REG_AT(0x038)
19#define VidCtrl6 REG_AT(0x03C)
20#define VidCtrl7 REG_AT(0x040)
21#define VidCtrl8 REG_AT(0x044)
22#define VidCtrl9 REG_AT(0x048)
23#define VidCtrl10 REG_AT(0x04C)
24#define VidCtrl11 REG_AT(0x050)
25#define VidCtrl12 REG_AT(0x054)
26#define VidCtrl13 REG_AT(0x058)
27#define VidCtrl14 REG_AT(0x05C)
28
29/* Video Control 1 Register */
30#define LINECNT 0xffc00000
31#define LINECNT_SHIFT 22
32#define LOADDLY BIT(21)
33#define BAUDVAL (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16))
34#define BAUDVAL_SHIFT 16
35#define VIDDONEVAL (BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9))
36#define VIDDONEVAL_SHIFT 9
37#define ENFREEZEFRAME BIT(8)
38#define TX3912_VIDCTRL1_BITSEL_MASK 0x000000c0
39#define TX3912_VIDCTRL1_2BIT_GRAY 0x00000040
40#define TX3912_VIDCTRL1_4BIT_GRAY 0x00000080
41#define TX3912_VIDCTRL1_8BIT_COLOR 0x000000c0
42#define BITSEL_SHIFT 6
43#define DISPSPLIT BIT(5)
44#define DISP8 BIT(4)
45#define DFMODE BIT(3)
46#define INVVID BIT(2)
47#define DISPON BIT(1)
48#define ENVID BIT(0)
49
50/* Video Control 2 Register */
51#define VIDRATE_MASK 0xffc00000
52#define VIDRATE_SHIFT 22
53#define HORZVAL_MASK 0x001ff000
54#define HORZVAL_SHIFT 12
55#define LINEVAL_MASK 0x000001ff
56
57/* Video Control 3 Register */
58#define TX3912_VIDCTRL3_VIDBANK_MASK 0xfff00000
59#define TX3912_VIDCTRL3_VIDBASEHI_MASK 0x000ffff0
60
61/* Video Control 4 Register */
62#define TX3912_VIDCTRL4_VIDBASELO_MASK 0x000ffff0
diff --git a/include/video/vga.h b/include/video/vga.h
new file mode 100644
index 000000000000..700d6c8eb736
--- /dev/null
+++ b/include/video/vga.h
@@ -0,0 +1,482 @@
1/*
2 * linux/include/video/vga.h -- standard VGA chipset interaction
3 *
4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
5 *
6 * Copyright history from vga16fb.c:
7 * Copyright 1999 Ben Pfaff and Petr Vandrovec
8 * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
9 * Based on VESA framebuffer (c) 1998 Gerd Knorr
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 */
16
17#ifndef __linux_video_vga_h__
18#define __linux_video_vga_h__
19
20#include <linux/config.h>
21#include <linux/types.h>
22#include <asm/io.h>
23#ifndef CONFIG_AMIGA
24#include <asm/vga.h>
25#else
26/*
27 * FIXME
28 * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space
29 * for MMIO accesses. This should make cirrusfb work again on Amiga
30 */
31#undef inb_p
32#undef inw_p
33#undef outb_p
34#undef outw
35#undef readb
36#undef writeb
37#undef writew
38#define inb_p(port) 0
39#define inw_p(port) 0
40#define outb_p(port, val) do { } while (0)
41#define outw(port, val) do { } while (0)
42#define readb z_readb
43#define writeb z_writeb
44#define writew z_writew
45#endif
46#include <asm/byteorder.h>
47
48
49/* Some of the code below is taken from SVGAlib. The original,
50 unmodified copyright notice for that code is below. */
51/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
52/* */
53/* This library is free software; you can redistribute it and/or */
54/* modify it without any restrictions. This library is distributed */
55/* in the hope that it will be useful, but without any warranty. */
56
57/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
58/* partially copyrighted (C) 1993 by Hartmut Schirmer */
59
60/* VGA data register ports */
61#define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
62#define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
63#define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
64#define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
65#define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
66#define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
67#define VGA_MIS_R 0x3CC /* Misc Output Read Register */
68#define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
69#define VGA_FTC_R 0x3CA /* Feature Control Read Register */
70#define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
71#define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
72#define VGA_PEL_D 0x3C9 /* PEL Data Register */
73#define VGA_PEL_MSK 0x3C6 /* PEL mask register */
74
75/* EGA-specific registers */
76#define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */
77#define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */
78
79/* VGA index register ports */
80#define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
81#define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
82#define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
83#define VGA_GFX_I 0x3CE /* Graphics Controller Index */
84#define VGA_SEQ_I 0x3C4 /* Sequencer Index */
85#define VGA_PEL_IW 0x3C8 /* PEL Write Index */
86#define VGA_PEL_IR 0x3C7 /* PEL Read Index */
87
88/* standard VGA indexes max counts */
89#define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
90#define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */
91#define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */
92#define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */
93#define VGA_MIS_C 0x01 /* Number of Misc Output Register */
94
95/* VGA misc register bit masks */
96#define VGA_MIS_COLOR 0x01
97#define VGA_MIS_ENB_MEM_ACCESS 0x02
98#define VGA_MIS_DCLK_28322_720 0x04
99#define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08)
100#define VGA_MIS_SEL_HIGH_PAGE 0x20
101
102/* VGA CRT controller register indices */
103#define VGA_CRTC_H_TOTAL 0
104#define VGA_CRTC_H_DISP 1
105#define VGA_CRTC_H_BLANK_START 2
106#define VGA_CRTC_H_BLANK_END 3
107#define VGA_CRTC_H_SYNC_START 4
108#define VGA_CRTC_H_SYNC_END 5
109#define VGA_CRTC_V_TOTAL 6
110#define VGA_CRTC_OVERFLOW 7
111#define VGA_CRTC_PRESET_ROW 8
112#define VGA_CRTC_MAX_SCAN 9
113#define VGA_CRTC_CURSOR_START 0x0A
114#define VGA_CRTC_CURSOR_END 0x0B
115#define VGA_CRTC_START_HI 0x0C
116#define VGA_CRTC_START_LO 0x0D
117#define VGA_CRTC_CURSOR_HI 0x0E
118#define VGA_CRTC_CURSOR_LO 0x0F
119#define VGA_CRTC_V_SYNC_START 0x10
120#define VGA_CRTC_V_SYNC_END 0x11
121#define VGA_CRTC_V_DISP_END 0x12
122#define VGA_CRTC_OFFSET 0x13
123#define VGA_CRTC_UNDERLINE 0x14
124#define VGA_CRTC_V_BLANK_START 0x15
125#define VGA_CRTC_V_BLANK_END 0x16
126#define VGA_CRTC_MODE 0x17
127#define VGA_CRTC_LINE_COMPARE 0x18
128#define VGA_CRTC_REGS VGA_CRT_C
129
130/* VGA CRT controller bit masks */
131#define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
132#define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
133
134/* VGA attribute controller register indices */
135#define VGA_ATC_PALETTE0 0x00
136#define VGA_ATC_PALETTE1 0x01
137#define VGA_ATC_PALETTE2 0x02
138#define VGA_ATC_PALETTE3 0x03
139#define VGA_ATC_PALETTE4 0x04
140#define VGA_ATC_PALETTE5 0x05
141#define VGA_ATC_PALETTE6 0x06
142#define VGA_ATC_PALETTE7 0x07
143#define VGA_ATC_PALETTE8 0x08
144#define VGA_ATC_PALETTE9 0x09
145#define VGA_ATC_PALETTEA 0x0A
146#define VGA_ATC_PALETTEB 0x0B
147#define VGA_ATC_PALETTEC 0x0C
148#define VGA_ATC_PALETTED 0x0D
149#define VGA_ATC_PALETTEE 0x0E
150#define VGA_ATC_PALETTEF 0x0F
151#define VGA_ATC_MODE 0x10
152#define VGA_ATC_OVERSCAN 0x11
153#define VGA_ATC_PLANE_ENABLE 0x12
154#define VGA_ATC_PEL 0x13
155#define VGA_ATC_COLOR_PAGE 0x14
156
157#define VGA_AR_ENABLE_DISPLAY 0x20
158
159/* VGA sequencer register indices */
160#define VGA_SEQ_RESET 0x00
161#define VGA_SEQ_CLOCK_MODE 0x01
162#define VGA_SEQ_PLANE_WRITE 0x02
163#define VGA_SEQ_CHARACTER_MAP 0x03
164#define VGA_SEQ_MEMORY_MODE 0x04
165
166/* VGA sequencer register bit masks */
167#define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
168#define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
169#define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
170#define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */
171#define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */
172#define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
173
174/* VGA graphics controller register indices */
175#define VGA_GFX_SR_VALUE 0x00
176#define VGA_GFX_SR_ENABLE 0x01
177#define VGA_GFX_COMPARE_VALUE 0x02
178#define VGA_GFX_DATA_ROTATE 0x03
179#define VGA_GFX_PLANE_READ 0x04
180#define VGA_GFX_MODE 0x05
181#define VGA_GFX_MISC 0x06
182#define VGA_GFX_COMPARE_MASK 0x07
183#define VGA_GFX_BIT_MASK 0x08
184
185/* VGA graphics controller bit masks */
186#define VGA_GR06_GRAPHICS_MODE 0x01
187
188/* macro for composing an 8-bit VGA register index and value
189 * into a single 16-bit quantity */
190#define VGA_OUT16VAL(v, r) (((v) << 8) | (r))
191
192/* decide whether we should enable the faster 16-bit VGA register writes */
193#ifdef __LITTLE_ENDIAN
194#define VGA_OUTW_WRITE
195#endif
196
197/* VGA State Save and Restore */
198#define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */
199#define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */
200#define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */
201#define VGA_SAVE_FONTS 7 /* save/restore all fonts */
202#define VGA_SAVE_MODE 8 /* save/restore video mode */
203#define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */
204
205struct vgastate {
206 void __iomem *vgabase; /* mmio base, if supported */
207 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */
208 __u32 memsize; /* VGA window size, 0 for default 64K */
209 __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */
210 __u32 depth; /* current fb depth, not important */
211 __u32 num_attr; /* number of att registers, 0 for default */
212 __u32 num_crtc; /* number of crt registers, 0 for default */
213 __u32 num_gfx; /* number of gfx registers, 0 for default */
214 __u32 num_seq; /* number of seq registers, 0 for default */
215 void *vidstate;
216};
217
218extern int save_vga(struct vgastate *state);
219extern int restore_vga(struct vgastate *state);
220
221/*
222 * generic VGA port read/write
223 */
224
225static inline unsigned char vga_io_r (unsigned short port)
226{
227 return inb_p(port);
228}
229
230static inline void vga_io_w (unsigned short port, unsigned char val)
231{
232 outb_p(val, port);
233}
234
235static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
236 unsigned char val)
237{
238 outw(VGA_OUT16VAL (val, reg), port);
239}
240
241static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port)
242{
243 return readb (regbase + port);
244}
245
246static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val)
247{
248 writeb (val, regbase + port);
249}
250
251static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port,
252 unsigned char reg, unsigned char val)
253{
254 writew (VGA_OUT16VAL (val, reg), regbase + port);
255}
256
257static inline unsigned char vga_r (void __iomem *regbase, unsigned short port)
258{
259 if (regbase)
260 return vga_mm_r (regbase, port);
261 else
262 return vga_io_r (port);
263}
264
265static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val)
266{
267 if (regbase)
268 vga_mm_w (regbase, port, val);
269 else
270 vga_io_w (port, val);
271}
272
273
274static inline void vga_w_fast (void __iomem *regbase, unsigned short port,
275 unsigned char reg, unsigned char val)
276{
277 if (regbase)
278 vga_mm_w_fast (regbase, port, reg, val);
279 else
280 vga_io_w_fast (port, reg, val);
281}
282
283
284/*
285 * VGA CRTC register read/write
286 */
287
288static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg)
289{
290 vga_w (regbase, VGA_CRT_IC, reg);
291 return vga_r (regbase, VGA_CRT_DC);
292}
293
294static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
295{
296#ifdef VGA_OUTW_WRITE
297 vga_w_fast (regbase, VGA_CRT_IC, reg, val);
298#else
299 vga_w (regbase, VGA_CRT_IC, reg);
300 vga_w (regbase, VGA_CRT_DC, val);
301#endif /* VGA_OUTW_WRITE */
302}
303
304static inline unsigned char vga_io_rcrt (unsigned char reg)
305{
306 vga_io_w (VGA_CRT_IC, reg);
307 return vga_io_r (VGA_CRT_DC);
308}
309
310static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
311{
312#ifdef VGA_OUTW_WRITE
313 vga_io_w_fast (VGA_CRT_IC, reg, val);
314#else
315 vga_io_w (VGA_CRT_IC, reg);
316 vga_io_w (VGA_CRT_DC, val);
317#endif /* VGA_OUTW_WRITE */
318}
319
320static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg)
321{
322 vga_mm_w (regbase, VGA_CRT_IC, reg);
323 return vga_mm_r (regbase, VGA_CRT_DC);
324}
325
326static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
327{
328#ifdef VGA_OUTW_WRITE
329 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
330#else
331 vga_mm_w (regbase, VGA_CRT_IC, reg);
332 vga_mm_w (regbase, VGA_CRT_DC, val);
333#endif /* VGA_OUTW_WRITE */
334}
335
336
337/*
338 * VGA sequencer register read/write
339 */
340
341static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg)
342{
343 vga_w (regbase, VGA_SEQ_I, reg);
344 return vga_r (regbase, VGA_SEQ_D);
345}
346
347static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
348{
349#ifdef VGA_OUTW_WRITE
350 vga_w_fast (regbase, VGA_SEQ_I, reg, val);
351#else
352 vga_w (regbase, VGA_SEQ_I, reg);
353 vga_w (regbase, VGA_SEQ_D, val);
354#endif /* VGA_OUTW_WRITE */
355}
356
357static inline unsigned char vga_io_rseq (unsigned char reg)
358{
359 vga_io_w (VGA_SEQ_I, reg);
360 return vga_io_r (VGA_SEQ_D);
361}
362
363static inline void vga_io_wseq (unsigned char reg, unsigned char val)
364{
365#ifdef VGA_OUTW_WRITE
366 vga_io_w_fast (VGA_SEQ_I, reg, val);
367#else
368 vga_io_w (VGA_SEQ_I, reg);
369 vga_io_w (VGA_SEQ_D, val);
370#endif /* VGA_OUTW_WRITE */
371}
372
373static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg)
374{
375 vga_mm_w (regbase, VGA_SEQ_I, reg);
376 return vga_mm_r (regbase, VGA_SEQ_D);
377}
378
379static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
380{
381#ifdef VGA_OUTW_WRITE
382 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
383#else
384 vga_mm_w (regbase, VGA_SEQ_I, reg);
385 vga_mm_w (regbase, VGA_SEQ_D, val);
386#endif /* VGA_OUTW_WRITE */
387}
388
389/*
390 * VGA graphics controller register read/write
391 */
392
393static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg)
394{
395 vga_w (regbase, VGA_GFX_I, reg);
396 return vga_r (regbase, VGA_GFX_D);
397}
398
399static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
400{
401#ifdef VGA_OUTW_WRITE
402 vga_w_fast (regbase, VGA_GFX_I, reg, val);
403#else
404 vga_w (regbase, VGA_GFX_I, reg);
405 vga_w (regbase, VGA_GFX_D, val);
406#endif /* VGA_OUTW_WRITE */
407}
408
409static inline unsigned char vga_io_rgfx (unsigned char reg)
410{
411 vga_io_w (VGA_GFX_I, reg);
412 return vga_io_r (VGA_GFX_D);
413}
414
415static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
416{
417#ifdef VGA_OUTW_WRITE
418 vga_io_w_fast (VGA_GFX_I, reg, val);
419#else
420 vga_io_w (VGA_GFX_I, reg);
421 vga_io_w (VGA_GFX_D, val);
422#endif /* VGA_OUTW_WRITE */
423}
424
425static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg)
426{
427 vga_mm_w (regbase, VGA_GFX_I, reg);
428 return vga_mm_r (regbase, VGA_GFX_D);
429}
430
431static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
432{
433#ifdef VGA_OUTW_WRITE
434 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
435#else
436 vga_mm_w (regbase, VGA_GFX_I, reg);
437 vga_mm_w (regbase, VGA_GFX_D, val);
438#endif /* VGA_OUTW_WRITE */
439}
440
441
442/*
443 * VGA attribute controller register read/write
444 */
445
446static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg)
447{
448 vga_w (regbase, VGA_ATT_IW, reg);
449 return vga_r (regbase, VGA_ATT_R);
450}
451
452static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
453{
454 vga_w (regbase, VGA_ATT_IW, reg);
455 vga_w (regbase, VGA_ATT_W, val);
456}
457
458static inline unsigned char vga_io_rattr (unsigned char reg)
459{
460 vga_io_w (VGA_ATT_IW, reg);
461 return vga_io_r (VGA_ATT_R);
462}
463
464static inline void vga_io_wattr (unsigned char reg, unsigned char val)
465{
466 vga_io_w (VGA_ATT_IW, reg);
467 vga_io_w (VGA_ATT_W, val);
468}
469
470static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg)
471{
472 vga_mm_w (regbase, VGA_ATT_IW, reg);
473 return vga_mm_r (regbase, VGA_ATT_R);
474}
475
476static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
477{
478 vga_mm_w (regbase, VGA_ATT_IW, reg);
479 vga_mm_w (regbase, VGA_ATT_W, val);
480}
481
482#endif /* __linux_video_vga_h__ */
diff --git a/include/video/w100fb.h b/include/video/w100fb.h
new file mode 100644
index 000000000000..bd548c2b47c4
--- /dev/null
+++ b/include/video/w100fb.h
@@ -0,0 +1,21 @@
1/*
2 * Support for the w100 frame buffer.
3 *
4 * Copyright (c) 2004 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * This structure describes the machine which we are running on.
13 * It is set by machine specific code and used in the probe routine
14 * of drivers/video/w100fb.c
15 */
16
17struct w100fb_mach_info {
18 void (*w100fb_ssp_send)(u8 adrs, u8 data);
19 int comadj;
20 int phadadj;
21};