diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/media/saa7146.h |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/media/saa7146.h')
-rw-r--r-- | include/media/saa7146.h | 452 |
1 files changed, 452 insertions, 0 deletions
diff --git a/include/media/saa7146.h b/include/media/saa7146.h new file mode 100644 index 000000000000..3dfb8d670eb7 --- /dev/null +++ b/include/media/saa7146.h | |||
@@ -0,0 +1,452 @@ | |||
1 | #ifndef __SAA7146__ | ||
2 | #define __SAA7146__ | ||
3 | |||
4 | #include <linux/version.h> /* for version macros */ | ||
5 | #include <linux/module.h> /* for module-version */ | ||
6 | #include <linux/delay.h> /* for delay-stuff */ | ||
7 | #include <linux/slab.h> /* for kmalloc/kfree */ | ||
8 | #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */ | ||
9 | #include <linux/init.h> /* for "__init" */ | ||
10 | #include <linux/interrupt.h> /* for IMMEDIATE_BH */ | ||
11 | #include <linux/kmod.h> /* for kernel module loader */ | ||
12 | #include <linux/i2c.h> /* for i2c subsystem */ | ||
13 | #include <asm/io.h> /* for accessing devices */ | ||
14 | #include <linux/stringify.h> | ||
15 | #include <linux/vmalloc.h> /* for vmalloc() */ | ||
16 | #include <linux/mm.h> /* for vmalloc_to_page() */ | ||
17 | |||
18 | /* ugly, but necessary to build the dvb stuff under 2.4. */ | ||
19 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,51) | ||
20 | #include "dvb_functions.h" | ||
21 | #endif | ||
22 | |||
23 | #define SAA7146_VERSION_CODE KERNEL_VERSION(0,5,0) | ||
24 | |||
25 | #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr))) | ||
26 | #define saa7146_read(sxy,adr) readl(sxy->mem+(adr)) | ||
27 | |||
28 | extern unsigned int saa7146_debug; | ||
29 | |||
30 | //#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),__stringify(KBUILD_MODNAME),__FUNCTION__) | ||
31 | |||
32 | #ifndef DEBUG_VARIABLE | ||
33 | #define DEBUG_VARIABLE saa7146_debug | ||
34 | #endif | ||
35 | |||
36 | #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,51) | ||
37 | #define DEBUG_PROLOG printk("%s: %s(): ",__stringify(KBUILD_BASENAME),__FUNCTION__) | ||
38 | #define INFO(x) { printk("%s: ",__stringify(KBUILD_BASENAME)); printk x; } | ||
39 | #else | ||
40 | #define DEBUG_PROLOG printk("%s: %s(): ",__stringify(KBUILD_MODNAME),__FUNCTION__) | ||
41 | #define INFO(x) { printk("%s: ",__stringify(KBUILD_MODNAME)); printk x; } | ||
42 | #endif | ||
43 | |||
44 | #define ERR(x) { DEBUG_PROLOG; printk x; } | ||
45 | |||
46 | #define DEB_S(x) if (0!=(DEBUG_VARIABLE&0x01)) { DEBUG_PROLOG; printk x; } /* simple debug messages */ | ||
47 | #define DEB_D(x) if (0!=(DEBUG_VARIABLE&0x02)) { DEBUG_PROLOG; printk x; } /* more detailed debug messages */ | ||
48 | #define DEB_EE(x) if (0!=(DEBUG_VARIABLE&0x04)) { DEBUG_PROLOG; printk x; } /* print enter and exit of functions */ | ||
49 | #define DEB_I2C(x) if (0!=(DEBUG_VARIABLE&0x08)) { DEBUG_PROLOG; printk x; } /* i2c debug messages */ | ||
50 | #define DEB_VBI(x) if (0!=(DEBUG_VARIABLE&0x10)) { DEBUG_PROLOG; printk x; } /* vbi debug messages */ | ||
51 | #define DEB_INT(x) if (0!=(DEBUG_VARIABLE&0x20)) { DEBUG_PROLOG; printk x; } /* interrupt debug messages */ | ||
52 | #define DEB_CAP(x) if (0!=(DEBUG_VARIABLE&0x40)) { DEBUG_PROLOG; printk x; } /* capture debug messages */ | ||
53 | |||
54 | #define SAA7146_IER_DISABLE(x,y) \ | ||
55 | saa7146_write(x, IER, saa7146_read(x, IER) & ~(y)); | ||
56 | #define SAA7146_IER_ENABLE(x,y) \ | ||
57 | saa7146_write(x, IER, saa7146_read(x, IER) | (y)); | ||
58 | #define SAA7146_ISR_CLEAR(x,y) \ | ||
59 | saa7146_write(x, ISR, (y)); | ||
60 | |||
61 | struct saa7146_dev; | ||
62 | struct saa7146_extension; | ||
63 | struct saa7146_vv; | ||
64 | |||
65 | /* saa7146 page table */ | ||
66 | struct saa7146_pgtable { | ||
67 | unsigned int size; | ||
68 | u32 *cpu; | ||
69 | dma_addr_t dma; | ||
70 | /* used for offsets for u,v planes for planar capture modes */ | ||
71 | unsigned long offset; | ||
72 | /* used for custom pagetables (used for example by budget dvb cards) */ | ||
73 | struct scatterlist *slist; | ||
74 | }; | ||
75 | |||
76 | struct saa7146_pci_extension_data { | ||
77 | struct saa7146_extension *ext; | ||
78 | void *ext_priv; /* most likely a name string */ | ||
79 | }; | ||
80 | |||
81 | #define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \ | ||
82 | { \ | ||
83 | .vendor = PCI_VENDOR_ID_PHILIPS, \ | ||
84 | .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \ | ||
85 | .subvendor = x_vendor, \ | ||
86 | .subdevice = x_device, \ | ||
87 | .driver_data = (unsigned long)& x_var, \ | ||
88 | } | ||
89 | |||
90 | struct saa7146_extension | ||
91 | { | ||
92 | char name[32]; /* name of the device */ | ||
93 | #define SAA7146_USE_I2C_IRQ 0x1 | ||
94 | #define SAA7146_I2C_SHORT_DELAY 0x2 | ||
95 | int flags; | ||
96 | |||
97 | /* pairs of subvendor and subdevice ids for | ||
98 | supported devices, last entry 0xffff, 0xfff */ | ||
99 | struct module *module; | ||
100 | struct pci_driver driver; | ||
101 | struct pci_device_id *pci_tbl; | ||
102 | |||
103 | /* extension functions */ | ||
104 | int (*probe)(struct saa7146_dev *); | ||
105 | int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *); | ||
106 | int (*detach)(struct saa7146_dev*); | ||
107 | |||
108 | u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */ | ||
109 | void (*irq_func)(struct saa7146_dev*, u32* irq_mask); | ||
110 | }; | ||
111 | |||
112 | struct saa7146_dma | ||
113 | { | ||
114 | dma_addr_t dma_handle; | ||
115 | u32 *cpu_addr; | ||
116 | }; | ||
117 | |||
118 | struct saa7146_dev | ||
119 | { | ||
120 | struct module *module; | ||
121 | |||
122 | struct list_head item; | ||
123 | |||
124 | /* different device locks */ | ||
125 | spinlock_t slock; | ||
126 | struct semaphore lock; | ||
127 | |||
128 | unsigned char __iomem *mem; /* pointer to mapped IO memory */ | ||
129 | int revision; /* chip revision; needed for bug-workarounds*/ | ||
130 | |||
131 | /* pci-device & irq stuff*/ | ||
132 | char name[32]; | ||
133 | struct pci_dev *pci; | ||
134 | u32 int_todo; | ||
135 | spinlock_t int_slock; | ||
136 | |||
137 | /* extension handling */ | ||
138 | struct saa7146_extension *ext; /* indicates if handled by extension */ | ||
139 | void *ext_priv; /* pointer for extension private use (most likely some private data) */ | ||
140 | struct saa7146_ext_vv *ext_vv_data; | ||
141 | |||
142 | /* per device video/vbi informations (if available) */ | ||
143 | struct saa7146_vv *vv_data; | ||
144 | void (*vv_callback)(struct saa7146_dev *dev, unsigned long status); | ||
145 | |||
146 | /* i2c-stuff */ | ||
147 | struct semaphore i2c_lock; | ||
148 | u32 i2c_bitrate; | ||
149 | struct saa7146_dma d_i2c; /* pointer to i2c memory */ | ||
150 | wait_queue_head_t i2c_wq; | ||
151 | int i2c_op; | ||
152 | |||
153 | /* memories */ | ||
154 | struct saa7146_dma d_rps0; | ||
155 | struct saa7146_dma d_rps1; | ||
156 | }; | ||
157 | |||
158 | /* from saa7146_i2c.c */ | ||
159 | int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate); | ||
160 | int saa7146_i2c_transfer(struct saa7146_dev *saa, const struct i2c_msg *msgs, int num, int retries); | ||
161 | |||
162 | /* from saa7146_core.c */ | ||
163 | extern struct list_head saa7146_devices; | ||
164 | extern struct semaphore saa7146_devices_lock; | ||
165 | int saa7146_register_extension(struct saa7146_extension*); | ||
166 | int saa7146_unregister_extension(struct saa7146_extension*); | ||
167 | struct saa7146_format* format_by_fourcc(struct saa7146_dev *dev, int fourcc); | ||
168 | int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt); | ||
169 | void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt); | ||
170 | int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length ); | ||
171 | char *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt); | ||
172 | void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data); | ||
173 | int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop); | ||
174 | |||
175 | /* some memory sizes */ | ||
176 | #define SAA7146_I2C_MEM ( 1*PAGE_SIZE) | ||
177 | #define SAA7146_RPS_MEM ( 1*PAGE_SIZE) | ||
178 | |||
179 | /* some i2c constants */ | ||
180 | #define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */ | ||
181 | #define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */ | ||
182 | #define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */ | ||
183 | |||
184 | /* unsorted defines */ | ||
185 | #define ME1 0x0000000800 | ||
186 | #define PV1 0x0000000008 | ||
187 | |||
188 | /* gpio defines */ | ||
189 | #define SAA7146_GPIO_INPUT 0x00 | ||
190 | #define SAA7146_GPIO_IRQHI 0x10 | ||
191 | #define SAA7146_GPIO_IRQLO 0x20 | ||
192 | #define SAA7146_GPIO_IRQHL 0x30 | ||
193 | #define SAA7146_GPIO_OUTLO 0x40 | ||
194 | #define SAA7146_GPIO_OUTHI 0x50 | ||
195 | |||
196 | /* debi defines */ | ||
197 | #define DEBINOSWAP 0x000e0000 | ||
198 | |||
199 | /* define for the register programming sequencer (rps) */ | ||
200 | #define CMD_NOP 0x00000000 /* No operation */ | ||
201 | #define CMD_CLR_EVENT 0x00000000 /* Clear event */ | ||
202 | #define CMD_SET_EVENT 0x10000000 /* Set signal event */ | ||
203 | #define CMD_PAUSE 0x20000000 /* Pause */ | ||
204 | #define CMD_CHECK_LATE 0x30000000 /* Check late */ | ||
205 | #define CMD_UPLOAD 0x40000000 /* Upload */ | ||
206 | #define CMD_STOP 0x50000000 /* Stop */ | ||
207 | #define CMD_INTERRUPT 0x60000000 /* Interrupt */ | ||
208 | #define CMD_JUMP 0x80000000 /* Jump */ | ||
209 | #define CMD_WR_REG 0x90000000 /* Write (load) register */ | ||
210 | #define CMD_RD_REG 0xa0000000 /* Read (store) register */ | ||
211 | #define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */ | ||
212 | |||
213 | #define CMD_OAN MASK_27 | ||
214 | #define CMD_INV MASK_26 | ||
215 | #define CMD_SIG4 MASK_25 | ||
216 | #define CMD_SIG3 MASK_24 | ||
217 | #define CMD_SIG2 MASK_23 | ||
218 | #define CMD_SIG1 MASK_22 | ||
219 | #define CMD_SIG0 MASK_21 | ||
220 | #define CMD_O_FID_B MASK_14 | ||
221 | #define CMD_E_FID_B MASK_13 | ||
222 | #define CMD_O_FID_A MASK_12 | ||
223 | #define CMD_E_FID_A MASK_11 | ||
224 | |||
225 | /* some events and command modifiers for rps1 squarewave generator */ | ||
226 | #define EVT_HS (1<<15) // Source Line Threshold reached | ||
227 | #define EVT_VBI_B (1<<9) // VSYNC Event | ||
228 | #define RPS_OAN (1<<27) // 1: OR events, 0: AND events | ||
229 | #define RPS_INV (1<<26) // Invert (compound) event | ||
230 | #define GPIO3_MSK 0xFF000000 // GPIO #3 control bits | ||
231 | |||
232 | /* Bit mask constants */ | ||
233 | #define MASK_00 0x00000001 /* Mask value for bit 0 */ | ||
234 | #define MASK_01 0x00000002 /* Mask value for bit 1 */ | ||
235 | #define MASK_02 0x00000004 /* Mask value for bit 2 */ | ||
236 | #define MASK_03 0x00000008 /* Mask value for bit 3 */ | ||
237 | #define MASK_04 0x00000010 /* Mask value for bit 4 */ | ||
238 | #define MASK_05 0x00000020 /* Mask value for bit 5 */ | ||
239 | #define MASK_06 0x00000040 /* Mask value for bit 6 */ | ||
240 | #define MASK_07 0x00000080 /* Mask value for bit 7 */ | ||
241 | #define MASK_08 0x00000100 /* Mask value for bit 8 */ | ||
242 | #define MASK_09 0x00000200 /* Mask value for bit 9 */ | ||
243 | #define MASK_10 0x00000400 /* Mask value for bit 10 */ | ||
244 | #define MASK_11 0x00000800 /* Mask value for bit 11 */ | ||
245 | #define MASK_12 0x00001000 /* Mask value for bit 12 */ | ||
246 | #define MASK_13 0x00002000 /* Mask value for bit 13 */ | ||
247 | #define MASK_14 0x00004000 /* Mask value for bit 14 */ | ||
248 | #define MASK_15 0x00008000 /* Mask value for bit 15 */ | ||
249 | #define MASK_16 0x00010000 /* Mask value for bit 16 */ | ||
250 | #define MASK_17 0x00020000 /* Mask value for bit 17 */ | ||
251 | #define MASK_18 0x00040000 /* Mask value for bit 18 */ | ||
252 | #define MASK_19 0x00080000 /* Mask value for bit 19 */ | ||
253 | #define MASK_20 0x00100000 /* Mask value for bit 20 */ | ||
254 | #define MASK_21 0x00200000 /* Mask value for bit 21 */ | ||
255 | #define MASK_22 0x00400000 /* Mask value for bit 22 */ | ||
256 | #define MASK_23 0x00800000 /* Mask value for bit 23 */ | ||
257 | #define MASK_24 0x01000000 /* Mask value for bit 24 */ | ||
258 | #define MASK_25 0x02000000 /* Mask value for bit 25 */ | ||
259 | #define MASK_26 0x04000000 /* Mask value for bit 26 */ | ||
260 | #define MASK_27 0x08000000 /* Mask value for bit 27 */ | ||
261 | #define MASK_28 0x10000000 /* Mask value for bit 28 */ | ||
262 | #define MASK_29 0x20000000 /* Mask value for bit 29 */ | ||
263 | #define MASK_30 0x40000000 /* Mask value for bit 30 */ | ||
264 | #define MASK_31 0x80000000 /* Mask value for bit 31 */ | ||
265 | |||
266 | #define MASK_B0 0x000000ff /* Mask value for byte 0 */ | ||
267 | #define MASK_B1 0x0000ff00 /* Mask value for byte 1 */ | ||
268 | #define MASK_B2 0x00ff0000 /* Mask value for byte 2 */ | ||
269 | #define MASK_B3 0xff000000 /* Mask value for byte 3 */ | ||
270 | |||
271 | #define MASK_W0 0x0000ffff /* Mask value for word 0 */ | ||
272 | #define MASK_W1 0xffff0000 /* Mask value for word 1 */ | ||
273 | |||
274 | #define MASK_PA 0xfffffffc /* Mask value for physical address */ | ||
275 | #define MASK_PR 0xfffffffe /* Mask value for protection register */ | ||
276 | #define MASK_ER 0xffffffff /* Mask value for the entire register */ | ||
277 | |||
278 | #define MASK_NONE 0x00000000 /* No mask */ | ||
279 | |||
280 | /* register aliases */ | ||
281 | #define BASE_ODD1 0x00 /* Video DMA 1 registers */ | ||
282 | #define BASE_EVEN1 0x04 | ||
283 | #define PROT_ADDR1 0x08 | ||
284 | #define PITCH1 0x0C | ||
285 | #define BASE_PAGE1 0x10 /* Video DMA 1 base page */ | ||
286 | #define NUM_LINE_BYTE1 0x14 | ||
287 | |||
288 | #define BASE_ODD2 0x18 /* Video DMA 2 registers */ | ||
289 | #define BASE_EVEN2 0x1C | ||
290 | #define PROT_ADDR2 0x20 | ||
291 | #define PITCH2 0x24 | ||
292 | #define BASE_PAGE2 0x28 /* Video DMA 2 base page */ | ||
293 | #define NUM_LINE_BYTE2 0x2C | ||
294 | |||
295 | #define BASE_ODD3 0x30 /* Video DMA 3 registers */ | ||
296 | #define BASE_EVEN3 0x34 | ||
297 | #define PROT_ADDR3 0x38 | ||
298 | #define PITCH3 0x3C | ||
299 | #define BASE_PAGE3 0x40 /* Video DMA 3 base page */ | ||
300 | #define NUM_LINE_BYTE3 0x44 | ||
301 | |||
302 | #define PCI_BT_V1 0x48 /* Video/FIFO 1 */ | ||
303 | #define PCI_BT_V2 0x49 /* Video/FIFO 2 */ | ||
304 | #define PCI_BT_V3 0x4A /* Video/FIFO 3 */ | ||
305 | #define PCI_BT_DEBI 0x4B /* DEBI */ | ||
306 | #define PCI_BT_A 0x4C /* Audio */ | ||
307 | |||
308 | #define DD1_INIT 0x50 /* Init setting of DD1 interface */ | ||
309 | |||
310 | #define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */ | ||
311 | #define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */ | ||
312 | |||
313 | #define BRS_CTRL 0x58 /* BRS control register */ | ||
314 | #define HPS_CTRL 0x5C /* HPS control register */ | ||
315 | #define HPS_V_SCALE 0x60 /* HPS vertical scale */ | ||
316 | #define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */ | ||
317 | #define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */ | ||
318 | #define HPS_H_SCALE 0x6C /* HPS horizontal scale */ | ||
319 | #define BCS_CTRL 0x70 /* BCS control */ | ||
320 | #define CHROMA_KEY_RANGE 0x74 | ||
321 | #define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */ | ||
322 | |||
323 | #define DEBI_CONFIG 0x7C | ||
324 | #define DEBI_COMMAND 0x80 | ||
325 | #define DEBI_PAGE 0x84 | ||
326 | #define DEBI_AD 0x88 | ||
327 | |||
328 | #define I2C_TRANSFER 0x8C | ||
329 | #define I2C_STATUS 0x90 | ||
330 | |||
331 | #define BASE_A1_IN 0x94 /* Audio 1 input DMA */ | ||
332 | #define PROT_A1_IN 0x98 | ||
333 | #define PAGE_A1_IN 0x9C | ||
334 | |||
335 | #define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */ | ||
336 | #define PROT_A1_OUT 0xA4 | ||
337 | #define PAGE_A1_OUT 0xA8 | ||
338 | |||
339 | #define BASE_A2_IN 0xAC /* Audio 2 input DMA */ | ||
340 | #define PROT_A2_IN 0xB0 | ||
341 | #define PAGE_A2_IN 0xB4 | ||
342 | |||
343 | #define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */ | ||
344 | #define PROT_A2_OUT 0xBC | ||
345 | #define PAGE_A2_OUT 0xC0 | ||
346 | |||
347 | #define RPS_PAGE0 0xC4 /* RPS task 0 page register */ | ||
348 | #define RPS_PAGE1 0xC8 /* RPS task 1 page register */ | ||
349 | |||
350 | #define RPS_THRESH0 0xCC /* HBI threshold for task 0 */ | ||
351 | #define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */ | ||
352 | |||
353 | #define RPS_TOV0 0xD4 /* RPS timeout for task 0 */ | ||
354 | #define RPS_TOV1 0xD8 /* RPS timeout for task 1 */ | ||
355 | |||
356 | #define IER 0xDC /* Interrupt enable register */ | ||
357 | |||
358 | #define GPIO_CTRL 0xE0 /* GPIO 0-3 register */ | ||
359 | |||
360 | #define EC1SSR 0xE4 /* Event cnt set 1 source select */ | ||
361 | #define EC2SSR 0xE8 /* Event cnt set 2 source select */ | ||
362 | #define ECT1R 0xEC /* Event cnt set 1 thresholds */ | ||
363 | #define ECT2R 0xF0 /* Event cnt set 2 thresholds */ | ||
364 | |||
365 | #define ACON1 0xF4 | ||
366 | #define ACON2 0xF8 | ||
367 | |||
368 | #define MC1 0xFC /* Main control register 1 */ | ||
369 | #define MC2 0x100 /* Main control register 2 */ | ||
370 | |||
371 | #define RPS_ADDR0 0x104 /* RPS task 0 address register */ | ||
372 | #define RPS_ADDR1 0x108 /* RPS task 1 address register */ | ||
373 | |||
374 | #define ISR 0x10C /* Interrupt status register */ | ||
375 | #define PSR 0x110 /* Primary status register */ | ||
376 | #define SSR 0x114 /* Secondary status register */ | ||
377 | |||
378 | #define EC1R 0x118 /* Event counter set 1 register */ | ||
379 | #define EC2R 0x11C /* Event counter set 2 register */ | ||
380 | |||
381 | #define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */ | ||
382 | #define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */ | ||
383 | #define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */ | ||
384 | #define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */ | ||
385 | #define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */ | ||
386 | #define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */ | ||
387 | #define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */ | ||
388 | #define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */ | ||
389 | |||
390 | #define LEVEL_REP 0x140, | ||
391 | #define A_TIME_SLOT1 0x180, /* from 180 - 1BC */ | ||
392 | #define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */ | ||
393 | |||
394 | /* isr masks */ | ||
395 | #define SPCI_PPEF 0x80000000 /* PCI parity error */ | ||
396 | #define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */ | ||
397 | #define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */ | ||
398 | #define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */ | ||
399 | #define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */ | ||
400 | #define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */ | ||
401 | #define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */ | ||
402 | #define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */ | ||
403 | #define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */ | ||
404 | #define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */ | ||
405 | #define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */ | ||
406 | #define SPCI_UPLD 0x00100000 /* RPS in upload */ | ||
407 | #define SPCI_DEBI_S 0x00080000 /* DEBI status */ | ||
408 | #define SPCI_DEBI_E 0x00040000 /* DEBI error */ | ||
409 | #define SPCI_IIC_S 0x00020000 /* I2C status */ | ||
410 | #define SPCI_IIC_E 0x00010000 /* I2C error */ | ||
411 | #define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */ | ||
412 | #define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */ | ||
413 | #define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */ | ||
414 | #define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */ | ||
415 | #define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */ | ||
416 | #define SPCI_V_PE 0x00000400 /* Video protection address */ | ||
417 | #define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */ | ||
418 | #define SPCI_FIDA 0x00000100 /* Field ID video port A */ | ||
419 | #define SPCI_FIDB 0x00000080 /* Field ID video port B */ | ||
420 | #define SPCI_PIN3 0x00000040 /* GPIO pin 3 */ | ||
421 | #define SPCI_PIN2 0x00000020 /* GPIO pin 2 */ | ||
422 | #define SPCI_PIN1 0x00000010 /* GPIO pin 1 */ | ||
423 | #define SPCI_PIN0 0x00000008 /* GPIO pin 0 */ | ||
424 | #define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */ | ||
425 | #define SPCI_EC3S 0x00000002 /* Event counter 3 */ | ||
426 | #define SPCI_EC0S 0x00000001 /* Event counter 0 */ | ||
427 | |||
428 | /* i2c */ | ||
429 | #define SAA7146_I2C_ABORT (1<<7) | ||
430 | #define SAA7146_I2C_SPERR (1<<6) | ||
431 | #define SAA7146_I2C_APERR (1<<5) | ||
432 | #define SAA7146_I2C_DTERR (1<<4) | ||
433 | #define SAA7146_I2C_DRERR (1<<3) | ||
434 | #define SAA7146_I2C_AL (1<<2) | ||
435 | #define SAA7146_I2C_ERR (1<<1) | ||
436 | #define SAA7146_I2C_BUSY (1<<0) | ||
437 | |||
438 | #define SAA7146_I2C_START (0x3) | ||
439 | #define SAA7146_I2C_CONT (0x2) | ||
440 | #define SAA7146_I2C_STOP (0x1) | ||
441 | #define SAA7146_I2C_NOP (0x0) | ||
442 | |||
443 | #define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500) | ||
444 | #define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100) | ||
445 | #define SAA7146_I2C_BUS_BIT_RATE_480 (0x400) | ||
446 | #define SAA7146_I2C_BUS_BIT_RATE_320 (0x600) | ||
447 | #define SAA7146_I2C_BUS_BIT_RATE_240 (0x700) | ||
448 | #define SAA7146_I2C_BUS_BIT_RATE_120 (0x000) | ||
449 | #define SAA7146_I2C_BUS_BIT_RATE_80 (0x200) | ||
450 | #define SAA7146_I2C_BUS_BIT_RATE_60 (0x300) | ||
451 | |||
452 | #endif | ||