diff options
| author | Sandor Yu <R01008@freescale.com> | 2014-07-01 03:48:57 -0400 |
|---|---|---|
| committer | Sandor Yu <R01008@freescale.com> | 2014-07-03 04:16:55 -0400 |
| commit | afdee488043af1ca3568f3a7a69e0d4b019e92b4 (patch) | |
| tree | a03cdd88b729b84159c09a26d1bd0865a9dcccec /include/linux/mfd | |
| parent | 0b2c79cb930c344b5d2c12456f0698a8cc58524e (diff) | |
ENGR00317086-2 gpr: Add dcic mux define in gpr head file
Add dcic mux bit define in gpr head file for both imx6q and imx6sx.
Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 216ccc9b67f51935c08387cac31da35fb3fb4568)
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index dc7f6633768b..653e7712ddeb 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |||
| @@ -267,15 +267,15 @@ | |||
| 267 | #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) | 267 | #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5) |
| 268 | #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) | 268 | #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4) |
| 269 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) | 269 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2) |
| 270 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2) | 270 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x0 << 2) |
| 271 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2) | 271 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0 (0x1 << 2) |
| 272 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2) | 272 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1 (0x2 << 2) |
| 273 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2) | 273 | #define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI (0x3 << 2) |
| 274 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) | 274 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0) |
| 275 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) | 275 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0) |
| 276 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0) | 276 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0 (0x1 << 0) |
| 277 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0) | 277 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1 (0x2 << 0) |
| 278 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0) | 278 | #define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI (0x3 << 0) |
| 279 | 279 | ||
| 280 | #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) | 280 | #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27) |
| 281 | #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) | 281 | #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) |
| @@ -419,4 +419,11 @@ | |||
| 419 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) | 419 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4) |
| 420 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) | 420 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4) |
| 421 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) | 421 | #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4) |
| 422 | |||
| 423 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2 (0x0 << 2) | ||
| 424 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS (0x1 << 2) | ||
| 425 | #define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK (0x1 << 2) | ||
| 426 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1 (0x0 << 1) | ||
| 427 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1) | ||
| 428 | #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1) | ||
| 422 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ | 429 | #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */ |