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authorAndrew Victor <andrew@sanpeople.com>2007-05-11 16:01:28 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-11 17:02:48 -0400
commitc53c9cf60e49119e97d38390849cac5b2f0a0981 (patch)
tree37615dedbbd8980b8357df47d90843eb86d017ff /include/asm-arm/arch-ks8695/regs-pci.h
parentc42dcb3dcfd3a473ab7c79c2ae91fc1c2e4dc5db (diff)
[ARM] 4331/3: Support for Micrel/Kendin KS8695 processor
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-ks8695/regs-pci.h')
-rw-r--r--include/asm-arm/arch-ks8695/regs-pci.h53
1 files changed, 53 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ks8695/regs-pci.h b/include/asm-arm/arch-ks8695/regs-pci.h
new file mode 100644
index 000000000000..286d6d488df8
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/regs-pci.h
@@ -0,0 +1,53 @@
1/*
2 * include/asm-arm/arch-ks8695/regs-pci.h
3 *
4 * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
5 * Copyright (C) 2006 Simtec Electronics
6 *
7 * KS8695 - PCI bridge registers and bit definitions.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#define KS8695_PCI_OFFSET (0xF0000 + 0x2000)
15#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET)
16#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET)
17
18
19#define KS8695_CRCFID (0x000) /* Configuration: Identification */
20#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */
21#define KS8695_CRCFRV (0x008) /* Configuration: Revision */
22#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */
23#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */
24#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */
25#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */
26#define KS8695_PBCA (0x100) /* Bridge Configuration Address */
27#define KS8695_PBCD (0x104) /* Bridge Configuration Data */
28#define KS8695_PBM (0x200) /* Bridge Mode */
29#define KS8695_PBCS (0x204) /* Bridge Control and Status */
30#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */
31#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */
32#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */
33#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */
34#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */
35#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */
36#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */
37#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */
38
39
40/* Configuration: Identification */
41
42/* Configuration: Command and Status */
43
44/* Configuration: Revision */
45
46
47
48#define CFRV_GUEST (1 << 23)
49
50#define PBCA_TYPE1 (1)
51#define PBCA_ENABLE (1 << 31)
52
53