drm/i915: Reset GMBUS controller after NAK

Once a NAK has been asserted by the slave, we need to reset the GMBUS
controller in order to continue. This is done by asserting the Software
Clear Interrupt bit and then clearing it again to restore operations.

If we don't clear the NAK, then all future GMBUS xfers will fail,
including DDC probes and EDID retrieval.

v2: Add some comments as suggested by Keith Packard.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35781
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Tested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: "Mengmeng Meng" <mengmeng.meng@intel.com>

1 files changed, 21 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 82d04c5899d2..d3b903bce7c5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -259,7 +259,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
                                         goto timeout;
                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                                        return 0;
+                                        goto clear_err;
 
                                 val = I915_READ(GMBUS3 + reg_offset);
                                 do {
@@ -287,7 +287,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
                                         goto timeout;
                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                                        return 0;
+                                        goto clear_err;
 
                                 val = loop = 0;
                                 do {
@@ -302,14 +302,31 @@ gmbus_xfer(struct i2c_adapter *adapter,
                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
                         goto timeout;
                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                        return 0;
+                        goto clear_err;
         }
 
-        return num;
+        goto done;
+
+clear_err:
+        /* Toggle the Software Clear Interrupt bit. This has the effect
+         * of resetting the GMBUS controller and so clearing the
+         * BUS_ERROR raised by the slave's NAK.
+         */
+        I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
+        I915_WRITE(GMBUS1 + reg_offset, 0);
+
+done:
+        /* Mark the GMBUS interface as disabled. We will re-enable it at the
+         * start of the next xfer, till then let it sleep.
+         */
+        I915_WRITE(GMBUS0 + reg_offset, 0);
+        return i;
 
 timeout:
         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
                  bus->reg0 & 0xff, bus->adapter.name);
+        I915_WRITE(GMBUS0 + reg_offset, 0);
+
         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
         if (!bus->force_bit)