diff options
author | Eilon Greenstein <eilong@broadcom.com> | 2009-07-28 20:20:04 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-07-30 15:19:20 -0400 |
commit | 581ce43d269bb9f9ea85d8f6e6acf68bad129740 (patch) | |
tree | 70ec22610ebf430603c98f596d9deb91bd59a6b4 /drivers | |
parent | 044824d96208c8ec4863f9c54a529e00a1f1d37c (diff) |
bnx2x: Receive traffic that maches management filtering rules
Due to lack of configuration, if the BMC configures the chip to pass all
broadcast/multicast traffic to it, the host will not receive it. On top of
fixing it, also make sure that in promiscuous mode, the host will receive the
management traffic as well.
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/bnx2x_main.c | 13 | ||||
-rw-r--r-- | drivers/net/bnx2x_reg.h | 5 |
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index a2de0cd9c9f9..5273988359ec 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
@@ -4831,7 +4831,14 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |||
4831 | int mode = bp->rx_mode; | 4831 | int mode = bp->rx_mode; |
4832 | int mask = (1 << BP_L_ID(bp)); | 4832 | int mask = (1 << BP_L_ID(bp)); |
4833 | int func = BP_FUNC(bp); | 4833 | int func = BP_FUNC(bp); |
4834 | int port = BP_PORT(bp); | ||
4834 | int i; | 4835 | int i; |
4836 | /* All but management unicast packets should pass to the host as well */ | ||
4837 | u32 llh_mask = | ||
4838 | NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST | | ||
4839 | NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST | | ||
4840 | NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN | | ||
4841 | NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN; | ||
4835 | 4842 | ||
4836 | DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask); | 4843 | DP(NETIF_MSG_IFUP, "rx mode %d mask 0x%x\n", mode, mask); |
4837 | 4844 | ||
@@ -4855,6 +4862,8 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |||
4855 | tstorm_mac_filter.ucast_accept_all = mask; | 4862 | tstorm_mac_filter.ucast_accept_all = mask; |
4856 | tstorm_mac_filter.mcast_accept_all = mask; | 4863 | tstorm_mac_filter.mcast_accept_all = mask; |
4857 | tstorm_mac_filter.bcast_accept_all = mask; | 4864 | tstorm_mac_filter.bcast_accept_all = mask; |
4865 | /* pass management unicast packets as well */ | ||
4866 | llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST; | ||
4858 | break; | 4867 | break; |
4859 | 4868 | ||
4860 | default: | 4869 | default: |
@@ -4862,6 +4871,10 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |||
4862 | break; | 4871 | break; |
4863 | } | 4872 | } |
4864 | 4873 | ||
4874 | REG_WR(bp, | ||
4875 | (port ? NIG_REG_LLH1_BRB1_DRV_MASK : NIG_REG_LLH0_BRB1_DRV_MASK), | ||
4876 | llh_mask); | ||
4877 | |||
4865 | for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) { | 4878 | for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) { |
4866 | REG_WR(bp, BAR_TSTRORM_INTMEM + | 4879 | REG_WR(bp, BAR_TSTRORM_INTMEM + |
4867 | TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4, | 4880 | TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4, |
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index d771168ec20a..8e9e7a24f2fc 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -1616,6 +1616,11 @@ | |||
1616 | /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are | 1616 | /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are |
1617 | loaded; 0-prepare; -unprepare */ | 1617 | loaded; 0-prepare; -unprepare */ |
1618 | #define MISC_REG_UNPREPARED 0xa424 | 1618 | #define MISC_REG_UNPREPARED 0xa424 |
1619 | #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) | ||
1620 | #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) | ||
1621 | #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) | ||
1622 | #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) | ||
1623 | #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) | ||
1619 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) | 1624 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) |
1620 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) | 1625 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) |
1621 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) | 1626 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) |