OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP

Clock source names vary across OMAP2/3 and OMAP4, the clock source enum
names have been made generic in the driver, but for purposes of debugging
and dumping clock sources, it is better to preserve the actual TRM name of
the clock.

Introduce a dss feature function 'dss_feat_get_clk_source_name()' which
returns a string with the TRM clock name for the current OMAP in use. The OMAP
specific name is printed along the generic name within brackets.

Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

1 files changed, 17 insertions, 2 deletions

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 998c188c8823..d049598bb412 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -81,6 +81,12 @@ static struct {
         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
 } dss;
 
+static const struct dss_clk_source_name dss_generic_clk_source_names[] = {
+        { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" },
+        { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" },
+        { DSS_CLK_SRC_FCK, "DSS_FCK" },
+};
+
 static void dss_clk_enable_all_no_ctx(void);
 static void dss_clk_disable_all_no_ctx(void);
 static void dss_clk_enable_no_ctx(enum dss_clock clks);
@@ -223,6 +229,11 @@ void dss_sdi_disable(void)
         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 }
 
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
+{
+        return dss_generic_clk_source_names[clk_src].clksrc_name;
+}
+
 void dss_dump_clocks(struct seq_file *s)
 {
         unsigned long dpll4_ck_rate;
@@ -238,12 +249,16 @@ void dss_dump_clocks(struct seq_file *s)
         seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 
         if (cpu_is_omap3630())
-                seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
+                seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
+                        dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
+                        dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
                         dpll4_ck_rate,
                         dpll4_ck_rate / dpll4_m4_ck_rate,
                         dss_clk_get_rate(DSS_CLK_FCK));
         else
-                seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
+                seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
+                        dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
+                        dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
                         dpll4_ck_rate,
                         dpll4_ck_rate / dpll4_m4_ck_rate,
                         dss_clk_get_rate(DSS_CLK_FCK));