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authorArchit Taneja <archit@ti.com>2011-05-06 02:15:50 -0400
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-05-11 07:20:52 -0400
commit702d144845086cacf8bb4f23196189f260c250e2 (patch)
tree536f9af661ea3cd004591c3bde278febf0d3d786 /drivers/video/omap2/dss/dispc.h
parent9b372c2d9da43be00e8a267730a2428e0eae12e8 (diff)
OMAP: DSS2: Clean up DISPC overlay manager register definitions
Represent manager/channel specific DISPC registers as inline functions returning the required dispc_reg struct. This is done since the current method is not scalable as the number of overlay managers increase in number. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dispc.h')
-rw-r--r--drivers/video/omap2/dss/dispc.h212
1 files changed, 187 insertions, 25 deletions
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
index f22346b59c58..05e56621d1f4 100644
--- a/drivers/video/omap2/dss/dispc.h
+++ b/drivers/video/omap2/dss/dispc.h
@@ -25,42 +25,20 @@ struct dispc_reg { u16 idx; };
25 25
26#define DISPC_REG(idx) ((const struct dispc_reg) { idx }) 26#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
27 27
28/* 28/* DISPC common registers */
29 * DISPC common registers and
30 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
31 * DIGIT, and ch = 2 for LCD2
32 */
33#define DISPC_REVISION DISPC_REG(0x0000) 29#define DISPC_REVISION DISPC_REG(0x0000)
34#define DISPC_SYSCONFIG DISPC_REG(0x0010) 30#define DISPC_SYSCONFIG DISPC_REG(0x0010)
35#define DISPC_SYSSTATUS DISPC_REG(0x0014) 31#define DISPC_SYSSTATUS DISPC_REG(0x0014)
36#define DISPC_IRQSTATUS DISPC_REG(0x0018) 32#define DISPC_IRQSTATUS DISPC_REG(0x0018)
37#define DISPC_IRQENABLE DISPC_REG(0x001C) 33#define DISPC_IRQENABLE DISPC_REG(0x001C)
38#define DISPC_CONTROL DISPC_REG(0x0040) 34#define DISPC_CONTROL DISPC_REG(0x0040)
39#define DISPC_CONTROL2 DISPC_REG(0x0238)
40#define DISPC_CONFIG DISPC_REG(0x0044) 35#define DISPC_CONFIG DISPC_REG(0x0044)
41#define DISPC_CONFIG2 DISPC_REG(0x0620)
42#define DISPC_CAPABLE DISPC_REG(0x0048) 36#define DISPC_CAPABLE DISPC_REG(0x0048)
43#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
44 (ch == 1 ? 0x0050 : 0x03AC))
45#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
46 (ch == 1 ? 0x0058 : 0x03B0))
47#define DISPC_LINE_STATUS DISPC_REG(0x005C) 37#define DISPC_LINE_STATUS DISPC_REG(0x005C)
48#define DISPC_LINE_NUMBER DISPC_REG(0x0060) 38#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
49#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
50#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
51#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
52#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
53#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) 39#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
54#define DISPC_SIZE_DIG DISPC_REG(0x0078) 40#define DISPC_CONTROL2 DISPC_REG(0x0238)
55#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC) 41#define DISPC_CONFIG2 DISPC_REG(0x0620)
56
57#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
58#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
59#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
60#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
61#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
62#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
63
64#define DISPC_DIVISOR DISPC_REG(0x0804) 42#define DISPC_DIVISOR DISPC_REG(0x0804)
65 43
66/* DISPC overlay registers */ 44/* DISPC overlay registers */
@@ -105,6 +83,190 @@ struct dispc_reg { u16 idx; };
105#define DISPC_OVL_PRELOAD(n) DISPC_REG(DISPC_OVL_BASE(n) + \ 83#define DISPC_OVL_PRELOAD(n) DISPC_REG(DISPC_OVL_BASE(n) + \
106 DISPC_PRELOAD_OFFSET(n)) 84 DISPC_PRELOAD_OFFSET(n))
107 85
86/* DISPC manager/channel specific registers */
87static inline struct dispc_reg DISPC_DEFAULT_COLOR(enum omap_channel channel)
88{
89 switch (channel) {
90 case OMAP_DSS_CHANNEL_LCD:
91 return DISPC_REG(0x004C);
92 case OMAP_DSS_CHANNEL_DIGIT:
93 return DISPC_REG(0x0050);
94 case OMAP_DSS_CHANNEL_LCD2:
95 return DISPC_REG(0x03AC);
96 default:
97 BUG();
98 }
99}
100
101static inline struct dispc_reg DISPC_TRANS_COLOR(enum omap_channel channel)
102{
103 switch (channel) {
104 case OMAP_DSS_CHANNEL_LCD:
105 return DISPC_REG(0x0054);
106 case OMAP_DSS_CHANNEL_DIGIT:
107 return DISPC_REG(0x0058);
108 case OMAP_DSS_CHANNEL_LCD2:
109 return DISPC_REG(0x03B0);
110 default:
111 BUG();
112 }
113}
114
115static inline struct dispc_reg DISPC_TIMING_H(enum omap_channel channel)
116{
117 switch (channel) {
118 case OMAP_DSS_CHANNEL_LCD:
119 return DISPC_REG(0x0064);
120 case OMAP_DSS_CHANNEL_DIGIT:
121 BUG();
122 case OMAP_DSS_CHANNEL_LCD2:
123 return DISPC_REG(0x0400);
124 default:
125 BUG();
126 }
127}
128
129static inline struct dispc_reg DISPC_TIMING_V(enum omap_channel channel)
130{
131 switch (channel) {
132 case OMAP_DSS_CHANNEL_LCD:
133 return DISPC_REG(0x0068);
134 case OMAP_DSS_CHANNEL_DIGIT:
135 BUG();
136 case OMAP_DSS_CHANNEL_LCD2:
137 return DISPC_REG(0x0404);
138 default:
139 BUG();
140 }
141}
142
143static inline struct dispc_reg DISPC_POL_FREQ(enum omap_channel channel)
144{
145 switch (channel) {
146 case OMAP_DSS_CHANNEL_LCD:
147 return DISPC_REG(0x006C);
148 case OMAP_DSS_CHANNEL_DIGIT:
149 BUG();
150 case OMAP_DSS_CHANNEL_LCD2:
151 return DISPC_REG(0x0408);
152 default:
153 BUG();
154 }
155}
156
157static inline struct dispc_reg DISPC_DIVISORo(enum omap_channel channel)
158{
159 switch (channel) {
160 case OMAP_DSS_CHANNEL_LCD:
161 return DISPC_REG(0x0070);
162 case OMAP_DSS_CHANNEL_DIGIT:
163 BUG();
164 case OMAP_DSS_CHANNEL_LCD2:
165 return DISPC_REG(0x040C);
166 default:
167 BUG();
168 }
169}
170
171/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
172static inline struct dispc_reg DISPC_SIZE_MGR(enum omap_channel channel)
173{
174 switch (channel) {
175 case OMAP_DSS_CHANNEL_LCD:
176 return DISPC_REG(0x007C);
177 case OMAP_DSS_CHANNEL_DIGIT:
178 return DISPC_REG(0x0078);
179 case OMAP_DSS_CHANNEL_LCD2:
180 return DISPC_REG(0x03CC);
181 default:
182 BUG();
183 }
184}
185
186static inline struct dispc_reg DISPC_DATA_CYCLE1(enum omap_channel channel)
187{
188 switch (channel) {
189 case OMAP_DSS_CHANNEL_LCD:
190 return DISPC_REG(0x01D4);
191 case OMAP_DSS_CHANNEL_DIGIT:
192 BUG();
193 case OMAP_DSS_CHANNEL_LCD2:
194 return DISPC_REG(0x03C0);
195 default:
196 BUG();
197 }
198}
199
200static inline struct dispc_reg DISPC_DATA_CYCLE2(enum omap_channel channel)
201{
202 switch (channel) {
203 case OMAP_DSS_CHANNEL_LCD:
204 return DISPC_REG(0x01D8);
205 case OMAP_DSS_CHANNEL_DIGIT:
206 BUG();
207 case OMAP_DSS_CHANNEL_LCD2:
208 return DISPC_REG(0x03C4);
209 default:
210 BUG();
211 }
212}
213
214static inline struct dispc_reg DISPC_DATA_CYCLE3(enum omap_channel channel)
215{
216 switch (channel) {
217 case OMAP_DSS_CHANNEL_LCD:
218 return DISPC_REG(0x01DC);
219 case OMAP_DSS_CHANNEL_DIGIT:
220 BUG();
221 case OMAP_DSS_CHANNEL_LCD2:
222 return DISPC_REG(0x03C8);
223 default:
224 BUG();
225 }
226}
227
228static inline struct dispc_reg DISPC_CPR_COEF_R(enum omap_channel channel)
229{
230 switch (channel) {
231 case OMAP_DSS_CHANNEL_LCD:
232 return DISPC_REG(0x0220);
233 case OMAP_DSS_CHANNEL_DIGIT:
234 BUG();
235 case OMAP_DSS_CHANNEL_LCD2:
236 return DISPC_REG(0x03BC);
237 default:
238 BUG();
239 }
240}
241
242static inline struct dispc_reg DISPC_CPR_COEF_G(enum omap_channel channel)
243{
244 switch (channel) {
245 case OMAP_DSS_CHANNEL_LCD:
246 return DISPC_REG(0x0224);
247 case OMAP_DSS_CHANNEL_DIGIT:
248 BUG();
249 case OMAP_DSS_CHANNEL_LCD2:
250 return DISPC_REG(0x03B8);
251 default:
252 BUG();
253 }
254}
255
256static inline struct dispc_reg DISPC_CPR_COEF_B(enum omap_channel channel)
257{
258 switch (channel) {
259 case OMAP_DSS_CHANNEL_LCD:
260 return DISPC_REG(0x0228);
261 case OMAP_DSS_CHANNEL_DIGIT:
262 BUG();
263 case OMAP_DSS_CHANNEL_LCD2:
264 return DISPC_REG(0x03B4);
265 default:
266 BUG();
267 }
268}
269
108/* DISPC overlay register base addresses */ 270/* DISPC overlay register base addresses */
109static inline u16 DISPC_OVL_BASE(enum omap_plane plane) 271static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
110{ 272{
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-16 10:00:23 -0400