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authorAndres Salomon <dilinger@queued.net>2008-04-28 05:14:53 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-28 11:58:35 -0400
commit32bf87e3697cf2f730b8fbf47cad903ceef718a2 (patch)
tree6476a1f8796c28e7eb70deb7eaae75872f95fb6d /drivers/video/geode/lxfb_ops.c
parent22af89aa0c0b4012a7431114a340efd3665a7617 (diff)
x86: geode: MSR cleanup
This cleans up a few MSR-using drivers in the following manner: - Ensures MSRs are all defined in asm/geode.h, rather than in misc places - Makes the naming consistent; cs553[56] ones begin with MSR_, GX-specific ones start with MSR_GX_, and LX-specific ones start with MSR_LX_. Also, make the names match the data sheet. - Use MSR names rather than numbers in source code - Document the fact that the LX's MSR_PADSEL has the wrong value in the data sheet. That's, uh, good to note. Signed-off-by: Andres Salomon <dilinger@debian.org> Acked-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/video/geode/lxfb_ops.c')
-rw-r--r--drivers/video/geode/lxfb_ops.c19
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c
index 4fbc99be96ef..a52c180062c8 100644
--- a/drivers/video/geode/lxfb_ops.c
+++ b/drivers/video/geode/lxfb_ops.c
@@ -13,6 +13,7 @@
13#include <linux/fb.h> 13#include <linux/fb.h>
14#include <linux/uaccess.h> 14#include <linux/uaccess.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <asm/geode.h>
16 17
17#include "lxfb.h" 18#include "lxfb.h"
18 19
@@ -101,7 +102,7 @@ static void lx_set_dotpll(u32 pllval)
101 u32 dotpll_lo, dotpll_hi; 102 u32 dotpll_lo, dotpll_hi;
102 int i; 103 int i;
103 104
104 rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 105 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
105 106
106 if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval)) 107 if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
107 return; 108 return;
@@ -110,7 +111,7 @@ static void lx_set_dotpll(u32 pllval)
110 dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX); 111 dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
111 dotpll_lo |= GLCP_DOTPLL_RESET; 112 dotpll_lo |= GLCP_DOTPLL_RESET;
112 113
113 wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 114 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
114 115
115 /* Wait 100us for the PLL to lock */ 116 /* Wait 100us for the PLL to lock */
116 117
@@ -119,7 +120,7 @@ static void lx_set_dotpll(u32 pllval)
119 /* Now, loop for the lock bit */ 120 /* Now, loop for the lock bit */
120 121
121 for (i = 0; i < 1000; i++) { 122 for (i = 0; i < 1000; i++) {
122 rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 123 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
123 if (dotpll_lo & GLCP_DOTPLL_LOCK) 124 if (dotpll_lo & GLCP_DOTPLL_LOCK)
124 break; 125 break;
125 } 126 }
@@ -127,7 +128,7 @@ static void lx_set_dotpll(u32 pllval)
127 /* Clear the reset bit */ 128 /* Clear the reset bit */
128 129
129 dotpll_lo &= ~GLCP_DOTPLL_RESET; 130 dotpll_lo &= ~GLCP_DOTPLL_RESET;
130 wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi); 131 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
131} 132}
132 133
133/* Set the clock based on the frequency specified by the current mode */ 134/* Set the clock based on the frequency specified by the current mode */
@@ -255,7 +256,7 @@ static void lx_graphics_enable(struct fb_info *info)
255 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW; 256 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
256 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH; 257 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
257 258
258 wrmsr(MSR_LX_DF_PADSEL, msrlo, msrhi); 259 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
259 } 260 }
260 261
261 if (par->output & OUTPUT_CRT) { 262 if (par->output & OUTPUT_CRT) {
@@ -321,7 +322,7 @@ void lx_set_mode(struct fb_info *info)
321 322
322 /* Set output mode */ 323 /* Set output mode */
323 324
324 rdmsrl(MSR_LX_DF_GLCONFIG, msrval); 325 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
325 msrval &= ~DF_CONFIG_OUTPUT_MASK; 326 msrval &= ~DF_CONFIG_OUTPUT_MASK;
326 327
327 if (par->output & OUTPUT_PANEL) { 328 if (par->output & OUTPUT_PANEL) {
@@ -335,7 +336,7 @@ void lx_set_mode(struct fb_info *info)
335 msrval |= DF_OUTPUT_CRT; 336 msrval |= DF_OUTPUT_CRT;
336 } 337 }
337 338
338 wrmsrl(MSR_LX_DF_GLCONFIG, msrval); 339 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
339 340
340 /* Clear the various buffers */ 341 /* Clear the various buffers */
341 /* FIXME: Adjust for panning here */ 342 /* FIXME: Adjust for panning here */
@@ -383,13 +384,13 @@ void lx_set_mode(struct fb_info *info)
383 384
384 /* Set default watermark values */ 385 /* Set default watermark values */
385 386
386 rdmsrl(MSR_LX_DC_SPARE, msrval); 387 rdmsrl(MSR_LX_SPARE_MSR, msrval);
387 388
388 msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT | 389 msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
389 DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD | 390 DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
390 DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM); 391 DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
391 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI; 392 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
392 wrmsrl(MSR_LX_DC_SPARE, msrval); 393 wrmsrl(MSR_LX_SPARE_MSR, msrval);
393 394
394 gcfg = DC_GCFG_DFLE; /* Display fifo enable */ 395 gcfg = DC_GCFG_DFLE; /* Display fifo enable */
395 gcfg |= 0xB600; /* Set default priority */ 396 gcfg |= 0xB600; /* Set default priority */