diff options
author | Jon Povey <jon.povey@racelogic.co.uk> | 2012-05-24 21:50:18 -0400 |
---|---|---|
committer | Felipe Balbi <balbi@ti.com> | 2012-06-04 11:29:42 -0400 |
commit | 6594b2d7b1ef8260e6e36ddc96bd37a40e39ba80 (patch) | |
tree | 92f64e51aabe6bbdb85b09afae8aa99e8c8bf983 /drivers/usb/musb/davinci.h | |
parent | 80e91fd59bc5291c6fe322551f644a58cf2c5e98 (diff) |
usb: musb: davinci: Fix build breakage
This appears to have been broken by
commit 5cfb19ac604a68c030b245561f575c2d1bac1d49
(ARM: davinci: streamline sysmod access)
For now, fix by hardcoding USB_PHY_CTRL and DM355_DEEPSLEEP
Tested on DM365 with defconfig changes.
Signed-off-by: Jon Povey <jon.povey@racelogic.co.uk>
Acked-by: Sekhar Nori <nsekhar@ti.com>
CC: Felipe Balbi <balbi@ti.com>
Cc: <stable@vger.kernel.org> # v3.4.x
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/musb/davinci.h')
-rw-r--r-- | drivers/usb/musb/davinci.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/usb/musb/davinci.h b/drivers/usb/musb/davinci.h index 046c84433cad..371baa0ee509 100644 --- a/drivers/usb/musb/davinci.h +++ b/drivers/usb/musb/davinci.h | |||
@@ -15,7 +15,7 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | /* Integrated highspeed/otg PHY */ | 17 | /* Integrated highspeed/otg PHY */ |
18 | #define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34) | 18 | #define USBPHY_CTL_PADDR 0x01c40034 |
19 | #define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */ | 19 | #define USBPHY_DATAPOL BIT(11) /* (dm355) switch D+/D- */ |
20 | #define USBPHY_PHYCLKGD BIT(8) | 20 | #define USBPHY_PHYCLKGD BIT(8) |
21 | #define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */ | 21 | #define USBPHY_SESNDEN BIT(7) /* v(sess_end) comparator */ |
@@ -27,7 +27,7 @@ | |||
27 | #define USBPHY_OTGPDWN BIT(1) | 27 | #define USBPHY_OTGPDWN BIT(1) |
28 | #define USBPHY_PHYPDWN BIT(0) | 28 | #define USBPHY_PHYPDWN BIT(0) |
29 | 29 | ||
30 | #define DM355_DEEPSLEEP_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x48) | 30 | #define DM355_DEEPSLEEP_PADDR 0x01c40048 |
31 | #define DRVVBUS_FORCE BIT(2) | 31 | #define DRVVBUS_FORCE BIT(2) |
32 | #define DRVVBUS_OVERRIDE BIT(1) | 32 | #define DRVVBUS_OVERRIDE BIT(1) |
33 | 33 | ||