usb: Add support for root hub port status CAS

The host controller port status register supports CAS (Cold Attach
Status) bit. This bit could be set when USB3.0 device is connected
when system is in Sx state. When the system wakes to S0 this port
status with CAS bit is reported and this port can't be used by any
device.

When CAS bit is set the port should be reset by warm reset. This
was not supported by xhci driver.

The issue was found when pendrive was connected to suspended
platform. The link state of "Compliance Mode" was reported together
with CAS bit. This link state was also not supported by xhci and
core/hub.c.

The CAS bit is defined only for xhci root hub port and it is
not supported on regular hubs. The link status is used to force
warm reset on port. Make the USB core issue a warm reset when port
is in ether the 'inactive' or 'compliance mode'. Change the xHCI driver
to report 'compliance mode' when the CAS is set. This force warm reset
on the root hub port.

This patch should be backported to stable kernels as old as 3.2, that
contain the commit 10d674a82e553cb8a1f41027bb3c3e309b3f6804 "USB: When
hot reset for USB3 fails, try warm reset."

Signed-off-by: Stanislaw Ledwon <staszek.ledwon@linux.intel.com>
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Acked-by: Andiry Xu <andiry.xu@amd.com>
Cc: stable@vger.kernel.org

1 files changed, 38 insertions, 6 deletions

diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 2732ef660c5c..7b01094d7993 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -462,6 +462,42 @@ void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
         }
 }
 
+/* Updates Link Status for super Speed port */
+static void xhci_hub_report_link_state(u32 *status, u32 status_reg)
+{
+        u32 pls = status_reg & PORT_PLS_MASK;
+
+        /* resume state is a xHCI internal state.
+         * Do not report it to usb core.
+         */
+        if (pls == XDEV_RESUME)
+                return;
+
+        /* When the CAS bit is set then warm reset
+         * should be performed on port
+         */
+        if (status_reg & PORT_CAS) {
+                /* The CAS bit can be set while the port is
+                 * in any link state.
+                 * Only roothubs have CAS bit, so we
+                 * pretend to be in compliance mode
+                 * unless we're already in compliance
+                 * or the inactive state.
+                 */
+                if (pls != USB_SS_PORT_LS_COMP_MOD &&
+                    pls != USB_SS_PORT_LS_SS_INACTIVE) {
+                        pls = USB_SS_PORT_LS_COMP_MOD;
+                }
+                /* Return also connection bit -
+                 * hub state machine resets port
+                 * when this bit is set.
+                 */
+                pls |= USB_PORT_STAT_CONNECTION;
+        }
+        /* update status field */
+        *status |= pls;
+}
+
 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
                 u16 wIndex, char *buf, u16 wLength)
 {
@@ -606,13 +642,9 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
                         else
                                 status |= USB_PORT_STAT_POWER;
                 }
-                /* Port Link State */
+                /* Update Port Link State for super speed ports*/
                 if (hcd->speed == HCD_USB3) {
-                        /* resume state is a xHCI internal state.
-                         * Do not report it to usb core.
-                         */
-                        if ((temp & PORT_PLS_MASK) != XDEV_RESUME)
-                                status |= (temp & PORT_PLS_MASK);
+                        xhci_hub_report_link_state(&status, temp);
                 }
                 if (bus_state->port_c_suspend & (1 << wIndex))
                         status |= 1 << USB_PORT_FEAT_C_SUSPEND;