diff options
author | Felipe Contreras <felipe.contreras@gmail.com> | 2010-11-10 13:09:35 -0500 |
---|---|---|
committer | Omar Ramirez Luna <omar.ramirez@ti.com> | 2010-11-10 19:34:43 -0500 |
commit | 9d4f81a722863c42472541cb71981d09613775b3 (patch) | |
tree | 394ecc8749c771272301b98fbfe5c36970621636 /drivers/staging | |
parent | a28903501cb7f7b1ad52c1e981aed2738ae7c434 (diff) |
Revert "staging: tidspbridge: remove dw_dmmu_base from cfg_hostres struct"
This reverts commit b5a44939231d6e3b0354624289507bfa1432a7b1.
Signed-off-by: Felipe Contreras <felipe.contreras@gmail.com>
Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Diffstat (limited to 'drivers/staging')
-rw-r--r-- | drivers/staging/tidspbridge/core/tiomap3430.c | 3 | ||||
-rw-r--r-- | drivers/staging/tidspbridge/core/tiomap_io.c | 3 | ||||
-rw-r--r-- | drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h | 1 | ||||
-rw-r--r-- | drivers/staging/tidspbridge/rmgr/drv.c | 4 |
4 files changed, 10 insertions, 1 deletions
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c index 1425c50e72b9..53b38b2b9ce1 100644 --- a/drivers/staging/tidspbridge/core/tiomap3430.c +++ b/drivers/staging/tidspbridge/core/tiomap3430.c | |||
@@ -845,6 +845,8 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt) | |||
845 | iounmap((void *)host_res->dw_mem_base[3]); | 845 | iounmap((void *)host_res->dw_mem_base[3]); |
846 | if (host_res->dw_mem_base[4]) | 846 | if (host_res->dw_mem_base[4]) |
847 | iounmap((void *)host_res->dw_mem_base[4]); | 847 | iounmap((void *)host_res->dw_mem_base[4]); |
848 | if (host_res->dw_dmmu_base) | ||
849 | iounmap(host_res->dw_dmmu_base); | ||
848 | if (host_res->dw_per_base) | 850 | if (host_res->dw_per_base) |
849 | iounmap(host_res->dw_per_base); | 851 | iounmap(host_res->dw_per_base); |
850 | if (host_res->dw_per_pm_base) | 852 | if (host_res->dw_per_pm_base) |
@@ -858,6 +860,7 @@ static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt) | |||
858 | host_res->dw_mem_base[2] = (u32) NULL; | 860 | host_res->dw_mem_base[2] = (u32) NULL; |
859 | host_res->dw_mem_base[3] = (u32) NULL; | 861 | host_res->dw_mem_base[3] = (u32) NULL; |
860 | host_res->dw_mem_base[4] = (u32) NULL; | 862 | host_res->dw_mem_base[4] = (u32) NULL; |
863 | host_res->dw_dmmu_base = NULL; | ||
861 | host_res->dw_sys_ctrl_base = NULL; | 864 | host_res->dw_sys_ctrl_base = NULL; |
862 | 865 | ||
863 | kfree(host_res); | 866 | kfree(host_res); |
diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c index 66dbf02549e4..b526532fdd07 100644 --- a/drivers/staging/tidspbridge/core/tiomap_io.c +++ b/drivers/staging/tidspbridge/core/tiomap_io.c | |||
@@ -393,6 +393,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) | |||
393 | omap_dspbridge_dev->dev.platform_data; | 393 | omap_dspbridge_dev->dev.platform_data; |
394 | struct cfg_hostres *resources = dev_context->resources; | 394 | struct cfg_hostres *resources = dev_context->resources; |
395 | int status = 0; | 395 | int status = 0; |
396 | u32 temp; | ||
396 | 397 | ||
397 | if (!dev_context->mbox) | 398 | if (!dev_context->mbox) |
398 | return 0; | 399 | return 0; |
@@ -436,7 +437,7 @@ int sm_interrupt_dsp(struct bridge_dev_context *dev_context, u16 mb_val) | |||
436 | omap_mbox_restore_ctx(dev_context->mbox); | 437 | omap_mbox_restore_ctx(dev_context->mbox); |
437 | 438 | ||
438 | /* Access MMU SYS CONFIG register to generate a short wakeup */ | 439 | /* Access MMU SYS CONFIG register to generate a short wakeup */ |
439 | iommu_read_reg(dev_context->dsp_mmu, MMU_SYSCONFIG); | 440 | temp = readl(resources->dw_dmmu_base + 0x10); |
440 | 441 | ||
441 | dev_context->dw_brd_state = BRD_RUNNING; | 442 | dev_context->dw_brd_state = BRD_RUNNING; |
442 | } else if (dev_context->dw_brd_state == BRD_RETENTION) { | 443 | } else if (dev_context->dw_brd_state == BRD_RETENTION) { |
diff --git a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h index dfb55cca34c7..38122dbf877a 100644 --- a/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h +++ b/drivers/staging/tidspbridge/include/dspbridge/cfgdefs.h | |||
@@ -68,6 +68,7 @@ struct cfg_hostres { | |||
68 | void __iomem *dw_per_base; | 68 | void __iomem *dw_per_base; |
69 | u32 dw_per_pm_base; | 69 | u32 dw_per_pm_base; |
70 | u32 dw_core_pm_base; | 70 | u32 dw_core_pm_base; |
71 | void __iomem *dw_dmmu_base; | ||
71 | void __iomem *dw_sys_ctrl_base; | 72 | void __iomem *dw_sys_ctrl_base; |
72 | }; | 73 | }; |
73 | 74 | ||
diff --git a/drivers/staging/tidspbridge/rmgr/drv.c b/drivers/staging/tidspbridge/rmgr/drv.c index 0c857b93416a..81b1b9013550 100644 --- a/drivers/staging/tidspbridge/rmgr/drv.c +++ b/drivers/staging/tidspbridge/rmgr/drv.c | |||
@@ -743,6 +743,7 @@ static int request_bridge_resources(struct cfg_hostres *res) | |||
743 | host_res->dw_sys_ctrl_base = ioremap(OMAP_SYSC_BASE, OMAP_SYSC_SIZE); | 743 | host_res->dw_sys_ctrl_base = ioremap(OMAP_SYSC_BASE, OMAP_SYSC_SIZE); |
744 | dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]); | 744 | dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", host_res->dw_mem_base[0]); |
745 | dev_dbg(bridge, "dw_mem_base[3] 0x%x\n", host_res->dw_mem_base[3]); | 745 | dev_dbg(bridge, "dw_mem_base[3] 0x%x\n", host_res->dw_mem_base[3]); |
746 | dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base); | ||
746 | 747 | ||
747 | /* for 24xx base port is not mapping the mamory for DSP | 748 | /* for 24xx base port is not mapping the mamory for DSP |
748 | * internal memory TODO Do a ioremap here */ | 749 | * internal memory TODO Do a ioremap here */ |
@@ -796,6 +797,8 @@ int drv_request_bridge_res_dsp(void **phost_resources) | |||
796 | OMAP_PER_PRM_SIZE); | 797 | OMAP_PER_PRM_SIZE); |
797 | host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE, | 798 | host_res->dw_core_pm_base = (u32) ioremap(OMAP_CORE_PRM_BASE, |
798 | OMAP_CORE_PRM_SIZE); | 799 | OMAP_CORE_PRM_SIZE); |
800 | host_res->dw_dmmu_base = ioremap(OMAP_DMMU_BASE, | ||
801 | OMAP_DMMU_SIZE); | ||
799 | 802 | ||
800 | dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", | 803 | dev_dbg(bridge, "dw_mem_base[0] 0x%x\n", |
801 | host_res->dw_mem_base[0]); | 804 | host_res->dw_mem_base[0]); |
@@ -807,6 +810,7 @@ int drv_request_bridge_res_dsp(void **phost_resources) | |||
807 | host_res->dw_mem_base[3]); | 810 | host_res->dw_mem_base[3]); |
808 | dev_dbg(bridge, "dw_mem_base[4] 0x%x\n", | 811 | dev_dbg(bridge, "dw_mem_base[4] 0x%x\n", |
809 | host_res->dw_mem_base[4]); | 812 | host_res->dw_mem_base[4]); |
813 | dev_dbg(bridge, "dw_dmmu_base %p\n", host_res->dw_dmmu_base); | ||
810 | 814 | ||
811 | shm_size = drv_datap->shm_size; | 815 | shm_size = drv_datap->shm_size; |
812 | if (shm_size >= 0x10000) { | 816 | if (shm_size >= 0x10000) { |