diff options
author | Paul Mundt <lethal@linux-sh.org> | 2012-05-25 02:26:01 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2012-05-25 02:26:01 -0400 |
commit | 75f5f8a56e0fdf6d32b3ae9c44c10bc0acd3857c (patch) | |
tree | ab4c7322730e02674e35e5cbbd9ac4afc57db628 /drivers/sh | |
parent | 1111cc1e8080b5ff46f5b945acb2f99d6176b2d1 (diff) |
sh: clkfwk: Use shared sh_clk_div_recalc().
This generalizes the div4 recalc routine for use by div6 and others, then
makes it the default.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/clk/cpg.c | 62 |
1 files changed, 26 insertions, 36 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 9386bd21c003..84aeeb8fe013 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c | |||
@@ -66,11 +66,6 @@ int __init sh_clk_mstp_register(struct clk *clks, int nr) | |||
66 | return ret; | 66 | return ret; |
67 | } | 67 | } |
68 | 68 | ||
69 | static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) | ||
70 | { | ||
71 | return clk_rate_table_round(clk, clk->freq_table, rate); | ||
72 | } | ||
73 | |||
74 | /* | 69 | /* |
75 | * Div/mult table lookup helpers | 70 | * Div/mult table lookup helpers |
76 | */ | 71 | */ |
@@ -85,6 +80,27 @@ static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk) | |||
85 | } | 80 | } |
86 | 81 | ||
87 | /* | 82 | /* |
83 | * Common div ops | ||
84 | */ | ||
85 | static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) | ||
86 | { | ||
87 | return clk_rate_table_round(clk, clk->freq_table, rate); | ||
88 | } | ||
89 | |||
90 | static unsigned long sh_clk_div_recalc(struct clk *clk) | ||
91 | { | ||
92 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); | ||
93 | unsigned int idx; | ||
94 | |||
95 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | ||
96 | table, clk->arch_flags ? &clk->arch_flags : NULL); | ||
97 | |||
98 | idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; | ||
99 | |||
100 | return clk->freq_table[idx].frequency; | ||
101 | } | ||
102 | |||
103 | /* | ||
88 | * div6 support | 104 | * div6 support |
89 | */ | 105 | */ |
90 | static int sh_clk_div6_divisors[64] = { | 106 | static int sh_clk_div6_divisors[64] = { |
@@ -103,19 +119,6 @@ static struct clk_div_table sh_clk_div6_table = { | |||
103 | .div_mult_table = &div6_div_mult_table, | 119 | .div_mult_table = &div6_div_mult_table, |
104 | }; | 120 | }; |
105 | 121 | ||
106 | static unsigned long sh_clk_div6_recalc(struct clk *clk) | ||
107 | { | ||
108 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); | ||
109 | unsigned int idx; | ||
110 | |||
111 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | ||
112 | table, NULL); | ||
113 | |||
114 | idx = sh_clk_read(clk) & clk->div_mask; | ||
115 | |||
116 | return clk->freq_table[idx].frequency; | ||
117 | } | ||
118 | |||
119 | static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) | 122 | static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) |
120 | { | 123 | { |
121 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); | 124 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); |
@@ -190,7 +193,7 @@ static void sh_clk_div6_disable(struct clk *clk) | |||
190 | } | 193 | } |
191 | 194 | ||
192 | static struct sh_clk_ops sh_clk_div6_clk_ops = { | 195 | static struct sh_clk_ops sh_clk_div6_clk_ops = { |
193 | .recalc = sh_clk_div6_recalc, | 196 | .recalc = sh_clk_div_recalc, |
194 | .round_rate = sh_clk_div_round_rate, | 197 | .round_rate = sh_clk_div_round_rate, |
195 | .set_rate = sh_clk_div6_set_rate, | 198 | .set_rate = sh_clk_div6_set_rate, |
196 | .enable = sh_clk_div6_enable, | 199 | .enable = sh_clk_div6_enable, |
@@ -198,7 +201,7 @@ static struct sh_clk_ops sh_clk_div6_clk_ops = { | |||
198 | }; | 201 | }; |
199 | 202 | ||
200 | static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { | 203 | static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = { |
201 | .recalc = sh_clk_div6_recalc, | 204 | .recalc = sh_clk_div_recalc, |
202 | .round_rate = sh_clk_div_round_rate, | 205 | .round_rate = sh_clk_div_round_rate, |
203 | .set_rate = sh_clk_div6_set_rate, | 206 | .set_rate = sh_clk_div6_set_rate, |
204 | .enable = sh_clk_div6_enable, | 207 | .enable = sh_clk_div6_enable, |
@@ -287,19 +290,6 @@ int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) | |||
287 | /* | 290 | /* |
288 | * div4 support | 291 | * div4 support |
289 | */ | 292 | */ |
290 | static unsigned long sh_clk_div4_recalc(struct clk *clk) | ||
291 | { | ||
292 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); | ||
293 | unsigned int idx; | ||
294 | |||
295 | clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, | ||
296 | table, &clk->arch_flags); | ||
297 | |||
298 | idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; | ||
299 | |||
300 | return clk->freq_table[idx].frequency; | ||
301 | } | ||
302 | |||
303 | static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) | 293 | static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) |
304 | { | 294 | { |
305 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); | 295 | struct clk_div_mult_table *table = clk_to_div_mult_table(clk); |
@@ -361,13 +351,13 @@ static void sh_clk_div4_disable(struct clk *clk) | |||
361 | } | 351 | } |
362 | 352 | ||
363 | static struct sh_clk_ops sh_clk_div4_clk_ops = { | 353 | static struct sh_clk_ops sh_clk_div4_clk_ops = { |
364 | .recalc = sh_clk_div4_recalc, | 354 | .recalc = sh_clk_div_recalc, |
365 | .set_rate = sh_clk_div4_set_rate, | 355 | .set_rate = sh_clk_div4_set_rate, |
366 | .round_rate = sh_clk_div_round_rate, | 356 | .round_rate = sh_clk_div_round_rate, |
367 | }; | 357 | }; |
368 | 358 | ||
369 | static struct sh_clk_ops sh_clk_div4_enable_clk_ops = { | 359 | static struct sh_clk_ops sh_clk_div4_enable_clk_ops = { |
370 | .recalc = sh_clk_div4_recalc, | 360 | .recalc = sh_clk_div_recalc, |
371 | .set_rate = sh_clk_div4_set_rate, | 361 | .set_rate = sh_clk_div4_set_rate, |
372 | .round_rate = sh_clk_div_round_rate, | 362 | .round_rate = sh_clk_div_round_rate, |
373 | .enable = sh_clk_div4_enable, | 363 | .enable = sh_clk_div4_enable, |
@@ -375,7 +365,7 @@ static struct sh_clk_ops sh_clk_div4_enable_clk_ops = { | |||
375 | }; | 365 | }; |
376 | 366 | ||
377 | static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { | 367 | static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = { |
378 | .recalc = sh_clk_div4_recalc, | 368 | .recalc = sh_clk_div_recalc, |
379 | .set_rate = sh_clk_div4_set_rate, | 369 | .set_rate = sh_clk_div4_set_rate, |
380 | .round_rate = sh_clk_div_round_rate, | 370 | .round_rate = sh_clk_div_round_rate, |
381 | .enable = sh_clk_div4_enable, | 371 | .enable = sh_clk_div4_enable, |