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authorArend van Spriel <arend@broadcom.com>2011-12-08 18:06:45 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-12-13 15:31:48 -0500
commitb2ffec46ea230acac52170dd0a747526328d25fe (patch)
treee083340fc281c502a6aafcf11275da89675bb92a /drivers/net
parent2e397c303807fadcf65f4e070603107453db4352 (diff)
brcm80211: smac: use inline access functions for struct si_pub fields
Instead of directly accessing the fields in struct si_pub the driver now uses inline access functions. This is in preparation of the bcma integration as a lot of information will be provided by bcma module. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Reviewed-by: Roland Vossen <rvossen@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.c118
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.h46
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.c56
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/nicpci.c35
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/otp.c20
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c2
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h2
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h2
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/pmu.c20
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.c4
10 files changed, 174 insertions, 131 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
index 8586ab78f891..83a013833678 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
@@ -321,9 +321,9 @@
321/* Newer chips can access PCI/PCIE and CC core without requiring to change 321/* Newer chips can access PCI/PCIE and CC core without requiring to change
322 * PCI BAR0 WIN 322 * PCI BAR0 WIN
323 */ 323 */
324#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \ 324#define SI_FAST(sih) ((ai_get_buscoretype(sih) == PCIE_CORE_ID) || \
325 (((si)->pub.buscoretype == PCI_CORE_ID) && \ 325 ((ai_get_buscoretype(sih) == PCI_CORE_ID) && \
326 (si)->pub.buscorerev >= 13)) 326 ai_get_buscorerev(sih) >= 13))
327 327
328#define CCREGS_FAST(si) (((char __iomem *)((si)->curmap) + \ 328#define CCREGS_FAST(si) (((char __iomem *)((si)->curmap) + \
329 PCI_16KB0_CCREGS_OFFSET)) 329 PCI_16KB0_CCREGS_OFFSET))
@@ -345,10 +345,10 @@
345 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \ 345 (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
346 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val) 346 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
347 347
348#define PCI(si) ((si)->pub.buscoretype == PCI_CORE_ID) 348#define PCI(sih) (ai_get_buscoretype(sih) == PCI_CORE_ID)
349#define PCIE(si) ((si)->pub.buscoretype == PCIE_CORE_ID) 349#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
350 350
351#define PCI_FORCEHT(si) (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID)) 351#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
352 352
353#ifdef BCMDBG 353#ifdef BCMDBG
354#define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__) 354#define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
@@ -927,14 +927,14 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
927 sii->pub.ccrev = (int)ai_corerev(&sii->pub); 927 sii->pub.ccrev = (int)ai_corerev(&sii->pub);
928 928
929 /* get chipcommon chipstatus */ 929 /* get chipcommon chipstatus */
930 if (sii->pub.ccrev >= 11) 930 if (ai_get_ccrev(&sii->pub) >= 11)
931 sii->chipst = R_REG(&cc->chipstatus); 931 sii->chipst = R_REG(&cc->chipstatus);
932 932
933 /* get chipcommon capabilites */ 933 /* get chipcommon capabilites */
934 sii->pub.cccaps = R_REG(&cc->capabilities); 934 sii->pub.cccaps = R_REG(&cc->capabilities);
935 935
936 /* get pmu rev and caps */ 936 /* get pmu rev and caps */
937 if (sii->pub.cccaps & CC_CAP_PMU) { 937 if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
938 sii->pub.pmucaps = R_REG(&cc->pmucapabilities); 938 sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
939 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; 939 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
940 } 940 }
@@ -988,7 +988,7 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
988 } 988 }
989 989
990 /* fixup necessary chip/core configurations */ 990 /* fixup necessary chip/core configurations */
991 if (SI_FAST(sii)) { 991 if (SI_FAST(&sii->pub)) {
992 if (!sii->pch) { 992 if (!sii->pch) {
993 sii->pch = pcicore_init(&sii->pub, sii->pbus, 993 sii->pch = pcicore_init(&sii->pub, sii->pbus,
994 (__iomem void *)PCIEREGS(sii)); 994 (__iomem void *)PCIEREGS(sii));
@@ -1097,7 +1097,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
1097 ai_setcoreidx(sih, origidx); 1097 ai_setcoreidx(sih, origidx);
1098 1098
1099 /* PMU specific initializations */ 1099 /* PMU specific initializations */
1100 if (sih->cccaps & CC_CAP_PMU) { 1100 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
1101 u32 xtalfreq; 1101 u32 xtalfreq;
1102 si_pmu_init(sih); 1102 si_pmu_init(sih);
1103 si_pmu_chip_init(sih); 1103 si_pmu_chip_init(sih);
@@ -1115,15 +1115,15 @@ static struct si_info *ai_doattach(struct si_info *sii,
1115 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, gpiotimerval), 1115 ai_corereg(sih, SI_CC_IDX, offsetof(struct chipcregs, gpiotimerval),
1116 ~0, w); 1116 ~0, w);
1117 1117
1118 if (PCIE(sii)) 1118 if (PCIE(sih))
1119 pcicore_attach(sii->pch, SI_DOATTACH); 1119 pcicore_attach(sii->pch, SI_DOATTACH);
1120 1120
1121 if (sih->chip == BCM43224_CHIP_ID) { 1121 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
1122 /* 1122 /*
1123 * enable 12 mA drive strenth for 43224 and 1123 * enable 12 mA drive strenth for 43224 and
1124 * set chipControl register bit 15 1124 * set chipControl register bit 15
1125 */ 1125 */
1126 if (sih->chiprev == 0) { 1126 if (ai_get_chiprev(sih) == 0) {
1127 SI_MSG("Applying 43224A0 WARs\n"); 1127 SI_MSG("Applying 43224A0 WARs\n");
1128 ai_corereg(sih, SI_CC_IDX, 1128 ai_corereg(sih, SI_CC_IDX,
1129 offsetof(struct chipcregs, chipcontrol), 1129 offsetof(struct chipcregs, chipcontrol),
@@ -1132,14 +1132,14 @@ static struct si_info *ai_doattach(struct si_info *sii,
1132 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE, 1132 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
1133 CCTRL_43224A0_12MA_LED_DRIVE); 1133 CCTRL_43224A0_12MA_LED_DRIVE);
1134 } 1134 }
1135 if (sih->chiprev >= 1) { 1135 if (ai_get_chiprev(sih) >= 1) {
1136 SI_MSG("Applying 43224B0+ WARs\n"); 1136 SI_MSG("Applying 43224B0+ WARs\n");
1137 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE, 1137 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
1138 CCTRL_43224B0_12MA_LED_DRIVE); 1138 CCTRL_43224B0_12MA_LED_DRIVE);
1139 } 1139 }
1140 } 1140 }
1141 1141
1142 if (sih->chip == BCM4313_CHIP_ID) { 1142 if (ai_get_chip_id(sih) == BCM4313_CHIP_ID) {
1143 /* 1143 /*
1144 * enable 12 mA drive strenth for 4313 and 1144 * enable 12 mA drive strenth for 4313 and
1145 * set chipControl register bit 1 1145 * set chipControl register bit 1
@@ -1249,7 +1249,7 @@ uint ai_coreidx(struct si_pub *sih)
1249 1249
1250bool ai_backplane64(struct si_pub *sih) 1250bool ai_backplane64(struct si_pub *sih)
1251{ 1251{
1252 return (sih->cccaps & CC_CAP_BKPLN64) != 0; 1252 return (ai_get_cccaps(sih) & CC_CAP_BKPLN64) != 0;
1253} 1253}
1254 1254
1255/* return index of coreid or BADIDX if not found */ 1255/* return index of coreid or BADIDX if not found */
@@ -1299,7 +1299,7 @@ void __iomem *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
1299 1299
1300 sii = (struct si_info *)sih; 1300 sii = (struct si_info *)sih;
1301 1301
1302 if (SI_FAST(sii)) { 1302 if (SI_FAST(sih)) {
1303 /* Overloading the origidx variable to remember the coreid, 1303 /* Overloading the origidx variable to remember the coreid,
1304 * this works because the core ids cannot be confused with 1304 * this works because the core ids cannot be confused with
1305 * core indices. 1305 * core indices.
@@ -1307,7 +1307,7 @@ void __iomem *ai_switch_core(struct si_pub *sih, uint coreid, uint *origidx,
1307 *origidx = coreid; 1307 *origidx = coreid;
1308 if (coreid == CC_CORE_ID) 1308 if (coreid == CC_CORE_ID)
1309 return CCREGS_FAST(sii); 1309 return CCREGS_FAST(sii);
1310 else if (coreid == sih->buscoretype) 1310 else if (coreid == ai_get_buscoretype(sih))
1311 return PCIEREGS(sii); 1311 return PCIEREGS(sii);
1312 } 1312 }
1313 INTR_OFF(sii, *intr_val); 1313 INTR_OFF(sii, *intr_val);
@@ -1322,8 +1322,8 @@ void ai_restore_core(struct si_pub *sih, uint coreid, uint intr_val)
1322 struct si_info *sii; 1322 struct si_info *sii;
1323 1323
1324 sii = (struct si_info *)sih; 1324 sii = (struct si_info *)sih;
1325 if (SI_FAST(sii) 1325 if (SI_FAST(sih)
1326 && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype))) 1326 && ((coreid == CC_CORE_ID) || (coreid == ai_get_buscoretype(sih))))
1327 return; 1327 return;
1328 1328
1329 ai_setcoreidx(sih, coreid); 1329 ai_setcoreidx(sih, coreid);
@@ -1367,7 +1367,7 @@ uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
1367 * If pci/pcie, we can get at pci/pcie regs 1367 * If pci/pcie, we can get at pci/pcie regs
1368 * and on newer cores to chipc 1368 * and on newer cores to chipc
1369 */ 1369 */
1370 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) { 1370 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sih)) {
1371 /* Chipc registers are mapped at 12KB */ 1371 /* Chipc registers are mapped at 12KB */
1372 fast = true; 1372 fast = true;
1373 r = (u32 __iomem *)((__iomem char *)sii->curmap + 1373 r = (u32 __iomem *)((__iomem char *)sii->curmap +
@@ -1378,7 +1378,7 @@ uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
1378 * an 8KB window or, in pcie and pci rev 13 at 8KB 1378 * an 8KB window or, in pcie and pci rev 13 at 8KB
1379 */ 1379 */
1380 fast = true; 1380 fast = true;
1381 if (SI_FAST(sii)) 1381 if (SI_FAST(sih))
1382 r = (u32 __iomem *)((__iomem char *)sii->curmap + 1382 r = (u32 __iomem *)((__iomem char *)sii->curmap +
1383 PCI_16KB0_PCIREGS_OFFSET + regoff); 1383 PCI_16KB0_PCIREGS_OFFSET + regoff);
1384 else 1384 else
@@ -1480,13 +1480,13 @@ static uint ai_slowclk_src(struct si_info *sii)
1480 struct chipcregs __iomem *cc; 1480 struct chipcregs __iomem *cc;
1481 u32 val; 1481 u32 val;
1482 1482
1483 if (sii->pub.ccrev < 6) { 1483 if (ai_get_ccrev(&sii->pub) < 6) {
1484 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, 1484 pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
1485 &val); 1485 &val);
1486 if (val & PCI_CFG_GPIO_SCS) 1486 if (val & PCI_CFG_GPIO_SCS)
1487 return SCC_SS_PCI; 1487 return SCC_SS_PCI;
1488 return SCC_SS_XTAL; 1488 return SCC_SS_XTAL;
1489 } else if (sii->pub.ccrev < 10) { 1489 } else if (ai_get_ccrev(&sii->pub) < 10) {
1490 cc = (struct chipcregs __iomem *) 1490 cc = (struct chipcregs __iomem *)
1491 ai_setcoreidx(&sii->pub, sii->curidx); 1491 ai_setcoreidx(&sii->pub, sii->curidx);
1492 return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK; 1492 return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
@@ -1505,14 +1505,14 @@ static uint ai_slowclk_freq(struct si_info *sii, bool max_freq,
1505 uint div; 1505 uint div;
1506 1506
1507 slowclk = ai_slowclk_src(sii); 1507 slowclk = ai_slowclk_src(sii);
1508 if (sii->pub.ccrev < 6) { 1508 if (ai_get_ccrev(&sii->pub) < 6) {
1509 if (slowclk == SCC_SS_PCI) 1509 if (slowclk == SCC_SS_PCI)
1510 return max_freq ? (PCIMAXFREQ / 64) 1510 return max_freq ? (PCIMAXFREQ / 64)
1511 : (PCIMINFREQ / 64); 1511 : (PCIMINFREQ / 64);
1512 else 1512 else
1513 return max_freq ? (XTALMAXFREQ / 32) 1513 return max_freq ? (XTALMAXFREQ / 32)
1514 : (XTALMINFREQ / 32); 1514 : (XTALMINFREQ / 32);
1515 } else if (sii->pub.ccrev < 10) { 1515 } else if (ai_get_ccrev(&sii->pub) < 10) {
1516 div = 4 * 1516 div = 4 *
1517 (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> 1517 (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
1518 SCC_CD_SHIFT) + 1); 1518 SCC_CD_SHIFT) + 1);
@@ -1553,7 +1553,8 @@ ai_clkctl_setdelay(struct si_info *sii, struct chipcregs __iomem *cc)
1553 1553
1554 /* Starting with 4318 it is ILP that is used for the delays */ 1554 /* Starting with 4318 it is ILP that is used for the delays */
1555 slowmaxfreq = 1555 slowmaxfreq =
1556 ai_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc); 1556 ai_slowclk_freq(sii,
1557 (ai_get_ccrev(&sii->pub) >= 10) ? false : true, cc);
1557 1558
1558 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; 1559 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
1559 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; 1560 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
@@ -1570,11 +1571,11 @@ void ai_clkctl_init(struct si_pub *sih)
1570 struct chipcregs __iomem *cc; 1571 struct chipcregs __iomem *cc;
1571 bool fast; 1572 bool fast;
1572 1573
1573 if (!(sih->cccaps & CC_CAP_PWR_CTL)) 1574 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
1574 return; 1575 return;
1575 1576
1576 sii = (struct si_info *)sih; 1577 sii = (struct si_info *)sih;
1577 fast = SI_FAST(sii); 1578 fast = SI_FAST(sih);
1578 if (!fast) { 1579 if (!fast) {
1579 origidx = sii->curidx; 1580 origidx = sii->curidx;
1580 cc = (struct chipcregs __iomem *) 1581 cc = (struct chipcregs __iomem *)
@@ -1588,7 +1589,7 @@ void ai_clkctl_init(struct si_pub *sih)
1588 } 1589 }
1589 1590
1590 /* set all Instaclk chip ILP to 1 MHz */ 1591 /* set all Instaclk chip ILP to 1 MHz */
1591 if (sih->ccrev >= 10) 1592 if (ai_get_ccrev(sih) >= 10)
1592 SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, 1593 SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
1593 (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); 1594 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
1594 1595
@@ -1613,17 +1614,17 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
1613 bool fast; 1614 bool fast;
1614 1615
1615 sii = (struct si_info *)sih; 1616 sii = (struct si_info *)sih;
1616 if (sih->cccaps & CC_CAP_PMU) { 1617 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
1617 INTR_OFF(sii, intr_val); 1618 INTR_OFF(sii, intr_val);
1618 fpdelay = si_pmu_fast_pwrup_delay(sih); 1619 fpdelay = si_pmu_fast_pwrup_delay(sih);
1619 INTR_RESTORE(sii, intr_val); 1620 INTR_RESTORE(sii, intr_val);
1620 return fpdelay; 1621 return fpdelay;
1621 } 1622 }
1622 1623
1623 if (!(sih->cccaps & CC_CAP_PWR_CTL)) 1624 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
1624 return 0; 1625 return 0;
1625 1626
1626 fast = SI_FAST(sii); 1627 fast = SI_FAST(sih);
1627 fpdelay = 0; 1628 fpdelay = 0;
1628 if (!fast) { 1629 if (!fast) {
1629 origidx = sii->curidx; 1630 origidx = sii->curidx;
@@ -1659,7 +1660,7 @@ int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
1659 sii = (struct si_info *)sih; 1660 sii = (struct si_info *)sih;
1660 1661
1661 /* pcie core doesn't have any mapping to control the xtal pu */ 1662 /* pcie core doesn't have any mapping to control the xtal pu */
1662 if (PCIE(sii)) 1663 if (PCIE(sih))
1663 return -1; 1664 return -1;
1664 1665
1665 pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in); 1666 pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);
@@ -1720,10 +1721,10 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1720 struct chipcregs __iomem *cc; 1721 struct chipcregs __iomem *cc;
1721 u32 scc; 1722 u32 scc;
1722 uint intr_val = 0; 1723 uint intr_val = 0;
1723 bool fast = SI_FAST(sii); 1724 bool fast = SI_FAST(&sii->pub);
1724 1725
1725 /* chipcommon cores prior to rev6 don't support dynamic clock control */ 1726 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1726 if (sii->pub.ccrev < 6) 1727 if (ai_get_ccrev(&sii->pub) < 6)
1727 return false; 1728 return false;
1728 1729
1729 if (!fast) { 1730 if (!fast) {
@@ -1737,12 +1738,13 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1737 goto done; 1738 goto done;
1738 } 1739 }
1739 1740
1740 if (!(sii->pub.cccaps & CC_CAP_PWR_CTL) && (sii->pub.ccrev < 20)) 1741 if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
1742 (ai_get_ccrev(&sii->pub) < 20))
1741 goto done; 1743 goto done;
1742 1744
1743 switch (mode) { 1745 switch (mode) {
1744 case CLK_FAST: /* FORCEHT, fast (pll) clock */ 1746 case CLK_FAST: /* FORCEHT, fast (pll) clock */
1745 if (sii->pub.ccrev < 10) { 1747 if (ai_get_ccrev(&sii->pub) < 10) {
1746 /* 1748 /*
1747 * don't forget to force xtal back 1749 * don't forget to force xtal back
1748 * on before we clear SCC_DYN_XTAL.. 1750 * on before we clear SCC_DYN_XTAL..
@@ -1750,14 +1752,14 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1750 ai_clkctl_xtal(&sii->pub, XTAL, ON); 1752 ai_clkctl_xtal(&sii->pub, XTAL, ON);
1751 SET_REG(&cc->slow_clk_ctl, 1753 SET_REG(&cc->slow_clk_ctl,
1752 (SCC_XC | SCC_FS | SCC_IP), SCC_IP); 1754 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
1753 } else if (sii->pub.ccrev < 20) { 1755 } else if (ai_get_ccrev(&sii->pub) < 20) {
1754 OR_REG(&cc->system_clk_ctl, SYCC_HR); 1756 OR_REG(&cc->system_clk_ctl, SYCC_HR);
1755 } else { 1757 } else {
1756 OR_REG(&cc->clk_ctl_st, CCS_FORCEHT); 1758 OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
1757 } 1759 }
1758 1760
1759 /* wait for the PLL */ 1761 /* wait for the PLL */
1760 if (sii->pub.cccaps & CC_CAP_PMU) { 1762 if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
1761 u32 htavail = CCS_HTAVAIL; 1763 u32 htavail = CCS_HTAVAIL;
1762 SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail) 1764 SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
1763 == 0), PMU_MAX_TRANSITION_DLY); 1765 == 0), PMU_MAX_TRANSITION_DLY);
@@ -1767,7 +1769,7 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1767 break; 1769 break;
1768 1770
1769 case CLK_DYNAMIC: /* enable dynamic clock control */ 1771 case CLK_DYNAMIC: /* enable dynamic clock control */
1770 if (sii->pub.ccrev < 10) { 1772 if (ai_get_ccrev(&sii->pub) < 10) {
1771 scc = R_REG(&cc->slow_clk_ctl); 1773 scc = R_REG(&cc->slow_clk_ctl);
1772 scc &= ~(SCC_FS | SCC_IP | SCC_XC); 1774 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1773 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL) 1775 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
@@ -1780,7 +1782,7 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1780 */ 1782 */
1781 if (scc & SCC_XC) 1783 if (scc & SCC_XC)
1782 ai_clkctl_xtal(&sii->pub, XTAL, OFF); 1784 ai_clkctl_xtal(&sii->pub, XTAL, OFF);
1783 } else if (sii->pub.ccrev < 20) { 1785 } else if (ai_get_ccrev(&sii->pub) < 20) {
1784 /* Instaclock */ 1786 /* Instaclock */
1785 AND_REG(&cc->system_clk_ctl, ~SYCC_HR); 1787 AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
1786 } else { 1788 } else {
@@ -1815,10 +1817,10 @@ bool ai_clkctl_cc(struct si_pub *sih, uint mode)
1815 sii = (struct si_info *)sih; 1817 sii = (struct si_info *)sih;
1816 1818
1817 /* chipcommon cores prior to rev6 don't support dynamic clock control */ 1819 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1818 if (sih->ccrev < 6) 1820 if (ai_get_ccrev(sih) < 6)
1819 return false; 1821 return false;
1820 1822
1821 if (PCI_FORCEHT(sii)) 1823 if (PCI_FORCEHT(sih))
1822 return mode == CLK_FAST; 1824 return mode == CLK_FAST;
1823 1825
1824 return _ai_clkctl_cc(sii, mode); 1826 return _ai_clkctl_cc(sii, mode);
@@ -1851,10 +1853,10 @@ void ai_pci_up(struct si_pub *sih)
1851 1853
1852 sii = (struct si_info *)sih; 1854 sii = (struct si_info *)sih;
1853 1855
1854 if (PCI_FORCEHT(sii)) 1856 if (PCI_FORCEHT(sih))
1855 _ai_clkctl_cc(sii, CLK_FAST); 1857 _ai_clkctl_cc(sii, CLK_FAST);
1856 1858
1857 if (PCIE(sii)) 1859 if (PCIE(sih))
1858 pcicore_up(sii->pch, SI_PCIUP); 1860 pcicore_up(sii->pch, SI_PCIUP);
1859 1861
1860} 1862}
@@ -1877,7 +1879,7 @@ void ai_pci_down(struct si_pub *sih)
1877 sii = (struct si_info *)sih; 1879 sii = (struct si_info *)sih;
1878 1880
1879 /* release FORCEHT since chip is going to "down" state */ 1881 /* release FORCEHT since chip is going to "down" state */
1880 if (PCI_FORCEHT(sii)) 1882 if (PCI_FORCEHT(sih))
1881 _ai_clkctl_cc(sii, CLK_DYNAMIC); 1883 _ai_clkctl_cc(sii, CLK_DYNAMIC);
1882 1884
1883 pcicore_down(sii->pch, SI_PCIDOWN); 1885 pcicore_down(sii->pch, SI_PCIDOWN);
@@ -1896,7 +1898,7 @@ void ai_pci_setup(struct si_pub *sih, uint coremask)
1896 1898
1897 sii = (struct si_info *)sih; 1899 sii = (struct si_info *)sih;
1898 1900
1899 if (PCI(sii)) { 1901 if (PCI(sih)) {
1900 /* get current core index */ 1902 /* get current core index */
1901 idx = sii->curidx; 1903 idx = sii->curidx;
1902 1904
@@ -1911,7 +1913,7 @@ void ai_pci_setup(struct si_pub *sih, uint coremask)
1911 * Enable sb->pci interrupts. Assume 1913 * Enable sb->pci interrupts. Assume
1912 * PCI rev 2.3 support was added in pci core rev 6 and things changed.. 1914 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1913 */ 1915 */
1914 if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) { 1916 if (PCIE(sih) || (PCI(sih) && (ai_get_buscorerev(sih) >= 6))) {
1915 /* pci config write to set this core bit in PCIIntMask */ 1917 /* pci config write to set this core bit in PCIIntMask */
1916 pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w); 1918 pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);
1917 w |= (coremask << PCI_SBIM_SHIFT); 1919 w |= (coremask << PCI_SBIM_SHIFT);
@@ -1921,7 +1923,7 @@ void ai_pci_setup(struct si_pub *sih, uint coremask)
1921 ai_setint(sih, siflag); 1923 ai_setint(sih, siflag);
1922 } 1924 }
1923 1925
1924 if (PCI(sii)) { 1926 if (PCI(sih)) {
1925 pcicore_pci_setup(sii->pch, regs); 1927 pcicore_pci_setup(sii->pch, regs);
1926 1928
1927 /* switch back to previous core */ 1929 /* switch back to previous core */
@@ -1944,11 +1946,11 @@ int ai_pci_fixcfg(struct si_pub *sih)
1944 origidx = ai_coreidx(&sii->pub); 1946 origidx = ai_coreidx(&sii->pub);
1945 1947
1946 /* check 'pi' is correct and fix it if not */ 1948 /* check 'pi' is correct and fix it if not */
1947 regs = ai_setcore(&sii->pub, sii->pub.buscoretype, 0); 1949 regs = ai_setcore(&sii->pub, ai_get_buscoretype(sih), 0);
1948 if (sii->pub.buscoretype == PCIE_CORE_ID) 1950 if (ai_get_buscoretype(sih) == PCIE_CORE_ID)
1949 pcicore_fixcfg_pcie(sii->pch, 1951 pcicore_fixcfg_pcie(sii->pch,
1950 (struct sbpcieregs __iomem *)regs); 1952 (struct sbpcieregs __iomem *)regs);
1951 else if (sii->pub.buscoretype == PCI_CORE_ID) 1953 else if (ai_get_buscoretype(sih) == PCI_CORE_ID)
1952 pcicore_fixcfg_pci(sii->pch, (struct sbpciregs __iomem *)regs); 1954 pcicore_fixcfg_pci(sii->pch, (struct sbpciregs __iomem *)regs);
1953 1955
1954 /* restore the original index */ 1956 /* restore the original index */
@@ -1982,7 +1984,7 @@ void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
1982 val = R_REG(&cc->chipcontrol); 1984 val = R_REG(&cc->chipcontrol);
1983 1985
1984 if (on) { 1986 if (on) {
1985 if (sih->chippkg == 9 || sih->chippkg == 0xb) 1987 if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb)
1986 /* Ext PA Controls for 4331 12x9 Package */ 1988 /* Ext PA Controls for 4331 12x9 Package */
1987 W_REG(&cc->chipcontrol, val | 1989 W_REG(&cc->chipcontrol, val |
1988 CCTRL4331_EXTPA_EN | 1990 CCTRL4331_EXTPA_EN |
@@ -2037,12 +2039,12 @@ bool ai_is_sprom_available(struct si_pub *sih)
2037{ 2039{
2038 struct si_info *sii = (struct si_info *)sih; 2040 struct si_info *sii = (struct si_info *)sih;
2039 2041
2040 if (sih->ccrev >= 31) { 2042 if (ai_get_ccrev(sih) >= 31) {
2041 uint origidx; 2043 uint origidx;
2042 struct chipcregs __iomem *cc; 2044 struct chipcregs __iomem *cc;
2043 u32 sromctrl; 2045 u32 sromctrl;
2044 2046
2045 if ((sih->cccaps & CC_CAP_SROM) == 0) 2047 if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0)
2046 return false; 2048 return false;
2047 2049
2048 origidx = sii->curidx; 2050 origidx = sii->curidx;
@@ -2052,7 +2054,7 @@ bool ai_is_sprom_available(struct si_pub *sih)
2052 return sromctrl & SRC_PRESENT; 2054 return sromctrl & SRC_PRESENT;
2053 } 2055 }
2054 2056
2055 switch (sih->chip) { 2057 switch (ai_get_chip_id(sih)) {
2056 case BCM4313_CHIP_ID: 2058 case BCM4313_CHIP_ID:
2057 return (sii->chipst & CST4313_SPROM_PRESENT) != 0; 2059 return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
2058 default: 2060 default:
@@ -2064,7 +2066,7 @@ bool ai_is_otp_disabled(struct si_pub *sih)
2064{ 2066{
2065 struct si_info *sii = (struct si_info *)sih; 2067 struct si_info *sii = (struct si_info *)sih;
2066 2068
2067 switch (sih->chip) { 2069 switch (ai_get_chip_id(sih)) {
2068 case BCM4313_CHIP_ID: 2070 case BCM4313_CHIP_ID:
2069 return (sii->chipst & CST4313_OTP_PRESENT) == 0; 2071 return (sii->chipst & CST4313_OTP_PRESENT) == 0;
2070 /* These chips always have their OTP on */ 2072 /* These chips always have their OTP on */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
index f049179846e6..347b8a26f025 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
@@ -292,4 +292,50 @@ extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
292/* Enable Ex-PA for 4313 */ 292/* Enable Ex-PA for 4313 */
293extern void ai_epa_4313war(struct si_pub *sih); 293extern void ai_epa_4313war(struct si_pub *sih);
294 294
295static inline uint ai_get_buscoretype(struct si_pub *sih)
296{
297 return sih->buscoretype;
298}
299
300static inline uint ai_get_buscorerev(struct si_pub *sih)
301{
302 return sih->buscorerev;
303}
304static inline int ai_get_ccrev(struct si_pub *sih)
305{
306 return sih->ccrev;
307}
308static inline u32 ai_get_cccaps(struct si_pub *sih)
309{
310 return sih->cccaps;
311}
312static inline int ai_get_pmurev(struct si_pub *sih)
313{
314 return sih->pmurev;
315}
316static inline u32 ai_get_pmucaps(struct si_pub *sih)
317{
318 return sih->pmucaps;
319}
320static inline uint ai_get_boardtype(struct si_pub *sih)
321{
322 return sih->boardtype;
323}
324static inline uint ai_get_boardvendor(struct si_pub *sih)
325{
326 return sih->boardvendor;
327}
328static inline uint ai_get_chip_id(struct si_pub *sih)
329{
330 return sih->chip;
331}
332static inline uint ai_get_chiprev(struct si_pub *sih)
333{
334 return sih->chiprev;
335}
336static inline uint ai_get_chippkg(struct si_pub *sih)
337{
338 return sih->chippkg;
339}
340
295#endif /* _BRCM_AIUTILS_H_ */ 341#endif /* _BRCM_AIUTILS_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index 87f8f5d3d91f..ed8fcb40b518 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -1205,7 +1205,7 @@ static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1205/* control chip clock to save power, enable dynamic clock or force fast clock */ 1205/* control chip clock to save power, enable dynamic clock or force fast clock */
1206static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode) 1206static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1207{ 1207{
1208 if (wlc_hw->sih->cccaps & CC_CAP_PMU) { 1208 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1209 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock 1209 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1210 * on backplane, but mac core will still run on ALP(not HT) when 1210 * on backplane, but mac core will still run on ALP(not HT) when
1211 * it enters powersave mode, which means the FCA bit may not be 1211 * it enters powersave mode, which means the FCA bit may not be
@@ -1227,7 +1227,7 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1227 (&wlc_hw->regs-> 1227 (&wlc_hw->regs->
1228 clk_ctl_st) & CCS_HTAVAIL)); 1228 clk_ctl_st) & CCS_HTAVAIL));
1229 } else { 1229 } else {
1230 if ((wlc_hw->sih->pmurev == 0) && 1230 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1231 (R_REG 1231 (R_REG
1232 (&wlc_hw->regs-> 1232 (&wlc_hw->regs->
1233 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ))) 1233 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
@@ -1843,7 +1843,7 @@ static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1843 uint b2 = boardrev & 0xf; 1843 uint b2 = boardrev & 0xf;
1844 1844
1845 /* voards from other vendors are always considered valid */ 1845 /* voards from other vendors are always considered valid */
1846 if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM) 1846 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1847 return true; 1847 return true;
1848 1848
1849 /* do some boardrev sanity checks when boardvendor is Broadcom */ 1849 /* do some boardrev sanity checks when boardvendor is Broadcom */
@@ -1935,8 +1935,8 @@ static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1935 * AI chip doesn't restore bar0win2 on 1935 * AI chip doesn't restore bar0win2 on
1936 * hibernation/resume, need sw fixup 1936 * hibernation/resume, need sw fixup
1937 */ 1937 */
1938 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || 1938 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
1939 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) 1939 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
1940 wlc_hw->regs = (struct d11regs __iomem *) 1940 wlc_hw->regs = (struct d11regs __iomem *)
1941 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 1941 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
1942 ai_core_reset(wlc_hw->sih, flags, resetbits); 1942 ai_core_reset(wlc_hw->sih, flags, resetbits);
@@ -2034,7 +2034,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2034 2034
2035 brcms_c_mctrl_reset(wlc_hw); 2035 brcms_c_mctrl_reset(wlc_hw);
2036 2036
2037 if (wlc_hw->sih->cccaps & CC_CAP_PMU) 2037 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2038 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 2038 brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
2039 2039
2040 brcms_b_phy_reset(wlc_hw); 2040 brcms_b_phy_reset(wlc_hw);
@@ -2117,8 +2117,8 @@ void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2117{ 2117{
2118 struct d11regs __iomem *regs = wlc_hw->regs; 2118 struct d11regs __iomem *regs = wlc_hw->regs;
2119 2119
2120 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || 2120 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
2121 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) { 2121 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
2122 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */ 2122 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2123 W_REG(&regs->tsf_clk_frac_l, 0x2082); 2123 W_REG(&regs->tsf_clk_frac_l, 0x2082);
2124 W_REG(&regs->tsf_clk_frac_h, 0x8); 2124 W_REG(&regs->tsf_clk_frac_h, 0x8);
@@ -2805,7 +2805,7 @@ void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2805 regs = wlc_hw->regs; 2805 regs = wlc_hw->regs;
2806 2806
2807 if (on) { 2807 if (on) {
2808 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) { 2808 if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
2809 OR_REG(&regs->clk_ctl_st, 2809 OR_REG(&regs->clk_ctl_st,
2810 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL | 2810 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
2811 CCS_ERSRC_REQ_PHYPLL)); 2811 CCS_ERSRC_REQ_PHYPLL));
@@ -4530,8 +4530,9 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
4530 wlc_hw->boardrev = (u16) j; 4530 wlc_hw->boardrev = (u16) j;
4531 if (!brcms_c_validboardtype(wlc_hw)) { 4531 if (!brcms_c_validboardtype(wlc_hw)) {
4532 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom " 4532 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4533 "board type (0x%x)" " or revision level (0x%x)\n", 4533 "board type (0x%x)" " or revision level (0x%x)\n",
4534 unit, wlc_hw->sih->boardtype, wlc_hw->boardrev); 4534 unit, ai_get_boardtype(wlc_hw->sih),
4535 wlc_hw->boardrev);
4535 err = 15; 4536 err = 15;
4536 goto fail; 4537 goto fail;
4537 } 4538 }
@@ -4552,7 +4553,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
4552 else 4553 else
4553 wlc_hw->_nbands = 1; 4554 wlc_hw->_nbands = 1;
4554 4555
4555 if ((wlc_hw->sih->chip == BCM43225_CHIP_ID)) 4556 if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
4556 wlc_hw->_nbands = 1; 4557 wlc_hw->_nbands = 1;
4557 4558
4558 /* BMAC_NOTE: remove init of pub values when brcms_c_attach() 4559 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
@@ -4584,16 +4585,14 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
4584 sha_params.corerev = wlc_hw->corerev; 4585 sha_params.corerev = wlc_hw->corerev;
4585 sha_params.vid = wlc_hw->vendorid; 4586 sha_params.vid = wlc_hw->vendorid;
4586 sha_params.did = wlc_hw->deviceid; 4587 sha_params.did = wlc_hw->deviceid;
4587 sha_params.chip = wlc_hw->sih->chip; 4588 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4588 sha_params.chiprev = wlc_hw->sih->chiprev; 4589 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4589 sha_params.chippkg = wlc_hw->sih->chippkg; 4590 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4590 sha_params.sromrev = wlc_hw->sromrev; 4591 sha_params.sromrev = wlc_hw->sromrev;
4591 sha_params.boardtype = wlc_hw->sih->boardtype; 4592 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4592 sha_params.boardrev = wlc_hw->boardrev; 4593 sha_params.boardrev = wlc_hw->boardrev;
4593 sha_params.boardvendor = wlc_hw->sih->boardvendor;
4594 sha_params.boardflags = wlc_hw->boardflags; 4594 sha_params.boardflags = wlc_hw->boardflags;
4595 sha_params.boardflags2 = wlc_hw->boardflags2; 4595 sha_params.boardflags2 = wlc_hw->boardflags2;
4596 sha_params.buscorerev = wlc_hw->sih->buscorerev;
4597 4596
4598 /* alloc and save pointer to shared phy state area */ 4597 /* alloc and save pointer to shared phy state area */
4599 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params); 4598 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
@@ -4734,10 +4733,9 @@ static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
4734 goto fail; 4733 goto fail;
4735 } 4734 }
4736 4735
4737 BCMMSG(wlc->wiphy, 4736 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
4738 "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n", 4737 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih),
4739 wlc_hw->deviceid, wlc_hw->_nbands, 4738 macaddr);
4740 wlc_hw->sih->boardtype, macaddr);
4741 4739
4742 return err; 4740 return err;
4743 4741
@@ -5073,8 +5071,8 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5073 * AI chip doesn't restore bar0win2 on 5071 * AI chip doesn't restore bar0win2 on
5074 * hibernation/resume, need sw fixup 5072 * hibernation/resume, need sw fixup
5075 */ 5073 */
5076 if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) || 5074 if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
5077 (wlc_hw->sih->chip == BCM43225_CHIP_ID)) 5075 (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
5078 wlc_hw->regs = (struct d11regs __iomem *) 5076 wlc_hw->regs = (struct d11regs __iomem *)
5079 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0); 5077 ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
5080 5078
@@ -5088,7 +5086,7 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5088 wlc_hw->wlc->pub->hw_up = true; 5086 wlc_hw->wlc->pub->hw_up = true;
5089 5087
5090 if ((wlc_hw->boardflags & BFL_FEM) 5088 if ((wlc_hw->boardflags & BFL_FEM)
5091 && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) { 5089 && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
5092 if (! 5090 if (!
5093 (wlc_hw->boardrev >= 0x1250 5091 (wlc_hw->boardrev >= 0x1250
5094 && (wlc_hw->boardflags & BFL_FEM_BT))) 5092 && (wlc_hw->boardflags & BFL_FEM_BT)))
@@ -5183,7 +5181,7 @@ int brcms_c_up(struct brcms_c_info *wlc)
5183 } 5181 }
5184 5182
5185 if ((wlc->pub->boardflags & BFL_FEM) 5183 if ((wlc->pub->boardflags & BFL_FEM)
5186 && (wlc->pub->sih->chip == BCM4313_CHIP_ID)) { 5184 && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
5187 if (wlc->pub->boardrev >= 0x1250 5185 if (wlc->pub->boardrev >= 0x1250
5188 && (wlc->pub->boardflags & BFL_FEM_BT)) 5186 && (wlc->pub->boardflags & BFL_FEM_BT))
5189 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL, 5187 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
@@ -8210,11 +8208,11 @@ bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8210 8208
8211 if (macintstatus & MI_GP0) { 8209 if (macintstatus & MI_GP0) {
8212 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d " 8210 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
8213 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); 8211 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
8214 8212
8215 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", 8213 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
8216 __func__, wlc_hw->sih->chip, 8214 __func__, ai_get_chip_id(wlc_hw->sih),
8217 wlc_hw->sih->chiprev); 8215 ai_get_chiprev(wlc_hw->sih));
8218 brcms_fatal_error(wlc_hw->wlc->wl); 8216 brcms_fatal_error(wlc_hw->wlc->wl);
8219 } 8217 }
8220 8218
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
index 0bcb26792046..2e8b5a19ace7 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
@@ -224,9 +224,9 @@ struct pcicore_info {
224}; 224};
225 225
226#define PCIE_ASPM(sih) \ 226#define PCIE_ASPM(sih) \
227 (((sih)->buscoretype == PCIE_CORE_ID) && \ 227 ((ai_get_buscoretype(sih) == PCIE_CORE_ID) && \
228 (((sih)->buscorerev >= 3) && \ 228 ((ai_get_buscorerev(sih) >= 3) && \
229 ((sih)->buscorerev <= 5))) 229 (ai_get_buscorerev(sih) <= 5)))
230 230
231 231
232/* delay needed between the mdio control/ mdiodata register data access */ 232/* delay needed between the mdio control/ mdiodata register data access */
@@ -251,7 +251,7 @@ struct pcicore_info *pcicore_init(struct si_pub *sih, struct pci_dev *pdev,
251 pi->sih = sih; 251 pi->sih = sih;
252 pi->dev = pdev; 252 pi->dev = pdev;
253 253
254 if (sih->buscoretype == PCIE_CORE_ID) { 254 if (ai_get_buscoretype(sih) == PCIE_CORE_ID) {
255 u8 cap_ptr; 255 u8 cap_ptr;
256 pi->regs.pcieregs = regs; 256 pi->regs.pcieregs = regs;
257 cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP, 257 cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
@@ -504,7 +504,8 @@ static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
504 struct si_pub *sih = pi->sih; 504 struct si_pub *sih = pi->sih;
505 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs; 505 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
506 506
507 if (sih->buscoretype != PCIE_CORE_ID || sih->buscorerev < 7) 507 if (ai_get_buscoretype(sih) != PCIE_CORE_ID ||
508 ai_get_buscorerev(sih) < 7)
508 return; 509 return;
509 510
510 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG); 511 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
@@ -527,7 +528,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
527 pcie_clkreq(pi, 1, 0); 528 pcie_clkreq(pi, 1, 0);
528 break; 529 break;
529 case SI_PCIDOWN: 530 case SI_PCIDOWN:
530 if (sih->buscorerev == 6) { /* turn on serdes PLL down */ 531 /* turn on serdes PLL down */
532 if (ai_get_buscorerev(sih) == 6) {
531 ai_corereg(sih, SI_CC_IDX, 533 ai_corereg(sih, SI_CC_IDX,
532 offsetof(struct chipcregs, chipcontrol_addr), 534 offsetof(struct chipcregs, chipcontrol_addr),
533 ~0, 0); 535 ~0, 0);
@@ -539,7 +541,8 @@ static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
539 } 541 }
540 break; 542 break;
541 case SI_PCIUP: 543 case SI_PCIUP:
542 if (sih->buscorerev == 6) { /* turn off serdes PLL down */ 544 /* turn off serdes PLL down */
545 if (ai_get_buscorerev(sih) == 6) {
543 ai_corereg(sih, SI_CC_IDX, 546 ai_corereg(sih, SI_CC_IDX,
544 offsetof(struct chipcregs, chipcontrol_addr), 547 offsetof(struct chipcregs, chipcontrol_addr),
545 ~0, 0); 548 ~0, 0);
@@ -678,7 +681,7 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
678 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs; 681 struct sbpcieregs __iomem *pcieregs = pi->regs.pcieregs;
679 u32 w; 682 u32 w;
680 683
681 if (sih->buscorerev == 0 || sih->buscorerev == 1) { 684 if (ai_get_buscorerev(sih) == 0 || ai_get_buscorerev(sih) == 1) {
682 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, 685 w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
683 PCIE_TLP_WORKAROUNDSREG); 686 PCIE_TLP_WORKAROUNDSREG);
684 w |= 0x8; 687 w |= 0x8;
@@ -686,13 +689,13 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
686 PCIE_TLP_WORKAROUNDSREG, w); 689 PCIE_TLP_WORKAROUNDSREG, w);
687 } 690 }
688 691
689 if (sih->buscorerev == 1) { 692 if (ai_get_buscorerev(sih) == 1) {
690 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG); 693 w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
691 w |= 0x40; 694 w |= 0x40;
692 pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w); 695 pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
693 } 696 }
694 697
695 if (sih->buscorerev == 0) { 698 if (ai_get_buscorerev(sih) == 0) {
696 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128); 699 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
697 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100); 700 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
698 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466); 701 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
@@ -708,13 +711,13 @@ static void pcie_war_pci_setup(struct pcicore_info *pi)
708 pcie_war_serdes(pi); 711 pcie_war_serdes(pi);
709 712
710 pcie_war_aspm_clkreq(pi); 713 pcie_war_aspm_clkreq(pi);
711 } else if (pi->sih->buscorerev == 7) 714 } else if (ai_get_buscorerev(pi->sih) == 7)
712 pcie_war_noplldown(pi); 715 pcie_war_noplldown(pi);
713 716
714 /* Note that the fix is actually in the SROM, 717 /* Note that the fix is actually in the SROM,
715 * that's why this is open-ended 718 * that's why this is open-ended
716 */ 719 */
717 if (pi->sih->buscorerev >= 6) 720 if (ai_get_buscorerev(pi->sih) >= 6)
718 pcie_misc_config_fixup(pi); 721 pcie_misc_config_fixup(pi);
719} 722}
720 723
@@ -745,7 +748,7 @@ void pcicore_attach(struct pcicore_info *pi, int state)
745 748
746void pcicore_hwup(struct pcicore_info *pi) 749void pcicore_hwup(struct pcicore_info *pi)
747{ 750{
748 if (!pi || pi->sih->buscoretype != PCIE_CORE_ID) 751 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
749 return; 752 return;
750 753
751 pcie_war_pci_setup(pi); 754 pcie_war_pci_setup(pi);
@@ -753,7 +756,7 @@ void pcicore_hwup(struct pcicore_info *pi)
753 756
754void pcicore_up(struct pcicore_info *pi, int state) 757void pcicore_up(struct pcicore_info *pi, int state)
755{ 758{
756 if (!pi || pi->sih->buscoretype != PCIE_CORE_ID) 759 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
757 return; 760 return;
758 761
759 /* Restore L1 timer for better performance */ 762 /* Restore L1 timer for better performance */
@@ -781,7 +784,7 @@ void pcicore_sleep(struct pcicore_info *pi)
781 784
782void pcicore_down(struct pcicore_info *pi, int state) 785void pcicore_down(struct pcicore_info *pi, int state)
783{ 786{
784 if (!pi || pi->sih->buscoretype != PCIE_CORE_ID) 787 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
785 return; 788 return;
786 789
787 pcie_clkreq_upd(pi, state); 790 pcie_clkreq_upd(pi, state);
@@ -826,7 +829,7 @@ pcicore_pci_setup(struct pcicore_info *pi, struct sbpciregs __iomem *pciregs)
826 829
827 OR_REG(&pciregs->sbtopci2, SBTOPCI_PREF | SBTOPCI_BURST); 830 OR_REG(&pciregs->sbtopci2, SBTOPCI_PREF | SBTOPCI_BURST);
828 831
829 if (((struct si_info *)(pi->sih))->pub.buscorerev >= 11) { 832 if (ai_get_buscorerev(pi->sih) >= 11) {
830 OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI); 833 OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
831 w = R_REG(&pciregs->clkrun); 834 w = R_REG(&pciregs->clkrun);
832 W_REG(&pciregs->clkrun, w | PCI_CLKRUN_DSBL); 835 W_REG(&pciregs->clkrun, w | PCI_CLKRUN_DSBL);
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/otp.c b/drivers/net/wireless/brcm80211/brcmsmac/otp.c
index edf551561fd8..612434ea952f 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/otp.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/otp.c
@@ -146,7 +146,7 @@ static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
146{ 146{
147 int ret = 0; 147 int ret = 0;
148 148
149 switch (sih->chip) { 149 switch (ai_get_chip_id(sih)) {
150 case BCM43224_CHIP_ID: 150 case BCM43224_CHIP_ID:
151 case BCM43225_CHIP_ID: 151 case BCM43225_CHIP_ID:
152 ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM; 152 ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
@@ -170,10 +170,10 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
170 * record word offset of General Use Region 170 * record word offset of General Use Region
171 * for various chipcommon revs 171 * for various chipcommon revs
172 */ 172 */
173 if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24 173 if (oi->ccrev == 21 || oi->ccrev == 24
174 || oi->sih->ccrev == 27) { 174 || oi->ccrev == 27) {
175 oi->otpgu_base = REVA4_OTPGU_BASE; 175 oi->otpgu_base = REVA4_OTPGU_BASE;
176 } else if (oi->sih->ccrev == 36) { 176 } else if (oi->ccrev == 36) {
177 /* 177 /*
178 * OTP size greater than equal to 2KB (128 words), 178 * OTP size greater than equal to 2KB (128 words),
179 * otpgu_base is similar to rev23 179 * otpgu_base is similar to rev23
@@ -182,7 +182,7 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
182 oi->otpgu_base = REVB8_OTPGU_BASE; 182 oi->otpgu_base = REVB8_OTPGU_BASE;
183 else 183 else
184 oi->otpgu_base = REV36_OTPGU_BASE; 184 oi->otpgu_base = REV36_OTPGU_BASE;
185 } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) { 185 } else if (oi->ccrev == 23 || oi->ccrev >= 25) {
186 oi->otpgu_base = REVB8_OTPGU_BASE; 186 oi->otpgu_base = REVB8_OTPGU_BASE;
187 } 187 }
188 188
@@ -201,8 +201,8 @@ static void _ipxotp_init(struct otpinfo *oi, struct chipcregs __iomem *cc)
201 /* Read OTP lock bits and subregion programmed indication bits */ 201 /* Read OTP lock bits and subregion programmed indication bits */
202 oi->status = R_REG(&cc->otpstatus); 202 oi->status = R_REG(&cc->otpstatus);
203 203
204 if ((oi->sih->chip == BCM43224_CHIP_ID) 204 if ((ai_get_chip_id(oi->sih) == BCM43224_CHIP_ID)
205 || (oi->sih->chip == BCM43225_CHIP_ID)) { 205 || (ai_get_chip_id(oi->sih) == BCM43225_CHIP_ID)) {
206 u32 p_bits; 206 u32 p_bits;
207 p_bits = 207 p_bits =
208 (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) & 208 (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
@@ -244,7 +244,7 @@ static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
244 struct chipcregs __iomem *cc; 244 struct chipcregs __iomem *cc;
245 245
246 /* Make sure we're running IPX OTP */ 246 /* Make sure we're running IPX OTP */
247 if (!OTPTYPE_IPX(sih->ccrev)) 247 if (!OTPTYPE_IPX(oi->ccrev))
248 return -EBADE; 248 return -EBADE;
249 249
250 /* Make sure OTP is not disabled */ 250 /* Make sure OTP is not disabled */
@@ -252,7 +252,7 @@ static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
252 return -EBADE; 252 return -EBADE;
253 253
254 /* Check for otp size */ 254 /* Check for otp size */
255 switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) { 255 switch ((ai_get_cccaps(sih) & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
256 case 0: 256 case 0:
257 /* Nothing there */ 257 /* Nothing there */
258 return -EBADE; 258 return -EBADE;
@@ -389,7 +389,7 @@ static int otp_init(struct si_pub *sih, struct otpinfo *oi)
389 389
390 memset(oi, 0, sizeof(struct otpinfo)); 390 memset(oi, 0, sizeof(struct otpinfo));
391 391
392 oi->ccrev = sih->ccrev; 392 oi->ccrev = ai_get_ccrev(sih);
393 393
394 if (OTPTYPE_IPX(oi->ccrev)) 394 if (OTPTYPE_IPX(oi->ccrev))
395 oi->fn = &ipxotp_fn; 395 oi->fn = &ipxotp_fn;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
index 008aab9c777c..30cc558dbadc 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
@@ -404,10 +404,8 @@ struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
404 sh->sromrev = shp->sromrev; 404 sh->sromrev = shp->sromrev;
405 sh->boardtype = shp->boardtype; 405 sh->boardtype = shp->boardtype;
406 sh->boardrev = shp->boardrev; 406 sh->boardrev = shp->boardrev;
407 sh->boardvendor = shp->boardvendor;
408 sh->boardflags = shp->boardflags; 407 sh->boardflags = shp->boardflags;
409 sh->boardflags2 = shp->boardflags2; 408 sh->boardflags2 = shp->boardflags2;
410 sh->buscorerev = shp->buscorerev;
411 409
412 sh->fast_timer = PHY_SW_TIMER_FAST; 410 sh->fast_timer = PHY_SW_TIMER_FAST;
413 sh->slow_timer = PHY_SW_TIMER_SLOW; 411 sh->slow_timer = PHY_SW_TIMER_SLOW;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h
index 96e15163222b..5549c7b0cfd6 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h
@@ -166,7 +166,6 @@ struct shared_phy_params {
166 struct phy_shim_info *physhim; 166 struct phy_shim_info *physhim;
167 uint unit; 167 uint unit;
168 uint corerev; 168 uint corerev;
169 uint buscorerev;
170 u16 vid; 169 u16 vid;
171 u16 did; 170 u16 did;
172 uint chip; 171 uint chip;
@@ -175,7 +174,6 @@ struct shared_phy_params {
175 uint sromrev; 174 uint sromrev;
176 uint boardtype; 175 uint boardtype;
177 uint boardrev; 176 uint boardrev;
178 uint boardvendor;
179 u32 boardflags; 177 u32 boardflags;
180 u32 boardflags2; 178 u32 boardflags2;
181}; 179};
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
index 5f9478b1c993..02e640723a9c 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
@@ -503,10 +503,8 @@ struct shared_phy {
503 uint sromrev; 503 uint sromrev;
504 uint boardtype; 504 uint boardtype;
505 uint boardrev; 505 uint boardrev;
506 uint boardvendor;
507 u32 boardflags; 506 u32 boardflags;
508 u32 boardflags2; 507 u32 boardflags2;
509 uint buscorerev;
510 uint fast_timer; 508 uint fast_timer;
511 uint slow_timer; 509 uint slow_timer;
512 uint glacial_timer; 510 uint glacial_timer;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
index 12ba575f5785..d4e909a6f2ab 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
@@ -115,10 +115,10 @@ static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
115 uint rsrcs; 115 uint rsrcs;
116 116
117 /* # resources */ 117 /* # resources */
118 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; 118 rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
119 119
120 /* determine min/max rsrc masks */ 120 /* determine min/max rsrc masks */
121 switch (sih->chip) { 121 switch (ai_get_chip_id(sih)) {
122 case BCM43224_CHIP_ID: 122 case BCM43224_CHIP_ID:
123 case BCM43225_CHIP_ID: 123 case BCM43225_CHIP_ID:
124 /* ??? */ 124 /* ??? */
@@ -145,7 +145,7 @@ si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
145{ 145{
146 u32 tmp = 0; 146 u32 tmp = 0;
147 147
148 switch (sih->chip) { 148 switch (ai_get_chip_id(sih)) {
149 case BCM43224_CHIP_ID: 149 case BCM43224_CHIP_ID:
150 case BCM43225_CHIP_ID: 150 case BCM43225_CHIP_ID:
151 if (spuravoid == 1) { 151 if (spuravoid == 1) {
@@ -207,7 +207,7 @@ u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
207{ 207{
208 uint delay = PMU_MAX_TRANSITION_DLY; 208 uint delay = PMU_MAX_TRANSITION_DLY;
209 209
210 switch (sih->chip) { 210 switch (ai_get_chip_id(sih)) {
211 case BCM43224_CHIP_ID: 211 case BCM43224_CHIP_ID:
212 case BCM43225_CHIP_ID: 212 case BCM43225_CHIP_ID:
213 case BCM4313_CHIP_ID: 213 case BCM4313_CHIP_ID:
@@ -276,10 +276,10 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
276 u32 clock = ALP_CLOCK; 276 u32 clock = ALP_CLOCK;
277 277
278 /* bail out with default */ 278 /* bail out with default */
279 if (!(sih->cccaps & CC_CAP_PMU)) 279 if (!(ai_get_cccaps(sih) & CC_CAP_PMU))
280 return clock; 280 return clock;
281 281
282 switch (sih->chip) { 282 switch (ai_get_chip_id(sih)) {
283 case BCM43224_CHIP_ID: 283 case BCM43224_CHIP_ID:
284 case BCM43225_CHIP_ID: 284 case BCM43225_CHIP_ID:
285 case BCM4313_CHIP_ID: 285 case BCM4313_CHIP_ID:
@@ -319,9 +319,9 @@ void si_pmu_init(struct si_pub *sih)
319 origidx = ai_coreidx(sih); 319 origidx = ai_coreidx(sih);
320 cc = ai_setcoreidx(sih, SI_CC_IDX); 320 cc = ai_setcoreidx(sih, SI_CC_IDX);
321 321
322 if (sih->pmurev == 1) 322 if (ai_get_pmurev(sih) == 1)
323 AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT); 323 AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
324 else if (sih->pmurev >= 2) 324 else if (ai_get_pmurev(sih) >= 2)
325 OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT); 325 OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
326 326
327 /* Return to original core */ 327 /* Return to original core */
@@ -358,7 +358,7 @@ void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
358 origidx = ai_coreidx(sih); 358 origidx = ai_coreidx(sih);
359 cc = ai_setcoreidx(sih, SI_CC_IDX); 359 cc = ai_setcoreidx(sih, SI_CC_IDX);
360 360
361 switch (sih->chip) { 361 switch (ai_get_chip_id(sih)) {
362 case BCM4313_CHIP_ID: 362 case BCM4313_CHIP_ID:
363 case BCM43224_CHIP_ID: 363 case BCM43224_CHIP_ID:
364 case BCM43225_CHIP_ID: 364 case BCM43225_CHIP_ID:
@@ -411,7 +411,7 @@ u32 si_pmu_measure_alpclk(struct si_pub *sih)
411 uint origidx; 411 uint origidx;
412 u32 alp_khz; 412 u32 alp_khz;
413 413
414 if (sih->pmurev < 10) 414 if (ai_get_pmurev(sih) < 10)
415 return 0; 415 return 0;
416 416
417 /* Remember original core before switch to chipc */ 417 /* Remember original core before switch to chipc */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.c b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
index b6987ea9fc68..95eb620fc7f0 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
@@ -589,9 +589,9 @@ static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
589static u8 __iomem * 589static u8 __iomem *
590srom_window_address(struct si_pub *sih, u8 __iomem *curmap) 590srom_window_address(struct si_pub *sih, u8 __iomem *curmap)
591{ 591{
592 if (sih->ccrev < 32) 592 if (ai_get_ccrev(sih) < 32)
593 return curmap + PCI_BAR0_SPROM_OFFSET; 593 return curmap + PCI_BAR0_SPROM_OFFSET;
594 if (sih->cccaps & CC_CAP_SROM) 594 if (ai_get_cccaps(sih) & CC_CAP_SROM)
595 return curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP; 595 return curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP;
596 596
597 return NULL; 597 return NULL;
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 19:54:32 -0400