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authorMike Frysinger <vapier@gentoo.org>2011-05-23 08:17:09 -0400
committerDavid S. Miller <davem@davemloft.net>2011-05-24 01:13:11 -0400
commit229de618ba6ff36e382b908b7637fe56c25ae9f1 (patch)
treeb9896ce90de6c2138dc9d8966507454d614c456d /drivers/net
parent6ac3f6649223d916bbdf1e823926f8f3b34b5d99 (diff)
net/irda: convert bfin_sir to common Blackfin UART header
No need to duplicate these defines now that the common Blackfin code has unified these for all UART devices. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Cc: Samuel Ortiz <samuel@sortiz.org> Cc: David Miller <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/irda/bfin_sir.c59
-rw-r--r--drivers/net/irda/bfin_sir.h63
2 files changed, 33 insertions, 89 deletions
diff --git a/drivers/net/irda/bfin_sir.c b/drivers/net/irda/bfin_sir.c
index f940dfa1f7f8..9d4ce1aba10c 100644
--- a/drivers/net/irda/bfin_sir.c
+++ b/drivers/net/irda/bfin_sir.c
@@ -67,27 +67,27 @@ static void bfin_sir_stop_tx(struct bfin_sir_port *port)
67 disable_dma(port->tx_dma_channel); 67 disable_dma(port->tx_dma_channel);
68#endif 68#endif
69 69
70 while (!(SIR_UART_GET_LSR(port) & THRE)) { 70 while (!(UART_GET_LSR(port) & THRE)) {
71 cpu_relax(); 71 cpu_relax();
72 continue; 72 continue;
73 } 73 }
74 74
75 SIR_UART_STOP_TX(port); 75 UART_CLEAR_IER(port, ETBEI);
76} 76}
77 77
78static void bfin_sir_enable_tx(struct bfin_sir_port *port) 78static void bfin_sir_enable_tx(struct bfin_sir_port *port)
79{ 79{
80 SIR_UART_ENABLE_TX(port); 80 UART_SET_IER(port, ETBEI);
81} 81}
82 82
83static void bfin_sir_stop_rx(struct bfin_sir_port *port) 83static void bfin_sir_stop_rx(struct bfin_sir_port *port)
84{ 84{
85 SIR_UART_STOP_RX(port); 85 UART_CLEAR_IER(port, ERBFI);
86} 86}
87 87
88static void bfin_sir_enable_rx(struct bfin_sir_port *port) 88static void bfin_sir_enable_rx(struct bfin_sir_port *port)
89{ 89{
90 SIR_UART_ENABLE_RX(port); 90 UART_SET_IER(port, ERBFI);
91} 91}
92 92
93static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed) 93static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
@@ -116,7 +116,7 @@ static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
116 116
117 do { 117 do {
118 udelay(utime); 118 udelay(utime);
119 lsr = SIR_UART_GET_LSR(port); 119 lsr = UART_GET_LSR(port);
120 } while (!(lsr & TEMT) && count--); 120 } while (!(lsr & TEMT) && count--);
121 121
122 /* The useconds for 1 bits to transmit */ 122 /* The useconds for 1 bits to transmit */
@@ -125,27 +125,27 @@ static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
125 /* Clear UCEN bit to reset the UART state machine 125 /* Clear UCEN bit to reset the UART state machine
126 * and control registers 126 * and control registers
127 */ 127 */
128 val = SIR_UART_GET_GCTL(port); 128 val = UART_GET_GCTL(port);
129 val &= ~UCEN; 129 val &= ~UCEN;
130 SIR_UART_PUT_GCTL(port, val); 130 UART_PUT_GCTL(port, val);
131 131
132 /* Set DLAB in LCR to Access THR RBR IER */ 132 /* Set DLAB in LCR to Access THR RBR IER */
133 SIR_UART_SET_DLAB(port); 133 UART_SET_DLAB(port);
134 SSYNC(); 134 SSYNC();
135 135
136 SIR_UART_PUT_DLL(port, quot & 0xFF); 136 UART_PUT_DLL(port, quot & 0xFF);
137 SIR_UART_PUT_DLH(port, (quot >> 8) & 0xFF); 137 UART_PUT_DLH(port, (quot >> 8) & 0xFF);
138 SSYNC(); 138 SSYNC();
139 139
140 /* Clear DLAB in LCR */ 140 /* Clear DLAB in LCR */
141 SIR_UART_CLEAR_DLAB(port); 141 UART_CLEAR_DLAB(port);
142 SSYNC(); 142 SSYNC();
143 143
144 SIR_UART_PUT_LCR(port, lcr); 144 UART_PUT_LCR(port, lcr);
145 145
146 val = SIR_UART_GET_GCTL(port); 146 val = UART_GET_GCTL(port);
147 val |= UCEN; 147 val |= UCEN;
148 SIR_UART_PUT_GCTL(port, val); 148 UART_PUT_GCTL(port, val);
149 149
150 ret = 0; 150 ret = 0;
151 break; 151 break;
@@ -154,12 +154,12 @@ static int bfin_sir_set_speed(struct bfin_sir_port *port, int speed)
154 break; 154 break;
155 } 155 }
156 156
157 val = SIR_UART_GET_GCTL(port); 157 val = UART_GET_GCTL(port);
158 /* If not add the 'RPOLC', we can't catch the receive interrupt. 158 /* If not add the 'RPOLC', we can't catch the receive interrupt.
159 * It's related with the HW layout and the IR transiver. 159 * It's related with the HW layout and the IR transiver.
160 */ 160 */
161 val |= IREN | RPOLC; 161 val |= IREN | RPOLC;
162 SIR_UART_PUT_GCTL(port, val); 162 UART_PUT_GCTL(port, val);
163 return ret; 163 return ret;
164} 164}
165 165
@@ -168,7 +168,7 @@ static int bfin_sir_is_receiving(struct net_device *dev)
168 struct bfin_sir_self *self = netdev_priv(dev); 168 struct bfin_sir_self *self = netdev_priv(dev);
169 struct bfin_sir_port *port = self->sir_port; 169 struct bfin_sir_port *port = self->sir_port;
170 170
171 if (!(SIR_UART_GET_IER(port) & ERBFI)) 171 if (!(UART_GET_IER(port) & ERBFI))
172 return 0; 172 return 0;
173 return self->rx_buff.state != OUTSIDE_FRAME; 173 return self->rx_buff.state != OUTSIDE_FRAME;
174} 174}
@@ -182,7 +182,7 @@ static void bfin_sir_tx_chars(struct net_device *dev)
182 182
183 if (self->tx_buff.len != 0) { 183 if (self->tx_buff.len != 0) {
184 chr = *(self->tx_buff.data); 184 chr = *(self->tx_buff.data);
185 SIR_UART_PUT_CHAR(port, chr); 185 UART_PUT_CHAR(port, chr);
186 self->tx_buff.data++; 186 self->tx_buff.data++;
187 self->tx_buff.len--; 187 self->tx_buff.len--;
188 } else { 188 } else {
@@ -206,8 +206,8 @@ static void bfin_sir_rx_chars(struct net_device *dev)
206 struct bfin_sir_port *port = self->sir_port; 206 struct bfin_sir_port *port = self->sir_port;
207 unsigned char ch; 207 unsigned char ch;
208 208
209 SIR_UART_CLEAR_LSR(port); 209 UART_CLEAR_LSR(port);
210 ch = SIR_UART_GET_CHAR(port); 210 ch = UART_GET_CHAR(port);
211 async_unwrap_char(dev, &self->stats, &self->rx_buff, ch); 211 async_unwrap_char(dev, &self->stats, &self->rx_buff, ch);
212 dev->last_rx = jiffies; 212 dev->last_rx = jiffies;
213} 213}
@@ -219,7 +219,7 @@ static irqreturn_t bfin_sir_rx_int(int irq, void *dev_id)
219 struct bfin_sir_port *port = self->sir_port; 219 struct bfin_sir_port *port = self->sir_port;
220 220
221 spin_lock(&self->lock); 221 spin_lock(&self->lock);
222 while ((SIR_UART_GET_LSR(port) & DR)) 222 while ((UART_GET_LSR(port) & DR))
223 bfin_sir_rx_chars(dev); 223 bfin_sir_rx_chars(dev);
224 spin_unlock(&self->lock); 224 spin_unlock(&self->lock);
225 225
@@ -233,7 +233,7 @@ static irqreturn_t bfin_sir_tx_int(int irq, void *dev_id)
233 struct bfin_sir_port *port = self->sir_port; 233 struct bfin_sir_port *port = self->sir_port;
234 234
235 spin_lock(&self->lock); 235 spin_lock(&self->lock);
236 if (SIR_UART_GET_LSR(port) & THRE) 236 if (UART_GET_LSR(port) & THRE)
237 bfin_sir_tx_chars(dev); 237 bfin_sir_tx_chars(dev);
238 spin_unlock(&self->lock); 238 spin_unlock(&self->lock);
239 239
@@ -312,7 +312,7 @@ static void bfin_sir_dma_rx_chars(struct net_device *dev)
312 struct bfin_sir_port *port = self->sir_port; 312 struct bfin_sir_port *port = self->sir_port;
313 int i; 313 int i;
314 314
315 SIR_UART_CLEAR_LSR(port); 315 UART_CLEAR_LSR(port);
316 316
317 for (i = port->rx_dma_buf.head; i < port->rx_dma_buf.tail; i++) 317 for (i = port->rx_dma_buf.head; i < port->rx_dma_buf.tail; i++)
318 async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]); 318 async_unwrap_char(dev, &self->stats, &self->rx_buff, port->rx_dma_buf.buf[i]);
@@ -430,11 +430,10 @@ static void bfin_sir_shutdown(struct bfin_sir_port *port, struct net_device *dev
430 unsigned short val; 430 unsigned short val;
431 431
432 bfin_sir_stop_rx(port); 432 bfin_sir_stop_rx(port);
433 SIR_UART_DISABLE_INTS(port);
434 433
435 val = SIR_UART_GET_GCTL(port); 434 val = UART_GET_GCTL(port);
436 val &= ~(UCEN | IREN | RPOLC); 435 val &= ~(UCEN | IREN | RPOLC);
437 SIR_UART_PUT_GCTL(port, val); 436 UART_PUT_GCTL(port, val);
438 437
439#ifdef CONFIG_SIR_BFIN_DMA 438#ifdef CONFIG_SIR_BFIN_DMA
440 disable_dma(port->tx_dma_channel); 439 disable_dma(port->tx_dma_channel);
@@ -518,12 +517,12 @@ static void bfin_sir_send_work(struct work_struct *work)
518 * sending data. We also can set the speed, which will 517 * sending data. We also can set the speed, which will
519 * reset all the UART. 518 * reset all the UART.
520 */ 519 */
521 val = SIR_UART_GET_GCTL(port); 520 val = UART_GET_GCTL(port);
522 val &= ~(IREN | RPOLC); 521 val &= ~(IREN | RPOLC);
523 SIR_UART_PUT_GCTL(port, val); 522 UART_PUT_GCTL(port, val);
524 SSYNC(); 523 SSYNC();
525 val |= IREN | RPOLC; 524 val |= IREN | RPOLC;
526 SIR_UART_PUT_GCTL(port, val); 525 UART_PUT_GCTL(port, val);
527 SSYNC(); 526 SSYNC();
528 /* bfin_sir_set_speed(port, self->speed); */ 527 /* bfin_sir_set_speed(port, self->speed); */
529 528
diff --git a/drivers/net/irda/bfin_sir.h b/drivers/net/irda/bfin_sir.h
index e3b285a67734..29cbde8501ed 100644
--- a/drivers/net/irda/bfin_sir.h
+++ b/drivers/net/irda/bfin_sir.h
@@ -26,7 +26,6 @@
26#include <asm/cacheflush.h> 26#include <asm/cacheflush.h>
27#include <asm/dma.h> 27#include <asm/dma.h>
28#include <asm/portmux.h> 28#include <asm/portmux.h>
29#include <mach/bfin_serial_5xx.h>
30#undef DRIVER_NAME 29#undef DRIVER_NAME
31 30
32#ifdef CONFIG_SIR_BFIN_DMA 31#ifdef CONFIG_SIR_BFIN_DMA
@@ -83,64 +82,10 @@ struct bfin_sir_self {
83 82
84#define DRIVER_NAME "bfin_sir" 83#define DRIVER_NAME "bfin_sir"
85 84
86#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR) 85#define port_membase(port) (((struct bfin_sir_port *)(port))->membase)
87#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL) 86#define get_lsr_cache(port) (((struct bfin_sir_port *)(port))->lsr)
88#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH) 87#define put_lsr_cache(port, v) (((struct bfin_sir_port *)(port))->lsr = (v))
89#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR) 88#include <asm/bfin_serial.h>
90#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
91
92#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
93#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
94#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
95#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
96#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
97
98#ifdef CONFIG_BF54x
99#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
100#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
101#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
102#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
103#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
104#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
105
106#define SIR_UART_SET_DLAB(port)
107#define SIR_UART_CLEAR_DLAB(port)
108
109#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_SET_IER(port, v)
110#define SIR_UART_DISABLE_INTS(port) SIR_UART_CLEAR_IER(port, 0xF)
111#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_LSR(port, TFI); SIR_UART_CLEAR_IER(port, ETBEI); } while (0)
112#define SIR_UART_ENABLE_TX(port) do { SIR_UART_SET_IER(port, ETBEI); } while (0)
113#define SIR_UART_STOP_RX(port) do { SIR_UART_CLEAR_IER(port, ERBFI); } while (0)
114#define SIR_UART_ENABLE_RX(port) do { SIR_UART_SET_IER(port, ERBFI); } while (0)
115#else
116
117#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
118#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
119#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
120
121#define SIR_UART_SET_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) | DLAB); } while (0)
122#define SIR_UART_CLEAR_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) & ~DLAB); } while (0)
123
124#define SIR_UART_ENABLE_INTS(port, v) SIR_UART_PUT_IER(port, v)
125#define SIR_UART_DISABLE_INTS(port) SIR_UART_PUT_IER(port, 0)
126#define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ETBEI); } while (0)
127#define SIR_UART_ENABLE_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ETBEI); } while (0)
128#define SIR_UART_STOP_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ERBFI); } while (0)
129#define SIR_UART_ENABLE_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ERBFI); } while (0)
130
131static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
132{
133 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
134 port->lsr |= (lsr & (BI|FE|PE|OE));
135 return lsr | port->lsr;
136}
137
138static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
139{
140 port->lsr = 0;
141 bfin_read16(port->membase + OFFSET_LSR);
142}
143#endif
144 89
145static const unsigned short per[][4] = { 90static const unsigned short per[][4] = {
146 /* rx pin tx pin NULL uart_number */ 91 /* rx pin tx pin NULL uart_number */