diff options
| author | Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> | 2011-11-30 00:11:13 -0500 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-11-30 15:08:39 -0500 |
| commit | 2ee4bd1e25f8752cc5c4d39219c7bf5079ffc21f (patch) | |
| tree | ee1feffd93c75af5d3b14949c20a7b49bf36b991 /drivers/net/wireless | |
| parent | 24bf33048579096958083449c9f5a68f9c5c0d6d (diff) | |
ath9k_hw: add definitions to support MCI h/w code
these definitions will be used by MCI state machine and the corresponding
hardware code
Cc: Wilson Tsao <wtsao@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_mci.h | 102 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 3 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.h | 146 | ||||
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/reg.h | 304 |
4 files changed, 529 insertions, 26 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.h b/drivers/net/wireless/ath/ath9k/ar9003_mci.h new file mode 100644 index 000000000000..798da116a44c --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.h | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2010-2011 Atheros Communications Inc. | ||
| 3 | * | ||
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | ||
| 5 | * purpose with or without fee is hereby granted, provided that the above | ||
| 6 | * copyright notice and this permission notice appear in all copies. | ||
| 7 | * | ||
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AR9003_MCI_H | ||
| 18 | #define AR9003_MCI_H | ||
| 19 | |||
| 20 | #define MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */ | ||
| 21 | |||
| 22 | /* Default remote BT device MCI COEX version */ | ||
| 23 | #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3 | ||
| 24 | #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0 | ||
| 25 | |||
| 26 | /* Local WLAN MCI COEX version */ | ||
| 27 | #define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3 | ||
| 28 | #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0 | ||
| 29 | |||
| 30 | enum mci_gpm_coex_query_type { | ||
| 31 | MCI_GPM_COEX_QUERY_BT_ALL_INFO = BIT(0), | ||
| 32 | MCI_GPM_COEX_QUERY_BT_TOPOLOGY = BIT(1), | ||
| 33 | MCI_GPM_COEX_QUERY_BT_DEBUG = BIT(2), | ||
| 34 | }; | ||
| 35 | |||
| 36 | enum mci_gpm_coex_halt_bt_gpm { | ||
| 37 | MCI_GPM_COEX_BT_GPM_UNHALT, | ||
| 38 | MCI_GPM_COEX_BT_GPM_HALT | ||
| 39 | }; | ||
| 40 | |||
| 41 | enum mci_gpm_coex_bt_update_flags_op { | ||
| 42 | MCI_GPM_COEX_BT_FLAGS_READ, | ||
| 43 | MCI_GPM_COEX_BT_FLAGS_SET, | ||
| 44 | MCI_GPM_COEX_BT_FLAGS_CLEAR | ||
| 45 | }; | ||
| 46 | |||
| 47 | #define MCI_NUM_BT_CHANNELS 79 | ||
| 48 | |||
| 49 | #define MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002 | ||
| 50 | #define MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004 | ||
| 51 | #define MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008 | ||
| 52 | #define MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010 | ||
| 53 | #define MCI_BT_MCI_FLAGS_DEBUG 0x00000020 | ||
| 54 | #define MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040 | ||
| 55 | #define MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080 | ||
| 56 | #define MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100 | ||
| 57 | #define MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200 | ||
| 58 | #define MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400 | ||
| 59 | #define MCI_BT_MCI_FLAGS_AR9462_MODE 0x00001000 | ||
| 60 | #define MCI_BT_MCI_FLAGS_OTHER 0x00010000 | ||
| 61 | |||
| 62 | #define MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde | ||
| 63 | |||
| 64 | #define MCI_TOGGLE_BT_MCI_FLAGS (MCI_BT_MCI_FLAGS_UPDATE_CORR | \ | ||
| 65 | MCI_BT_MCI_FLAGS_UPDATE_HDR | \ | ||
| 66 | MCI_BT_MCI_FLAGS_UPDATE_PLD | \ | ||
| 67 | MCI_BT_MCI_FLAGS_MCI_MODE) | ||
| 68 | |||
| 69 | #define MCI_2G_FLAGS_CLEAR_MASK 0x00000000 | ||
| 70 | #define MCI_2G_FLAGS_SET_MASK MCI_TOGGLE_BT_MCI_FLAGS | ||
| 71 | #define MCI_2G_FLAGS MCI_DEFAULT_BT_MCI_FLAGS | ||
| 72 | |||
| 73 | #define MCI_5G_FLAGS_CLEAR_MASK MCI_TOGGLE_BT_MCI_FLAGS | ||
| 74 | #define MCI_5G_FLAGS_SET_MASK 0x00000000 | ||
| 75 | #define MCI_5G_FLAGS (MCI_DEFAULT_BT_MCI_FLAGS & \ | ||
| 76 | ~MCI_TOGGLE_BT_MCI_FLAGS) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Default value for AR9462 is 0x00002201 | ||
| 80 | */ | ||
| 81 | #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003 | ||
| 82 | #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004 | ||
| 83 | #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008 | ||
| 84 | #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010 | ||
| 85 | #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020 | ||
| 86 | #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040 | ||
| 87 | #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080 | ||
| 88 | #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700 | ||
| 89 | #define ATH_MCI_CONFIG_AGGR_THRESH_S 8 | ||
| 90 | #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800 | ||
| 91 | #define ATH_MCI_CONFIG_CLK_DIV 0x00003000 | ||
| 92 | #define ATH_MCI_CONFIG_CLK_DIV_S 12 | ||
| 93 | #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000 | ||
| 94 | #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000 | ||
| 95 | #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000 | ||
| 96 | |||
| 97 | #define ATH_MCI_CONFIG_MCI_OBS_MASK (ATH_MCI_CONFIG_MCI_OBS_MCI | \ | ||
| 98 | ATH_MCI_CONFIG_MCI_OBS_TXRX | \ | ||
| 99 | ATH_MCI_CONFIG_MCI_OBS_BT) | ||
| 100 | #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F | ||
| 101 | |||
| 102 | #endif | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 497d7461838a..ed64114571fc 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h | |||
| @@ -490,6 +490,8 @@ | |||
| 490 | #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 | 490 | #define AR_PHY_TEST_CTL_TSTADC_EN_S 8 |
| 491 | #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 | 491 | #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00 |
| 492 | #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 | 492 | #define AR_PHY_TEST_CTL_RX_OBS_SEL_S 10 |
| 493 | #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000 | ||
| 494 | #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 | ||
| 493 | 495 | ||
| 494 | 496 | ||
| 495 | #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168) | 497 | #define AR_PHY_TSTDAC (AR_SM_BASE + 0x168) |
| @@ -1001,6 +1003,7 @@ | |||
| 1001 | 1003 | ||
| 1002 | /* GLB Registers */ | 1004 | /* GLB Registers */ |
| 1003 | #define AR_GLB_BASE 0x20000 | 1005 | #define AR_GLB_BASE 0x20000 |
| 1006 | #define AR_GLB_GPIO_CONTROL (AR_GLB_BASE) | ||
| 1004 | #define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) | 1007 | #define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) |
| 1005 | #define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ | 1008 | #define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ |
| 1006 | (AR_SREV_9462_20(_ah) ? 0x4c : 0x50)) | 1009 | (AR_SREV_9462_20(_ah) ? 0x4c : 0x50)) |
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 3cb878c28ccf..4f786cb3020a 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h | |||
| @@ -266,6 +266,7 @@ enum ath9k_int { | |||
| 266 | ATH9K_INT_TX = 0x00000040, | 266 | ATH9K_INT_TX = 0x00000040, |
| 267 | ATH9K_INT_TXDESC = 0x00000080, | 267 | ATH9K_INT_TXDESC = 0x00000080, |
| 268 | ATH9K_INT_TIM_TIMER = 0x00000100, | 268 | ATH9K_INT_TIM_TIMER = 0x00000100, |
| 269 | ATH9K_INT_MCI = 0x00000200, | ||
| 269 | ATH9K_INT_BB_WATCHDOG = 0x00000400, | 270 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
| 270 | ATH9K_INT_TXURN = 0x00000800, | 271 | ATH9K_INT_TXURN = 0x00000800, |
| 271 | ATH9K_INT_MIB = 0x00001000, | 272 | ATH9K_INT_MIB = 0x00001000, |
| @@ -417,6 +418,25 @@ enum ath9k_rx_qtype { | |||
| 417 | ATH9K_RX_QUEUE_MAX, | 418 | ATH9K_RX_QUEUE_MAX, |
| 418 | }; | 419 | }; |
| 419 | 420 | ||
| 421 | enum mci_message_header { /* length of payload */ | ||
| 422 | MCI_LNA_CTRL = 0x10, /* len = 0 */ | ||
| 423 | MCI_CONT_NACK = 0x20, /* len = 0 */ | ||
| 424 | MCI_CONT_INFO = 0x30, /* len = 4 */ | ||
| 425 | MCI_CONT_RST = 0x40, /* len = 0 */ | ||
| 426 | MCI_SCHD_INFO = 0x50, /* len = 16 */ | ||
| 427 | MCI_CPU_INT = 0x60, /* len = 4 */ | ||
| 428 | MCI_SYS_WAKING = 0x70, /* len = 0 */ | ||
| 429 | MCI_GPM = 0x80, /* len = 16 */ | ||
| 430 | MCI_LNA_INFO = 0x90, /* len = 1 */ | ||
| 431 | MCI_LNA_STATE = 0x94, | ||
| 432 | MCI_LNA_TAKE = 0x98, | ||
| 433 | MCI_LNA_TRANS = 0x9c, | ||
| 434 | MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ | ||
| 435 | MCI_REQ_WAKE = 0xc0, /* len = 0 */ | ||
| 436 | MCI_DEBUG_16 = 0xfe, /* len = 2 */ | ||
| 437 | MCI_REMOTE_RESET = 0xff /* len = 16 */ | ||
| 438 | }; | ||
| 439 | |||
| 420 | enum ath_mci_gpm_coex_profile_type { | 440 | enum ath_mci_gpm_coex_profile_type { |
| 421 | MCI_GPM_COEX_PROFILE_UNKNOWN, | 441 | MCI_GPM_COEX_PROFILE_UNKNOWN, |
| 422 | MCI_GPM_COEX_PROFILE_RFCOMM, | 442 | MCI_GPM_COEX_PROFILE_RFCOMM, |
| @@ -427,6 +447,132 @@ enum ath_mci_gpm_coex_profile_type { | |||
| 427 | MCI_GPM_COEX_PROFILE_MAX | 447 | MCI_GPM_COEX_PROFILE_MAX |
| 428 | }; | 448 | }; |
| 429 | 449 | ||
| 450 | /* MCI GPM/Coex opcode/type definitions */ | ||
| 451 | enum { | ||
| 452 | MCI_GPM_COEX_W_GPM_PAYLOAD = 1, | ||
| 453 | MCI_GPM_COEX_B_GPM_TYPE = 4, | ||
| 454 | MCI_GPM_COEX_B_GPM_OPCODE = 5, | ||
| 455 | /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ | ||
| 456 | MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, | ||
| 457 | |||
| 458 | /* MCI_GPM_COEX_VERSION_QUERY */ | ||
| 459 | /* MCI_GPM_COEX_VERSION_RESPONSE */ | ||
| 460 | MCI_GPM_COEX_B_MAJOR_VERSION = 6, | ||
| 461 | MCI_GPM_COEX_B_MINOR_VERSION = 7, | ||
| 462 | /* MCI_GPM_COEX_STATUS_QUERY */ | ||
| 463 | MCI_GPM_COEX_B_BT_BITMAP = 6, | ||
| 464 | MCI_GPM_COEX_B_WLAN_BITMAP = 7, | ||
| 465 | /* MCI_GPM_COEX_HALT_BT_GPM */ | ||
| 466 | MCI_GPM_COEX_B_HALT_STATE = 6, | ||
| 467 | /* MCI_GPM_COEX_WLAN_CHANNELS */ | ||
| 468 | MCI_GPM_COEX_B_CHANNEL_MAP = 6, | ||
| 469 | /* MCI_GPM_COEX_BT_PROFILE_INFO */ | ||
| 470 | MCI_GPM_COEX_B_PROFILE_TYPE = 6, | ||
| 471 | MCI_GPM_COEX_B_PROFILE_LINKID = 7, | ||
| 472 | MCI_GPM_COEX_B_PROFILE_STATE = 8, | ||
| 473 | MCI_GPM_COEX_B_PROFILE_ROLE = 9, | ||
| 474 | MCI_GPM_COEX_B_PROFILE_RATE = 10, | ||
| 475 | MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, | ||
| 476 | MCI_GPM_COEX_H_PROFILE_T = 12, | ||
| 477 | MCI_GPM_COEX_B_PROFILE_W = 14, | ||
| 478 | MCI_GPM_COEX_B_PROFILE_A = 15, | ||
| 479 | /* MCI_GPM_COEX_BT_STATUS_UPDATE */ | ||
| 480 | MCI_GPM_COEX_B_STATUS_TYPE = 6, | ||
| 481 | MCI_GPM_COEX_B_STATUS_LINKID = 7, | ||
| 482 | MCI_GPM_COEX_B_STATUS_STATE = 8, | ||
| 483 | /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ | ||
| 484 | MCI_GPM_COEX_W_BT_FLAGS = 6, | ||
| 485 | MCI_GPM_COEX_B_BT_FLAGS_OP = 10 | ||
| 486 | }; | ||
| 487 | |||
| 488 | enum mci_gpm_subtype { | ||
| 489 | MCI_GPM_BT_CAL_REQ = 0, | ||
| 490 | MCI_GPM_BT_CAL_GRANT = 1, | ||
| 491 | MCI_GPM_BT_CAL_DONE = 2, | ||
| 492 | MCI_GPM_WLAN_CAL_REQ = 3, | ||
| 493 | MCI_GPM_WLAN_CAL_GRANT = 4, | ||
| 494 | MCI_GPM_WLAN_CAL_DONE = 5, | ||
| 495 | MCI_GPM_COEX_AGENT = 0x0c, | ||
| 496 | MCI_GPM_RSVD_PATTERN = 0xfe, | ||
| 497 | MCI_GPM_RSVD_PATTERN32 = 0xfefefefe, | ||
| 498 | MCI_GPM_BT_DEBUG = 0xff | ||
| 499 | }; | ||
| 500 | |||
| 501 | enum mci_bt_state { | ||
| 502 | MCI_BT_SLEEP, | ||
| 503 | MCI_BT_AWAKE, | ||
| 504 | MCI_BT_CAL_START, | ||
| 505 | MCI_BT_CAL | ||
| 506 | }; | ||
| 507 | |||
| 508 | /* Type of state query */ | ||
| 509 | enum mci_state_type { | ||
| 510 | MCI_STATE_ENABLE, | ||
| 511 | MCI_STATE_INIT_GPM_OFFSET, | ||
| 512 | MCI_STATE_NEXT_GPM_OFFSET, | ||
| 513 | MCI_STATE_LAST_GPM_OFFSET, | ||
| 514 | MCI_STATE_BT, | ||
| 515 | MCI_STATE_SET_BT_SLEEP, | ||
| 516 | MCI_STATE_SET_BT_AWAKE, | ||
| 517 | MCI_STATE_SET_BT_CAL_START, | ||
| 518 | MCI_STATE_SET_BT_CAL, | ||
| 519 | MCI_STATE_LAST_SCHD_MSG_OFFSET, | ||
| 520 | MCI_STATE_REMOTE_SLEEP, | ||
| 521 | MCI_STATE_CONT_RSSI_POWER, | ||
| 522 | MCI_STATE_CONT_PRIORITY, | ||
| 523 | MCI_STATE_CONT_TXRX, | ||
| 524 | MCI_STATE_RESET_REQ_WAKE, | ||
| 525 | MCI_STATE_SEND_WLAN_COEX_VERSION, | ||
| 526 | MCI_STATE_SET_BT_COEX_VERSION, | ||
| 527 | MCI_STATE_SEND_WLAN_CHANNELS, | ||
| 528 | MCI_STATE_SEND_VERSION_QUERY, | ||
| 529 | MCI_STATE_SEND_STATUS_QUERY, | ||
| 530 | MCI_STATE_NEED_FLUSH_BT_INFO, | ||
| 531 | MCI_STATE_SET_CONCUR_TX_PRI, | ||
| 532 | MCI_STATE_RECOVER_RX, | ||
| 533 | MCI_STATE_NEED_FTP_STOMP, | ||
| 534 | MCI_STATE_NEED_TUNING, | ||
| 535 | MCI_STATE_DEBUG, | ||
| 536 | MCI_STATE_MAX | ||
| 537 | }; | ||
| 538 | |||
| 539 | enum mci_gpm_coex_opcode { | ||
| 540 | MCI_GPM_COEX_VERSION_QUERY, | ||
| 541 | MCI_GPM_COEX_VERSION_RESPONSE, | ||
| 542 | MCI_GPM_COEX_STATUS_QUERY, | ||
| 543 | MCI_GPM_COEX_HALT_BT_GPM, | ||
| 544 | MCI_GPM_COEX_WLAN_CHANNELS, | ||
| 545 | MCI_GPM_COEX_BT_PROFILE_INFO, | ||
| 546 | MCI_GPM_COEX_BT_STATUS_UPDATE, | ||
| 547 | MCI_GPM_COEX_BT_UPDATE_FLAGS | ||
| 548 | }; | ||
| 549 | |||
| 550 | #define MCI_GPM_NOMORE 0 | ||
| 551 | #define MCI_GPM_MORE 1 | ||
| 552 | #define MCI_GPM_INVALID 0xffffffff | ||
| 553 | |||
| 554 | #define MCI_GPM_RECYCLE(_p_gpm) do { \ | ||
| 555 | *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \ | ||
| 556 | MCI_GPM_RSVD_PATTERN32; \ | ||
| 557 | } while (0) | ||
| 558 | |||
| 559 | #define MCI_GPM_TYPE(_p_gpm) \ | ||
| 560 | (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) | ||
| 561 | |||
| 562 | #define MCI_GPM_OPCODE(_p_gpm) \ | ||
| 563 | (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) | ||
| 564 | |||
| 565 | #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \ | ||
| 566 | *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\ | ||
| 567 | } while (0) | ||
| 568 | |||
| 569 | #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \ | ||
| 570 | *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ | ||
| 571 | *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\ | ||
| 572 | } while (0) | ||
| 573 | |||
| 574 | #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) | ||
| 575 | |||
| 430 | struct ath9k_beacon_state { | 576 | struct ath9k_beacon_state { |
| 431 | u32 bs_nexttbtt; | 577 | u32 bs_nexttbtt; |
| 432 | u32 bs_nextdtim; | 578 | u32 bs_nextdtim; |
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 45910975d853..ba3672f45a20 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h | |||
| @@ -1006,6 +1006,8 @@ enum { | |||
| 1006 | #define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030) | 1006 | #define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030) |
| 1007 | #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 | 1007 | #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 |
| 1008 | #define AR_INTR_ASYNC_MASK_GPIO_S 18 | 1008 | #define AR_INTR_ASYNC_MASK_GPIO_S 18 |
| 1009 | #define AR_INTR_ASYNC_MASK_MCI 0x00000080 | ||
| 1010 | #define AR_INTR_ASYNC_MASK_MCI_S 7 | ||
| 1009 | 1011 | ||
| 1010 | #define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034) | 1012 | #define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034) |
| 1011 | #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 | 1013 | #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 |
| @@ -1013,6 +1015,14 @@ enum { | |||
| 1013 | 1015 | ||
| 1014 | #define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038) | 1016 | #define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038) |
| 1015 | #define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038) | 1017 | #define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038) |
| 1018 | #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 | ||
| 1019 | #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \ | ||
| 1020 | AR_INTR_ASYNC_CAUSE_MCI) | ||
| 1021 | |||
| 1022 | /* Asynchronous Interrupt Enable Register */ | ||
| 1023 | #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 | ||
| 1024 | #define AR_INTR_ASYNC_ENABLE_MCI_S 7 | ||
| 1025 | |||
| 1016 | 1026 | ||
| 1017 | #define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c) | 1027 | #define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c) |
| 1018 | #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 | 1028 | #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 |
| @@ -1555,6 +1565,8 @@ enum { | |||
| 1555 | #define AR_DIAG_FRAME_NV0 0x00020000 | 1565 | #define AR_DIAG_FRAME_NV0 0x00020000 |
| 1556 | #define AR_DIAG_OBS_PT_SEL1 0x000C0000 | 1566 | #define AR_DIAG_OBS_PT_SEL1 0x000C0000 |
| 1557 | #define AR_DIAG_OBS_PT_SEL1_S 18 | 1567 | #define AR_DIAG_OBS_PT_SEL1_S 18 |
| 1568 | #define AR_DIAG_OBS_PT_SEL2 0x08000000 | ||
| 1569 | #define AR_DIAG_OBS_PT_SEL2_S 27 | ||
| 1558 | #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ | 1570 | #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ |
| 1559 | #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 | 1571 | #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 |
| 1560 | #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 | 1572 | #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 |
| @@ -1929,37 +1941,277 @@ enum { | |||
| 1929 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 | 1941 | #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 |
| 1930 | 1942 | ||
| 1931 | /* MCI Registers */ | 1943 | /* MCI Registers */ |
| 1932 | #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c | 1944 | |
| 1933 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 | 1945 | #define AR_MCI_COMMAND0 0x1800 |
| 1934 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 | 1946 | #define AR_MCI_COMMAND0_HEADER 0xFF |
| 1935 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 | 1947 | #define AR_MCI_COMMAND0_HEADER_S 0 |
| 1936 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 | 1948 | #define AR_MCI_COMMAND0_LEN 0x1f00 |
| 1937 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 | 1949 | #define AR_MCI_COMMAND0_LEN_S 8 |
| 1938 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 | 1950 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 |
| 1939 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 | 1951 | #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 |
| 1940 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 | 1952 | |
| 1941 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 | 1953 | #define AR_MCI_COMMAND1 0x1804 |
| 1942 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 | 1954 | |
| 1943 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 | 1955 | #define AR_MCI_COMMAND2 0x1808 |
| 1944 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 | 1956 | #define AR_MCI_COMMAND2_RESET_TX 0x01 |
| 1945 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 | 1957 | #define AR_MCI_COMMAND2_RESET_TX_S 0 |
| 1946 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 | 1958 | #define AR_MCI_COMMAND2_RESET_RX 0x02 |
| 1947 | #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 | 1959 | #define AR_MCI_COMMAND2_RESET_RX_S 1 |
| 1948 | #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 | 1960 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC |
| 1949 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 | 1961 | #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 |
| 1950 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 | 1962 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 |
| 1951 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 | 1963 | #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 |
| 1952 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 | 1964 | |
| 1953 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 | 1965 | #define AR_MCI_RX_CTRL 0x180c |
| 1954 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 | 1966 | |
| 1955 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 | 1967 | #define AR_MCI_TX_CTRL 0x1810 |
| 1956 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 | 1968 | /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ |
| 1957 | #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ | 1969 | #define AR_MCI_TX_CTRL_CLK_DIV 0x03 |
| 1970 | #define AR_MCI_TX_CTRL_CLK_DIV_S 0 | ||
| 1971 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 | ||
| 1972 | #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 | ||
| 1973 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 | ||
| 1974 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 | ||
| 1975 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 | ||
| 1976 | #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 | ||
| 1977 | |||
| 1978 | #define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814 | ||
| 1979 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF | ||
| 1980 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 | ||
| 1981 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 | ||
| 1982 | #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 | ||
| 1983 | |||
| 1984 | #define AR_MCI_SCHD_TABLE_0 0x1818 | ||
| 1985 | #define AR_MCI_SCHD_TABLE_1 0x181c | ||
| 1986 | #define AR_MCI_GPM_0 0x1820 | ||
| 1987 | #define AR_MCI_GPM_1 0x1824 | ||
| 1988 | #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 | ||
| 1989 | #define AR_MCI_GPM_WRITE_PTR_S 16 | ||
| 1990 | #define AR_MCI_GPM_BUF_LEN 0x0000FFFF | ||
| 1991 | #define AR_MCI_GPM_BUF_LEN_S 0 | ||
| 1992 | |||
| 1993 | #define AR_MCI_INTERRUPT_RAW 0x1828 | ||
| 1994 | #define AR_MCI_INTERRUPT_EN 0x182c | ||
| 1995 | #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 | ||
| 1996 | #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 | ||
| 1997 | #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 | ||
| 1998 | #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 | ||
| 1999 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 | ||
| 2000 | #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 | ||
| 2001 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 | ||
| 2002 | #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 | ||
| 2003 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 | ||
| 2004 | #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 | ||
| 2005 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 | ||
| 2006 | #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 | ||
| 2007 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 | ||
| 2008 | #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 | ||
| 2009 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 | ||
| 2010 | #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 | ||
| 2011 | #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 | ||
| 2012 | #define AR_MCI_INTERRUPT_RX_MSG_S 9 | ||
| 2013 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 | ||
| 2014 | #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 | ||
| 2015 | #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 | ||
| 2016 | #define AR_MCI_INTERRUPT_BT_PRI_S 11 | ||
| 2017 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 | ||
| 2018 | #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 | ||
| 2019 | #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 | ||
| 2020 | #define AR_MCI_INTERRUPT_BT_FREQ_S 28 | ||
| 2021 | #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 | ||
| 2022 | #define AR_MCI_INTERRUPT_BT_STOMP_S 29 | ||
| 2023 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 | ||
| 2024 | #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 | ||
| 2025 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 | ||
| 2026 | #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 | ||
| 2027 | |||
| 2028 | #define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \ | ||
| 2029 | AR_MCI_INTERRUPT_RX_INVALID_HDR | \ | ||
| 2030 | AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ | ||
| 2031 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ | ||
| 2032 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ | ||
| 2033 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ | ||
| 2034 | AR_MCI_INTERRUPT_RX_MSG | \ | ||
| 2035 | AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ | ||
| 2036 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT) | ||
| 2037 | |||
| 2038 | #define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ | ||
| 2039 | AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ | ||
| 2040 | AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ | ||
| 2041 | AR_MCI_INTERRUPT_TX_SW_MSG_FAIL) | ||
| 2042 | |||
| 2043 | #define AR_MCI_REMOTE_CPU_INT 0x1830 | ||
| 2044 | #define AR_MCI_REMOTE_CPU_INT_EN 0x1834 | ||
| 2045 | #define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838 | ||
| 2046 | #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c | ||
| 2047 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 | ||
| 2048 | #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 | ||
| 2049 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 | ||
| 2050 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 | ||
| 2051 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 | ||
| 2052 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 | ||
| 2053 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 | ||
| 2054 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 | ||
| 2055 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 | ||
| 2056 | #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 | ||
| 2057 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 | ||
| 2058 | #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 | ||
| 2059 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 | ||
| 2060 | #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 | ||
| 2061 | #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 | ||
| 2062 | #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 | ||
| 2063 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 | ||
| 2064 | #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 | ||
| 2065 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 | ||
| 2066 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 | ||
| 2067 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 | ||
| 2068 | #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 | ||
| 2069 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 | ||
| 2070 | #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 | ||
| 2071 | #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ | ||
| 1958 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \ | 2072 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \ |
| 1959 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ | 2073 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ |
| 1960 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ | 2074 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ |
| 1961 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ | 2075 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ |
| 1962 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST) | 2076 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST) |
| 1963 | 2077 | ||
| 2078 | #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \ | ||
| 2079 | AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \ | ||
| 2080 | AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ | ||
| 2081 | AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \ | ||
| 2082 | AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ | ||
| 2083 | AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ | ||
| 2084 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ | ||
| 2085 | AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ | ||
| 2086 | AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ | ||
| 2087 | AR_MCI_INTERRUPT_RX_MSG_CONT_RST | \ | ||
| 2088 | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) | ||
| 2089 | |||
| 2090 | #define AR_MCI_CPU_INT 0x1840 | ||
| 2091 | |||
| 2092 | #define AR_MCI_RX_STATUS 0x1844 | ||
| 2093 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 | ||
| 2094 | #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 | ||
| 2095 | #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 | ||
| 2096 | #define AR_MCI_RX_REMOTE_SLEEP_S 12 | ||
| 2097 | #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 | ||
| 2098 | #define AR_MCI_RX_MCI_CLK_REQ_S 13 | ||
| 2099 | |||
| 2100 | #define AR_MCI_CONT_STATUS 0x1848 | ||
| 2101 | #define AR_MCI_CONT_RSSI_POWER 0x000000FF | ||
| 2102 | #define AR_MCI_CONT_RSSI_POWER_S 0 | ||
| 2103 | #define AR_MCI_CONT_RRIORITY 0x0000FF00 | ||
| 2104 | #define AR_MCI_CONT_RRIORITY_S 8 | ||
| 2105 | #define AR_MCI_CONT_TXRX 0x00010000 | ||
| 2106 | #define AR_MCI_CONT_TXRX_S 16 | ||
| 2107 | |||
| 2108 | #define AR_MCI_BT_PRI0 0x184c | ||
| 2109 | #define AR_MCI_BT_PRI1 0x1850 | ||
| 2110 | #define AR_MCI_BT_PRI2 0x1854 | ||
| 2111 | #define AR_MCI_BT_PRI3 0x1858 | ||
| 2112 | #define AR_MCI_BT_PRI 0x185c | ||
| 2113 | #define AR_MCI_WL_FREQ0 0x1860 | ||
| 2114 | #define AR_MCI_WL_FREQ1 0x1864 | ||
| 2115 | #define AR_MCI_WL_FREQ2 0x1868 | ||
| 2116 | #define AR_MCI_GAIN 0x186c | ||
| 2117 | #define AR_MCI_WBTIMER1 0x1870 | ||
| 2118 | #define AR_MCI_WBTIMER2 0x1874 | ||
| 2119 | #define AR_MCI_WBTIMER3 0x1878 | ||
| 2120 | #define AR_MCI_WBTIMER4 0x187c | ||
| 2121 | #define AR_MCI_MAXGAIN 0x1880 | ||
| 2122 | #define AR_MCI_HW_SCHD_TBL_CTL 0x1884 | ||
| 2123 | #define AR_MCI_HW_SCHD_TBL_D0 0x1888 | ||
| 2124 | #define AR_MCI_HW_SCHD_TBL_D1 0x188c | ||
| 2125 | #define AR_MCI_HW_SCHD_TBL_D2 0x1890 | ||
| 2126 | #define AR_MCI_HW_SCHD_TBL_D3 0x1894 | ||
| 2127 | #define AR_MCI_TX_PAYLOAD0 0x1898 | ||
| 2128 | #define AR_MCI_TX_PAYLOAD1 0x189c | ||
| 2129 | #define AR_MCI_TX_PAYLOAD2 0x18a0 | ||
| 2130 | #define AR_MCI_TX_PAYLOAD3 0x18a4 | ||
| 2131 | #define AR_BTCOEX_WBTIMER 0x18a8 | ||
| 2132 | |||
| 2133 | #define AR_BTCOEX_CTRL 0x18ac | ||
| 2134 | #define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001 | ||
| 2135 | #define AR_BTCOEX_CTRL_AR9462_MODE_S 0 | ||
| 2136 | #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 | ||
| 2137 | #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 | ||
| 2138 | #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 | ||
| 2139 | #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 | ||
| 2140 | #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 | ||
| 2141 | #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 | ||
| 2142 | #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 | ||
| 2143 | #define AR_BTCOEX_CTRL_PA_SHARED_S 4 | ||
| 2144 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 | ||
| 2145 | #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 | ||
| 2146 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 | ||
| 2147 | #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 | ||
| 2148 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 | ||
| 2149 | #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 | ||
| 2150 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 | ||
| 2151 | #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 | ||
| 2152 | #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 | ||
| 2153 | #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 | ||
| 2154 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 | ||
| 2155 | #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 | ||
| 2156 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 | ||
| 2157 | #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 | ||
| 2158 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 | ||
| 2159 | #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 | ||
| 2160 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 | ||
| 2161 | #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 | ||
| 2162 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 | ||
| 2163 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 | ||
| 2164 | #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 | ||
| 2165 | #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 | ||
| 2166 | |||
| 2167 | #define AR_BTCOEX_WL_WEIGHTS0 0x18b0 | ||
| 2168 | #define AR_BTCOEX_WL_WEIGHTS1 0x18b4 | ||
| 2169 | #define AR_BTCOEX_WL_WEIGHTS2 0x18b8 | ||
| 2170 | #define AR_BTCOEX_WL_WEIGHTS3 0x18bc | ||
| 2171 | #define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) | ||
| 2172 | #define AR_BTCOEX_WL_LNA 0x1940 | ||
| 2173 | #define AR_BTCOEX_RFGAIN_CTRL 0x1944 | ||
| 2174 | |||
| 2175 | #define AR_BTCOEX_CTRL2 0x1948 | ||
| 2176 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 | ||
| 2177 | #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 | ||
| 2178 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 | ||
| 2179 | #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 | ||
| 2180 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 | ||
| 2181 | #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 | ||
| 2182 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 | ||
| 2183 | #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 | ||
| 2184 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 | ||
| 2185 | #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 | ||
| 2186 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 | ||
| 2187 | #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 | ||
| 2188 | |||
| 2189 | #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 | ||
| 2190 | #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 | ||
| 2191 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 | ||
| 2192 | #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 | ||
| 2193 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 | ||
| 2194 | #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 | ||
| 2195 | #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 | ||
| 2196 | #define AR_GLB_WLAN_UART_INTF_EN_S 17 | ||
| 2197 | #define AR_GLB_DS_JTAG_DISABLE 0x00040000 | ||
| 2198 | #define AR_GLB_DS_JTAG_DISABLE_S 18 | ||
| 2199 | |||
| 2200 | #define AR_BTCOEX_RC 0x194c | ||
| 2201 | #define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2)) | ||
| 2202 | #define AR_BTCOEX_DBG 0x1a50 | ||
| 2203 | #define AR_MCI_LAST_HW_MSG_HDR 0x1a54 | ||
| 2204 | #define AR_MCI_LAST_HW_MSG_BDY 0x1a58 | ||
| 2205 | |||
| 2206 | #define AR_MCI_SCHD_TABLE_2 0x1a5c | ||
| 2207 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 | ||
| 2208 | #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 | ||
| 2209 | #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 | ||
| 2210 | #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 | ||
| 2211 | |||
| 2212 | #define AR_BTCOEX_CTRL3 0x1a60 | ||
| 2213 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff | ||
| 2214 | #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 | ||
| 2215 | |||
| 1964 | 2216 | ||
| 1965 | #endif | 2217 | #endif |