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authorJohn W. Linville <linville@tuxdriver.com>2010-12-16 15:43:36 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-12-20 14:49:47 -0500
commit5c405b5c3e435fd332058c59ee58eaa1ac9c513a (patch)
tree3f6125a86d0d86d5712640bf4a4db856ddcdf10f /drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
parent61ad5394590c5c5338ab4ec50553d809a9996d50 (diff)
rtl8192ce: drop 'rtl8192c-' prefix from files
Signed-off-by: John W. Linville <linville@tuxdriver.com> Tested-by: Larry Finger <Larry.Finger@lwfinger.net>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192ce/hw.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.c2173
1 files changed, 2173 insertions, 0 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
new file mode 100644
index 000000000000..1266dbe44176
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
@@ -0,0 +1,2173 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../pci.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "dm.h"
40#include "fw.h"
41#include "led.h"
42#include "hw.h"
43
44#define LLT_CONFIG 5
45
46static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
47 u8 set_bits, u8 clear_bits)
48{
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51
52 rtlpci->reg_bcn_ctrl_val |= set_bits;
53 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
54
55 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
56}
57
58static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
59{
60 struct rtl_priv *rtlpriv = rtl_priv(hw);
61 u8 tmp1byte;
62
63 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
64 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
65 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
66 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
67 tmp1byte &= ~(BIT(0));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
69}
70
71static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 u8 tmp1byte;
75
76 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
77 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
78 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
79 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
80 tmp1byte |= BIT(0);
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
82}
83
84static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
85{
86 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
87}
88
89static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
90{
91 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
92}
93
94void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
95{
96 struct rtl_priv *rtlpriv = rtl_priv(hw);
97 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
98 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
99
100 switch (variable) {
101 case HW_VAR_RCR:
102 *((u32 *) (val)) = rtlpci->receive_config;
103 break;
104 case HW_VAR_RF_STATE:
105 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
106 break;
107 case HW_VAR_FWLPS_RF_ON:{
108 enum rf_pwrstate rfState;
109 u32 val_rcr;
110
111 rtlpriv->cfg->ops->get_hw_reg(hw,
112 HW_VAR_RF_STATE,
113 (u8 *) (&rfState));
114 if (rfState == ERFOFF) {
115 *((bool *) (val)) = true;
116 } else {
117 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
118 val_rcr &= 0x00070000;
119 if (val_rcr)
120 *((bool *) (val)) = false;
121 else
122 *((bool *) (val)) = true;
123 }
124 break;
125 }
126 case HW_VAR_FW_PSMODE_STATUS:
127 *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
128 break;
129 case HW_VAR_CORRECT_TSF:{
130 u64 tsf;
131 u32 *ptsf_low = (u32 *)&tsf;
132 u32 *ptsf_high = ((u32 *)&tsf) + 1;
133
134 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
135 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
136
137 *((u64 *) (val)) = tsf;
138
139 break;
140 }
141 case HW_VAR_MGT_FILTER:
142 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
143 break;
144 case HW_VAR_CTRL_FILTER:
145 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
146 break;
147 case HW_VAR_DATA_FILTER:
148 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
149 break;
150 default:
151 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
152 ("switch case not process\n"));
153 break;
154 }
155}
156
157void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
158{
159 struct rtl_priv *rtlpriv = rtl_priv(hw);
160 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
161 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
162 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
163 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
164 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
165 u8 idx;
166
167 switch (variable) {
168 case HW_VAR_ETHER_ADDR:{
169 for (idx = 0; idx < ETH_ALEN; idx++) {
170 rtl_write_byte(rtlpriv, (REG_MACID + idx),
171 val[idx]);
172 }
173 break;
174 }
175 case HW_VAR_BASIC_RATE:{
176 u16 b_rate_cfg = ((u16 *) val)[0];
177 u8 rate_index = 0;
178 b_rate_cfg = b_rate_cfg & 0x15f;
179 b_rate_cfg |= 0x01;
180 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
181 rtl_write_byte(rtlpriv, REG_RRSR + 1,
182 (b_rate_cfg >> 8)&0xff);
183 while (b_rate_cfg > 0x1) {
184 b_rate_cfg = (b_rate_cfg >> 1);
185 rate_index++;
186 }
187 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
188 rate_index);
189 break;
190 }
191 case HW_VAR_BSSID:{
192 for (idx = 0; idx < ETH_ALEN; idx++) {
193 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
194 val[idx]);
195 }
196 break;
197 }
198 case HW_VAR_SIFS:{
199 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
200 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
201
202 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
203 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
204
205 if (!mac->ht_enable)
206 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
207 0x0e0e);
208 else
209 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
210 *((u16 *) val));
211 break;
212 }
213 case HW_VAR_SLOT_TIME:{
214 u8 e_aci;
215
216 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
217 ("HW_VAR_SLOT_TIME %x\n", val[0]));
218
219 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
220
221 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
222 rtlpriv->cfg->ops->set_hw_reg(hw,
223 HW_VAR_AC_PARAM,
224 (u8 *) (&e_aci));
225 }
226 break;
227 }
228 case HW_VAR_ACK_PREAMBLE:{
229 u8 reg_tmp;
230 u8 short_preamble = (bool) (*(u8 *) val);
231 reg_tmp = (mac->cur_40_prime_sc) << 5;
232 if (short_preamble)
233 reg_tmp |= 0x80;
234
235 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
236 break;
237 }
238 case HW_VAR_AMPDU_MIN_SPACE:{
239 u8 min_spacing_to_set;
240 u8 sec_min_space;
241
242 min_spacing_to_set = *((u8 *) val);
243 if (min_spacing_to_set <= 7) {
244 sec_min_space = 0;
245
246 if (min_spacing_to_set < sec_min_space)
247 min_spacing_to_set = sec_min_space;
248
249 mac->min_space_cfg = ((mac->min_space_cfg &
250 0xf8) |
251 min_spacing_to_set);
252
253 *val = min_spacing_to_set;
254
255 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
256 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
257 mac->min_space_cfg));
258
259 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
260 mac->min_space_cfg);
261 }
262 break;
263 }
264 case HW_VAR_SHORTGI_DENSITY:{
265 u8 density_to_set;
266
267 density_to_set = *((u8 *) val);
268 mac->min_space_cfg |= (density_to_set << 3);
269
270 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
271 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
272 mac->min_space_cfg));
273
274 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
275 mac->min_space_cfg);
276
277 break;
278 }
279 case HW_VAR_AMPDU_FACTOR:{
280 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
281
282 u8 factor_toset;
283 u8 *p_regtoset = NULL;
284 u8 index = 0;
285
286 p_regtoset = regtoset_normal;
287
288 factor_toset = *((u8 *) val);
289 if (factor_toset <= 3) {
290 factor_toset = (1 << (factor_toset + 2));
291 if (factor_toset > 0xf)
292 factor_toset = 0xf;
293
294 for (index = 0; index < 4; index++) {
295 if ((p_regtoset[index] & 0xf0) >
296 (factor_toset << 4))
297 p_regtoset[index] =
298 (p_regtoset[index] & 0x0f) |
299 (factor_toset << 4);
300
301 if ((p_regtoset[index] & 0x0f) >
302 factor_toset)
303 p_regtoset[index] =
304 (p_regtoset[index] & 0xf0) |
305 (factor_toset);
306
307 rtl_write_byte(rtlpriv,
308 (REG_AGGLEN_LMT + index),
309 p_regtoset[index]);
310
311 }
312
313 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
314 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
315 factor_toset));
316 }
317 break;
318 }
319 case HW_VAR_AC_PARAM:{
320 u8 e_aci = *((u8 *) val);
321 u32 u4b_ac_param = 0;
322
323 u4b_ac_param |= (u32) mac->ac[e_aci].aifs;
324 u4b_ac_param |= ((u32) mac->ac[e_aci].cw_min
325 & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
326 u4b_ac_param |= ((u32) mac->ac[e_aci].cw_max &
327 0xF) << AC_PARAM_ECW_MAX_OFFSET;
328 u4b_ac_param |= (u32) mac->ac[e_aci].tx_op
329 << AC_PARAM_TXOP_LIMIT_OFFSET;
330
331 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
332 ("queue:%x, ac_param:%x\n", e_aci,
333 u4b_ac_param));
334
335 switch (e_aci) {
336 case AC1_BK:
337 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
338 u4b_ac_param);
339 break;
340 case AC0_BE:
341 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
342 u4b_ac_param);
343 break;
344 case AC2_VI:
345 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
346 u4b_ac_param);
347 break;
348 case AC3_VO:
349 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
350 u4b_ac_param);
351 break;
352 default:
353 RT_ASSERT(false,
354 ("SetHwReg8185(): invalid aci: %d !\n",
355 e_aci));
356 break;
357 }
358
359 if (rtlpci->acm_method != eAcmWay2_SW)
360 rtlpriv->cfg->ops->set_hw_reg(hw,
361 HW_VAR_ACM_CTRL,
362 (u8 *) (&e_aci));
363 break;
364 }
365 case HW_VAR_ACM_CTRL:{
366 u8 e_aci = *((u8 *) val);
367 union aci_aifsn *p_aci_aifsn =
368 (union aci_aifsn *)(&(mac->ac[0].aifs));
369 u8 acm = p_aci_aifsn->f.acm;
370 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
371
372 acm_ctrl =
373 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
374
375 if (acm) {
376 switch (e_aci) {
377 case AC0_BE:
378 acm_ctrl |= AcmHw_BeqEn;
379 break;
380 case AC2_VI:
381 acm_ctrl |= AcmHw_ViqEn;
382 break;
383 case AC3_VO:
384 acm_ctrl |= AcmHw_VoqEn;
385 break;
386 default:
387 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
388 ("HW_VAR_ACM_CTRL acm set "
389 "failed: eACI is %d\n", acm));
390 break;
391 }
392 } else {
393 switch (e_aci) {
394 case AC0_BE:
395 acm_ctrl &= (~AcmHw_BeqEn);
396 break;
397 case AC2_VI:
398 acm_ctrl &= (~AcmHw_ViqEn);
399 break;
400 case AC3_VO:
401 acm_ctrl &= (~AcmHw_BeqEn);
402 break;
403 default:
404 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
405 ("switch case not process\n"));
406 break;
407 }
408 }
409
410 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
411 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
412 "Write 0x%X\n", acm_ctrl));
413 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
414 break;
415 }
416 case HW_VAR_RCR:{
417 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
418 rtlpci->receive_config = ((u32 *) (val))[0];
419 break;
420 }
421 case HW_VAR_RETRY_LIMIT:{
422 u8 retry_limit = ((u8 *) (val))[0];
423
424 rtl_write_word(rtlpriv, REG_RL,
425 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
426 retry_limit << RETRY_LIMIT_LONG_SHIFT);
427 break;
428 }
429 case HW_VAR_DUAL_TSF_RST:
430 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
431 break;
432 case HW_VAR_EFUSE_BYTES:
433 rtlefuse->efuse_usedbytes = *((u16 *) val);
434 break;
435 case HW_VAR_EFUSE_USAGE:
436 rtlefuse->efuse_usedpercentage = *((u8 *) val);
437 break;
438 case HW_VAR_IO_CMD:
439 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
440 break;
441 case HW_VAR_WPA_CONFIG:
442 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
443 break;
444 case HW_VAR_SET_RPWM:{
445 u8 rpwm_val;
446
447 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
448 udelay(1);
449
450 if (rpwm_val & BIT(7)) {
451 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
452 (*(u8 *) val));
453 } else {
454 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
455 ((*(u8 *) val) | BIT(7)));
456 }
457
458 break;
459 }
460 case HW_VAR_H2C_FW_PWRMODE:{
461 u8 psmode = (*(u8 *) val);
462
463 if ((psmode != FW_PS_ACTIVE_MODE) &&
464 (!IS_92C_SERIAL(rtlhal->version))) {
465 rtl92c_dm_rf_saving(hw, true);
466 }
467
468 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
469 break;
470 }
471 case HW_VAR_FW_PSMODE_STATUS:
472 ppsc->b_fw_current_inpsmode = *((bool *) val);
473 break;
474 case HW_VAR_H2C_FW_JOINBSSRPT:{
475 u8 mstatus = (*(u8 *) val);
476 u8 tmp_regcr, tmp_reg422;
477 bool b_recover = false;
478
479 if (mstatus == RT_MEDIA_CONNECT) {
480 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
481 NULL);
482
483 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
484 rtl_write_byte(rtlpriv, REG_CR + 1,
485 (tmp_regcr | BIT(0)));
486
487 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
488 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
489
490 tmp_reg422 =
491 rtl_read_byte(rtlpriv,
492 REG_FWHW_TXQ_CTRL + 2);
493 if (tmp_reg422 & BIT(6))
494 b_recover = true;
495 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
496 tmp_reg422 & (~BIT(6)));
497
498 rtl92c_set_fw_rsvdpagepkt(hw, 0);
499
500 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
501 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
502
503 if (b_recover) {
504 rtl_write_byte(rtlpriv,
505 REG_FWHW_TXQ_CTRL + 2,
506 tmp_reg422);
507 }
508
509 rtl_write_byte(rtlpriv, REG_CR + 1,
510 (tmp_regcr & ~(BIT(0))));
511 }
512 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
513
514 break;
515 }
516 case HW_VAR_AID:{
517 u16 u2btmp;
518 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
519 u2btmp &= 0xC000;
520 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
521 mac->assoc_id));
522
523 break;
524 }
525 case HW_VAR_CORRECT_TSF:{
526 u8 btype_ibss = ((u8 *) (val))[0];
527
528 /*btype_ibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ?
529 1 : 0;*/
530
531 if (btype_ibss == true)
532 _rtl92ce_stop_tx_beacon(hw);
533
534 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
535
536 rtl_write_dword(rtlpriv, REG_TSFTR,
537 (u32) (mac->tsf & 0xffffffff));
538 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
539 (u32) ((mac->tsf >> 32)&0xffffffff));
540
541 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
542
543 if (btype_ibss == true)
544 _rtl92ce_resume_tx_beacon(hw);
545
546 break;
547
548 }
549 case HW_VAR_MGT_FILTER:
550 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *) val);
551 break;
552 case HW_VAR_CTRL_FILTER:
553 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *) val);
554 break;
555 case HW_VAR_DATA_FILTER:
556 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *) val);
557 break;
558 default:
559 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
560 "not process\n"));
561 break;
562 }
563}
564
565static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
566{
567 struct rtl_priv *rtlpriv = rtl_priv(hw);
568 bool status = true;
569 long count = 0;
570 u32 value = _LLT_INIT_ADDR(address) |
571 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
572
573 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
574
575 do {
576 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
577 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
578 break;
579
580 if (count > POLLING_LLT_THRESHOLD) {
581 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
582 ("Failed to polling write LLT done at "
583 "address %d!\n", address));
584 status = false;
585 break;
586 }
587 } while (++count);
588
589 return status;
590}
591
592static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
593{
594 struct rtl_priv *rtlpriv = rtl_priv(hw);
595 unsigned short i;
596 u8 txpktbuf_bndy;
597 u8 maxPage;
598 bool status;
599
600#if LLT_CONFIG == 1
601 maxPage = 255;
602 txpktbuf_bndy = 252;
603#elif LLT_CONFIG == 2
604 maxPage = 127;
605 txpktbuf_bndy = 124;
606#elif LLT_CONFIG == 3
607 maxPage = 255;
608 txpktbuf_bndy = 174;
609#elif LLT_CONFIG == 4
610 maxPage = 255;
611 txpktbuf_bndy = 246;
612#elif LLT_CONFIG == 5
613 maxPage = 255;
614 txpktbuf_bndy = 246;
615#endif
616
617#if LLT_CONFIG == 1
618 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
619 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
620#elif LLT_CONFIG == 2
621 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
622#elif LLT_CONFIG == 3
623 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
624#elif LLT_CONFIG == 4
625 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
626#elif LLT_CONFIG == 5
627 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
628
629 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
630#endif
631
632 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
633 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
634
635 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
636 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
637
638 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
639 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
640 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
641
642 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
643 status = _rtl92ce_llt_write(hw, i, i + 1);
644 if (true != status)
645 return status;
646 }
647
648 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
649 if (true != status)
650 return status;
651
652 for (i = txpktbuf_bndy; i < maxPage; i++) {
653 status = _rtl92ce_llt_write(hw, i, (i + 1));
654 if (true != status)
655 return status;
656 }
657
658 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
659 if (true != status)
660 return status;
661
662 return true;
663}
664
665static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
666{
667 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
668 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
669 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
670 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
671
672 if (rtlpci->up_first_time)
673 return;
674
675 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
676 rtl92ce_sw_led_on(hw, pLed0);
677 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
678 rtl92ce_sw_led_on(hw, pLed0);
679 else
680 rtl92ce_sw_led_off(hw, pLed0);
681
682}
683
684static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
685{
686 struct rtl_priv *rtlpriv = rtl_priv(hw);
687 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
688 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
689
690 unsigned char bytetmp;
691 unsigned short wordtmp;
692 u16 retry;
693
694 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
695 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
696 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
697
698 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
699 udelay(2);
700
701 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
702 udelay(2);
703
704 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
705 udelay(2);
706
707 retry = 0;
708 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
709 rtl_read_dword(rtlpriv, 0xEC),
710 bytetmp));
711
712 while ((bytetmp & BIT(0)) && retry < 1000) {
713 retry++;
714 udelay(50);
715 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
716 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
717 rtl_read_dword(rtlpriv,
718 0xEC),
719 bytetmp));
720 udelay(50);
721 }
722
723 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
724
725 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
726 udelay(2);
727
728 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
729
730 if (_rtl92ce_llt_table_init(hw) == false)
731 return false;;
732
733 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
734 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
735
736 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
737
738 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
739 wordtmp &= 0xf;
740 wordtmp |= 0xF771;
741 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
742
743 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
744 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
745 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
746
747 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
748
749 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
750 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
751 DMA_BIT_MASK(32));
752 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
753 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
754 DMA_BIT_MASK(32));
755 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
756 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
757 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
758 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
759 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
760 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
761 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
762 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
763 rtl_write_dword(rtlpriv, REG_HQ_DESA,
764 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
765 DMA_BIT_MASK(32));
766 rtl_write_dword(rtlpriv, REG_RX_DESA,
767 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
768 DMA_BIT_MASK(32));
769
770 if (IS_92C_SERIAL(rtlhal->version))
771 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
772 else
773 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
774
775 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
776
777 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
778 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
779 do {
780 retry++;
781 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
782 } while ((retry < 200) && (bytetmp & BIT(7)));
783
784 _rtl92ce_gen_refresh_led_state(hw);
785
786 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
787
788 return true;;
789}
790
791static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
792{
793 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
794 struct rtl_priv *rtlpriv = rtl_priv(hw);
795 u8 reg_bw_opmode;
796 u32 reg_ratr, reg_prsr;
797
798 reg_bw_opmode = BW_OPMODE_20MHZ;
799 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
800 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
801 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
802
803 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
804
805 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
806
807 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
808
809 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
810
811 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
812
813 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
814
815 rtl_write_word(rtlpriv, REG_RL, 0x0707);
816
817 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
818
819 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
820
821 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
822 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
823 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
824 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
825
826 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
827
828 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
829
830 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
831
832 rtlpci->reg_bcn_ctrl_val = 0x1f;
833 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
834
835 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
836
837 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
838
839 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
840 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
841
842 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
843
844 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
845
846 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
847
848 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
849
850 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
851 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
852
853 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
854
855 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
856
857 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
858 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
859
860}
861
862static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
863{
864 struct rtl_priv *rtlpriv = rtl_priv(hw);
865 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
866
867 rtl_write_byte(rtlpriv, 0x34b, 0x93);
868 rtl_write_word(rtlpriv, 0x350, 0x870c);
869 rtl_write_byte(rtlpriv, 0x352, 0x1);
870
871 if (ppsc->b_support_backdoor)
872 rtl_write_byte(rtlpriv, 0x349, 0x1b);
873 else
874 rtl_write_byte(rtlpriv, 0x349, 0x03);
875
876 rtl_write_word(rtlpriv, 0x350, 0x2718);
877 rtl_write_byte(rtlpriv, 0x352, 0x1);
878}
879
880void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
881{
882 struct rtl_priv *rtlpriv = rtl_priv(hw);
883 u8 sec_reg_value;
884
885 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
886 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
887 rtlpriv->sec.pairwise_enc_algorithm,
888 rtlpriv->sec.group_enc_algorithm));
889
890 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
891 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
892 "hw encryption\n"));
893 return;
894 }
895
896 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
897
898 if (rtlpriv->sec.use_defaultkey) {
899 sec_reg_value |= SCR_TxUseDK;
900 sec_reg_value |= SCR_RxUseDK;
901 }
902
903 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
904
905 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
906
907 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
908 ("The SECR-value %x\n", sec_reg_value));
909
910 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
911
912}
913
914int rtl92ce_hw_init(struct ieee80211_hw *hw)
915{
916 struct rtl_priv *rtlpriv = rtl_priv(hw);
917 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
918 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
919 struct rtl_phy *rtlphy = &(rtlpriv->phy);
920 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
921 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
922 static bool iqk_initialized; /* initialized to false */
923 bool rtstatus = true;
924 bool is92c;
925 int err;
926 u8 tmp_u1b;
927
928 rtlpci->being_init_adapter = true;
929 rtlpriv->intf_ops->disable_aspm(hw);
930 rtstatus = _rtl92ce_init_mac(hw);
931 if (rtstatus != true) {
932 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
933 err = 1;
934 return err;
935 }
936
937 err = rtl92c_download_fw(hw);
938 if (err) {
939 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
940 ("Failed to download FW. Init HW "
941 "without FW now..\n"));
942 err = 1;
943 rtlhal->bfw_ready = false;
944 return err;
945 } else {
946 rtlhal->bfw_ready = true;
947 }
948
949 rtlhal->last_hmeboxnum = 0;
950 rtl92c_phy_mac_config(hw);
951 rtl92c_phy_bb_config(hw);
952 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
953 rtl92c_phy_rf_config(hw);
954 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
955 RF_CHNLBW, RFREG_OFFSET_MASK);
956 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
957 RF_CHNLBW, RFREG_OFFSET_MASK);
958 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
959 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
960 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
961 _rtl92ce_hw_configure(hw);
962 rtl_cam_reset_all_entry(hw);
963 rtl92ce_enable_hw_security_config(hw);
964 ppsc->rfpwr_state = ERFON;
965 tmp_u1b = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG)&(~BIT(3));
966 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, tmp_u1b);
967 tmp_u1b = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
968 ppsc->rfoff_reason |= (tmp_u1b & BIT(3)) ? 0 : RF_CHANGE_BY_HW;
969 if (ppsc->rfoff_reason > RF_CHANGE_BY_PS)
970 rtl_ps_set_rf_state(hw, ERFOFF, ppsc->rfoff_reason, true);
971 else {
972 ppsc->rfpwr_state = ERFON;
973 ppsc->rfoff_reason = 0;
974 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
975 }
976 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
977 _rtl92ce_enable_aspm_back_door(hw);
978 rtlpriv->intf_ops->enable_aspm(hw);
979 if (ppsc->rfpwr_state == ERFON) {
980 rtl92c_phy_set_rfpath_switch(hw, 1);
981 if (iqk_initialized)
982 rtl92c_phy_iq_calibrate(hw, true);
983 else {
984 rtl92c_phy_iq_calibrate(hw, false);
985 iqk_initialized = true;
986 }
987
988 rtl92c_dm_check_txpower_tracking(hw);
989 rtl92c_phy_lc_calibrate(hw);
990 }
991
992 is92c = IS_92C_SERIAL(rtlhal->version);
993 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
994 if (!(tmp_u1b & BIT(0))) {
995 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
996 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
997 }
998
999 if (!(tmp_u1b & BIT(1)) && is92c) {
1000 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1001 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
1002 }
1003
1004 if (!(tmp_u1b & BIT(4))) {
1005 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1006 tmp_u1b &= 0x0F;
1007 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1008 udelay(10);
1009 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1010 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
1011 }
1012 rtl92c_dm_init(hw);
1013 rtlpci->being_init_adapter = false;
1014 return err;
1015}
1016
1017static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1018{
1019 struct rtl_priv *rtlpriv = rtl_priv(hw);
1020 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1021 enum version_8192c version = VERSION_UNKNOWN;
1022 u32 value32;
1023
1024 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1025 if (value32 & TRP_VAUX_EN) {
1026 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1027 VERSION_A_CHIP_88C;
1028 } else {
1029 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1030 VERSION_B_CHIP_88C;
1031 }
1032
1033 switch (version) {
1034 case VERSION_B_CHIP_92C:
1035 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1036 ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1037 break;
1038 case VERSION_B_CHIP_88C:
1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1040 ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1041 break;
1042 case VERSION_A_CHIP_92C:
1043 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1044 ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1045 break;
1046 case VERSION_A_CHIP_88C:
1047 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1048 ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1049 break;
1050 default:
1051 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1052 ("Chip Version ID: Unknown. Bug?\n"));
1053 break;
1054 }
1055
1056 switch (version & 0x3) {
1057 case CHIP_88C:
1058 rtlphy->rf_type = RF_1T1R;
1059 break;
1060 case CHIP_92C:
1061 rtlphy->rf_type = RF_2T2R;
1062 break;
1063 case CHIP_92C_1T2R:
1064 rtlphy->rf_type = RF_1T2R;
1065 break;
1066 default:
1067 rtlphy->rf_type = RF_1T1R;
1068 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1069 ("ERROR RF_Type is set!!"));
1070 break;
1071 }
1072
1073 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1074 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1075 "RF_2T2R" : "RF_1T1R"));
1076
1077 return version;
1078}
1079
1080static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1081 enum nl80211_iftype type)
1082{
1083 struct rtl_priv *rtlpriv = rtl_priv(hw);
1084 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1085 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1086 bt_msr &= 0xfc;
1087
1088 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1089 type == NL80211_IFTYPE_STATION) {
1090 _rtl92ce_stop_tx_beacon(hw);
1091 _rtl92ce_enable_bcn_sub_func(hw);
1092 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1093 _rtl92ce_resume_tx_beacon(hw);
1094 _rtl92ce_disable_bcn_sub_func(hw);
1095 } else {
1096 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1097 ("Set HW_VAR_MEDIA_STATUS: "
1098 "No such media status(%x).\n", type));
1099 }
1100
1101 switch (type) {
1102 case NL80211_IFTYPE_UNSPECIFIED:
1103 bt_msr |= MSR_NOLINK;
1104 ledaction = LED_CTL_LINK;
1105 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1106 ("Set Network type to NO LINK!\n"));
1107 break;
1108 case NL80211_IFTYPE_ADHOC:
1109 bt_msr |= MSR_ADHOC;
1110 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1111 ("Set Network type to Ad Hoc!\n"));
1112 break;
1113 case NL80211_IFTYPE_STATION:
1114 bt_msr |= MSR_INFRA;
1115 ledaction = LED_CTL_LINK;
1116 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1117 ("Set Network type to STA!\n"));
1118 break;
1119 case NL80211_IFTYPE_AP:
1120 bt_msr |= MSR_AP;
1121 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1122 ("Set Network type to AP!\n"));
1123 break;
1124 default:
1125 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1126 ("Network type %d not support!\n", type));
1127 return 1;
1128 break;
1129
1130 }
1131
1132 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1133 rtlpriv->cfg->ops->led_control(hw, ledaction);
1134 if ((bt_msr & 0xfc) == MSR_AP)
1135 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1136 else
1137 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1138 return 0;
1139}
1140
1141static void _rtl92ce_set_check_bssid(struct ieee80211_hw *hw,
1142 enum nl80211_iftype type)
1143{
1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1145 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1146 u8 filterout_non_associated_bssid = false;
1147
1148 switch (type) {
1149 case NL80211_IFTYPE_ADHOC:
1150 case NL80211_IFTYPE_STATION:
1151 filterout_non_associated_bssid = true;
1152 break;
1153 case NL80211_IFTYPE_UNSPECIFIED:
1154 case NL80211_IFTYPE_AP:
1155 default:
1156 break;
1157 }
1158
1159 if (filterout_non_associated_bssid == true) {
1160 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1161 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1162 (u8 *) (&reg_rcr));
1163 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1164 } else if (filterout_non_associated_bssid == false) {
1165 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1166 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1167 rtlpriv->cfg->ops->set_hw_reg(hw,
1168 HW_VAR_RCR, (u8 *) (&reg_rcr));
1169 }
1170}
1171
1172int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1173{
1174 if (_rtl92ce_set_media_status(hw, type))
1175 return -EOPNOTSUPP;
1176 _rtl92ce_set_check_bssid(hw, type);
1177 return 0;
1178}
1179
1180void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1181{
1182 struct rtl_priv *rtlpriv = rtl_priv(hw);
1183 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1184
1185 u32 u4b_ac_param;
1186
1187 rtl92c_dm_init_edca_turbo(hw);
1188
1189 u4b_ac_param = (u32) mac->ac[aci].aifs;
1190 u4b_ac_param |=
1191 ((u32) mac->ac[aci].cw_min & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
1192 u4b_ac_param |=
1193 ((u32) mac->ac[aci].cw_max & 0xF) << AC_PARAM_ECW_MAX_OFFSET;
1194 u4b_ac_param |= (u32) mac->ac[aci].tx_op << AC_PARAM_TXOP_LIMIT_OFFSET;
1195 RT_TRACE(rtlpriv, COMP_QOS, DBG_DMESG,
1196 ("queue:%x, ac_param:%x aifs:%x cwmin:%x cwmax:%x txop:%x\n",
1197 aci, u4b_ac_param, mac->ac[aci].aifs, mac->ac[aci].cw_min,
1198 mac->ac[aci].cw_max, mac->ac[aci].tx_op));
1199 switch (aci) {
1200 case AC1_BK:
1201 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
1202 break;
1203 case AC0_BE:
1204 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
1205 break;
1206 case AC2_VI:
1207 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
1208 break;
1209 case AC3_VO:
1210 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
1211 break;
1212 default:
1213 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1214 break;
1215 }
1216}
1217
1218void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1219{
1220 struct rtl_priv *rtlpriv = rtl_priv(hw);
1221 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1222
1223 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1224 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1225 rtlpci->irq_enabled = true;
1226}
1227
1228void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1229{
1230 struct rtl_priv *rtlpriv = rtl_priv(hw);
1231 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1232
1233 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1234 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1235 rtlpci->irq_enabled = false;
1236}
1237
1238static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1239{
1240 struct rtl_priv *rtlpriv = rtl_priv(hw);
1241 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1242 u8 u1b_tmp;
1243
1244 rtlpriv->intf_ops->enable_aspm(hw);
1245 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1246 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1247 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1248 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1249 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1250 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1251 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->bfw_ready)
1252 rtl92c_firmware_selfreset(hw);
1253 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1254 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1255 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1256 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1257 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1258 (u1b_tmp << 8));
1259 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1260 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1261 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1262 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1263 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1264 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1265 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1266}
1267
1268void rtl92ce_card_disable(struct ieee80211_hw *hw)
1269{
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1272 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1273 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1274 enum nl80211_iftype opmode;
1275
1276 mac->link_state = MAC80211_NOLINK;
1277 opmode = NL80211_IFTYPE_UNSPECIFIED;
1278 _rtl92ce_set_media_status(hw, opmode);
1279 if (rtlpci->driver_is_goingto_unload ||
1280 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1281 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1282 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1283 _rtl92ce_poweroff_adapter(hw);
1284}
1285
1286void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1287 u32 *p_inta, u32 *p_intb)
1288{
1289 struct rtl_priv *rtlpriv = rtl_priv(hw);
1290 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1291
1292 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1293 rtl_write_dword(rtlpriv, ISR, *p_inta);
1294
1295 /*
1296 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1297 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1298 */
1299}
1300
1301void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1302{
1303
1304 struct rtl_priv *rtlpriv = rtl_priv(hw);
1305 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1306 u16 bcn_interval, atim_window;
1307
1308 bcn_interval = mac->beacon_interval;
1309 atim_window = 2; /*FIX MERGE */
1310 rtl92ce_disable_interrupt(hw);
1311 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1312 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1313 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1314 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1315 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1316 rtl_write_byte(rtlpriv, 0x606, 0x30);
1317 rtl92ce_enable_interrupt(hw);
1318}
1319
1320void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1321{
1322 struct rtl_priv *rtlpriv = rtl_priv(hw);
1323 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1324 u16 bcn_interval = mac->beacon_interval;
1325
1326 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1327 ("beacon_interval:%d\n", bcn_interval));
1328 rtl92ce_disable_interrupt(hw);
1329 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1330 rtl92ce_enable_interrupt(hw);
1331}
1332
1333void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1334 u32 add_msr, u32 rm_msr)
1335{
1336 struct rtl_priv *rtlpriv = rtl_priv(hw);
1337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1338
1339 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1340 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1341 if (add_msr)
1342 rtlpci->irq_mask[0] |= add_msr;
1343 if (rm_msr)
1344 rtlpci->irq_mask[0] &= (~rm_msr);
1345 rtl92ce_disable_interrupt(hw);
1346 rtl92ce_enable_interrupt(hw);
1347}
1348
1349static u8 _rtl92c_get_chnl_group(u8 chnl)
1350{
1351 u8 group;
1352
1353 if (chnl < 3)
1354 group = 0;
1355 else if (chnl < 9)
1356 group = 1;
1357 else
1358 group = 2;
1359 return group;
1360}
1361
1362static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1363 bool autoload_fail,
1364 u8 *hwinfo)
1365{
1366 struct rtl_priv *rtlpriv = rtl_priv(hw);
1367 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1368 u8 rf_path, index, tempval;
1369 u16 i;
1370
1371 for (rf_path = 0; rf_path < 2; rf_path++) {
1372 for (i = 0; i < 3; i++) {
1373 if (!autoload_fail) {
1374 rtlefuse->
1375 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1376 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1377 rtlefuse->
1378 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1379 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1380 i];
1381 } else {
1382 rtlefuse->
1383 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1384 EEPROM_DEFAULT_TXPOWERLEVEL;
1385 rtlefuse->
1386 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1387 EEPROM_DEFAULT_TXPOWERLEVEL;
1388 }
1389 }
1390 }
1391
1392 for (i = 0; i < 3; i++) {
1393 if (!autoload_fail)
1394 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1395 else
1396 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1397 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1398 (tempval & 0xf);
1399 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1400 ((tempval & 0xf0) >> 4);
1401 }
1402
1403 for (rf_path = 0; rf_path < 2; rf_path++)
1404 for (i = 0; i < 3; i++)
1405 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1406 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1407 i,
1408 rtlefuse->
1409 eeprom_chnlarea_txpwr_cck[rf_path][i]));
1410 for (rf_path = 0; rf_path < 2; rf_path++)
1411 for (i = 0; i < 3; i++)
1412 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1413 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1414 rf_path, i,
1415 rtlefuse->
1416 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1417 for (rf_path = 0; rf_path < 2; rf_path++)
1418 for (i = 0; i < 3; i++)
1419 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1420 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1421 rf_path, i,
1422 rtlefuse->
1423 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1424 [i]));
1425
1426 for (rf_path = 0; rf_path < 2; rf_path++) {
1427 for (i = 0; i < 14; i++) {
1428 index = _rtl92c_get_chnl_group((u8) i);
1429
1430 rtlefuse->txpwrlevel_cck[rf_path][i] =
1431 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1432 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1433 rtlefuse->
1434 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1435
1436 if ((rtlefuse->
1437 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1438 rtlefuse->
1439 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1440 > 0) {
1441 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1442 rtlefuse->
1443 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1444 [index] -
1445 rtlefuse->
1446 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1447 [index];
1448 } else {
1449 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1450 }
1451 }
1452
1453 for (i = 0; i < 14; i++) {
1454 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1455 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1456 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1457 rtlefuse->txpwrlevel_cck[rf_path][i],
1458 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1459 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1460 }
1461 }
1462
1463 for (i = 0; i < 3; i++) {
1464 if (!autoload_fail) {
1465 rtlefuse->eeprom_pwrlimit_ht40[i] =
1466 hwinfo[EEPROM_TXPWR_GROUP + i];
1467 rtlefuse->eeprom_pwrlimit_ht20[i] =
1468 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1469 } else {
1470 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1471 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1472 }
1473 }
1474
1475 for (rf_path = 0; rf_path < 2; rf_path++) {
1476 for (i = 0; i < 14; i++) {
1477 index = _rtl92c_get_chnl_group((u8) i);
1478
1479 if (rf_path == RF90_PATH_A) {
1480 rtlefuse->pwrgroup_ht20[rf_path][i] =
1481 (rtlefuse->eeprom_pwrlimit_ht20[index]
1482 & 0xf);
1483 rtlefuse->pwrgroup_ht40[rf_path][i] =
1484 (rtlefuse->eeprom_pwrlimit_ht40[index]
1485 & 0xf);
1486 } else if (rf_path == RF90_PATH_B) {
1487 rtlefuse->pwrgroup_ht20[rf_path][i] =
1488 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1489 & 0xf0) >> 4);
1490 rtlefuse->pwrgroup_ht40[rf_path][i] =
1491 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1492 & 0xf0) >> 4);
1493 }
1494
1495 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1496 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1497 rf_path, i,
1498 rtlefuse->pwrgroup_ht20[rf_path][i]));
1499 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1500 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1501 rf_path, i,
1502 rtlefuse->pwrgroup_ht40[rf_path][i]));
1503 }
1504 }
1505
1506 for (i = 0; i < 14; i++) {
1507 index = _rtl92c_get_chnl_group((u8) i);
1508
1509 if (!autoload_fail)
1510 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1511 else
1512 tempval = EEPROM_DEFAULT_HT20_DIFF;
1513
1514 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1515 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1516 ((tempval >> 4) & 0xF);
1517
1518 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1519 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1520
1521 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1522 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1523
1524 index = _rtl92c_get_chnl_group((u8) i);
1525
1526 if (!autoload_fail)
1527 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1528 else
1529 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1530
1531 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1532 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1533 ((tempval >> 4) & 0xF);
1534 }
1535
1536 rtlefuse->legacy_ht_txpowerdiff =
1537 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1538
1539 for (i = 0; i < 14; i++)
1540 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1541 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1542 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1543 for (i = 0; i < 14; i++)
1544 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1545 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1546 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1547 for (i = 0; i < 14; i++)
1548 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1549 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1550 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1551 for (i = 0; i < 14; i++)
1552 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1553 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1554 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1555
1556 if (!autoload_fail)
1557 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1558 else
1559 rtlefuse->eeprom_regulatory = 0;
1560 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1561 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1562
1563 if (!autoload_fail) {
1564 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1565 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1566 } else {
1567 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1568 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1569 }
1570 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1571 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1572 rtlefuse->eeprom_tssi[RF90_PATH_A],
1573 rtlefuse->eeprom_tssi[RF90_PATH_B]));
1574
1575 if (!autoload_fail)
1576 tempval = hwinfo[EEPROM_THERMAL_METER];
1577 else
1578 tempval = EEPROM_DEFAULT_THERMALMETER;
1579 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1580
1581 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1582 rtlefuse->b_apk_thermalmeterignore = true;
1583
1584 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1585 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1586 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1587}
1588
1589static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1590{
1591 struct rtl_priv *rtlpriv = rtl_priv(hw);
1592 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1593 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1594 u16 i, usvalue;
1595 u8 hwinfo[HWSET_MAX_SIZE];
1596 u16 eeprom_id;
1597
1598 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1599 rtl_efuse_shadow_map_update(hw);
1600
1601 memcpy((void *)hwinfo,
1602 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1603 HWSET_MAX_SIZE);
1604 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1605 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1606 ("RTL819X Not boot from eeprom, check it !!"));
1607 }
1608
1609 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
1610 hwinfo, HWSET_MAX_SIZE);
1611
1612 eeprom_id = *((u16 *)&hwinfo[0]);
1613 if (eeprom_id != RTL8190_EEPROM_ID) {
1614 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1615 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1616 rtlefuse->autoload_failflag = true;
1617 } else {
1618 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1619 rtlefuse->autoload_failflag = false;
1620 }
1621
1622 if (rtlefuse->autoload_failflag == true)
1623 return;
1624
1625 for (i = 0; i < 6; i += 2) {
1626 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1627 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1628 }
1629
1630 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1631 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1632
1633 _rtl92ce_read_txpower_info_from_hwpg(hw,
1634 rtlefuse->autoload_failflag,
1635 hwinfo);
1636
1637 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1638 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1639 rtlefuse->b_txpwr_fromeprom = true;
1640 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1641
1642 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1643 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1644
1645 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1646 switch (rtlefuse->eeprom_oemid) {
1647 case EEPROM_CID_DEFAULT:
1648 if (rtlefuse->eeprom_did == 0x8176) {
1649 if ((rtlefuse->eeprom_svid == 0x103C &&
1650 rtlefuse->eeprom_smid == 0x1629))
1651 rtlhal->oem_id = RT_CID_819x_HP;
1652 else
1653 rtlhal->oem_id = RT_CID_DEFAULT;
1654 } else {
1655 rtlhal->oem_id = RT_CID_DEFAULT;
1656 }
1657 break;
1658 case EEPROM_CID_TOSHIBA:
1659 rtlhal->oem_id = RT_CID_TOSHIBA;
1660 break;
1661 case EEPROM_CID_QMI:
1662 rtlhal->oem_id = RT_CID_819x_QMI;
1663 break;
1664 case EEPROM_CID_WHQL:
1665 default:
1666 rtlhal->oem_id = RT_CID_DEFAULT;
1667 break;
1668
1669 }
1670 }
1671
1672}
1673
1674static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1675{
1676 struct rtl_priv *rtlpriv = rtl_priv(hw);
1677 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1678 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1679
1680 switch (rtlhal->oem_id) {
1681 case RT_CID_819x_HP:
1682 pcipriv->ledctl.bled_opendrain = true;
1683 break;
1684 case RT_CID_819x_Lenovo:
1685 case RT_CID_DEFAULT:
1686 case RT_CID_TOSHIBA:
1687 case RT_CID_CCX:
1688 case RT_CID_819x_Acer:
1689 case RT_CID_WHQL:
1690 default:
1691 break;
1692 }
1693 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1694 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1695}
1696
1697void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1698{
1699 struct rtl_priv *rtlpriv = rtl_priv(hw);
1700 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1701 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1702 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1703 u8 tmp_u1b;
1704
1705 rtlhal->version = _rtl92ce_read_chip_version(hw);
1706 if (get_rf_type(rtlphy) == RF_1T1R)
1707 rtlpriv->dm.brfpath_rxenable[0] = true;
1708 else
1709 rtlpriv->dm.brfpath_rxenable[0] =
1710 rtlpriv->dm.brfpath_rxenable[1] = true;
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1712 rtlhal->version));
1713 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1714 if (tmp_u1b & BIT(4)) {
1715 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1716 rtlefuse->epromtype = EEPROM_93C46;
1717 } else {
1718 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1719 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1720 }
1721 if (tmp_u1b & BIT(5)) {
1722 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1723 rtlefuse->autoload_failflag = false;
1724 _rtl92ce_read_adapter_info(hw);
1725 } else {
1726 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1727 }
1728
1729 _rtl92ce_hal_customized_behavior(hw);
1730}
1731
1732void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
1733{
1734 struct rtl_priv *rtlpriv = rtl_priv(hw);
1735 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1736 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1737
1738 u32 ratr_value = (u32) mac->basic_rates;
1739 u8 *p_mcsrate = mac->mcs;
1740 u8 ratr_index = 0;
1741 u8 b_nmode = mac->ht_enable;
1742 u8 mimo_ps = 1;
1743 u16 shortgi_rate;
1744 u32 tmp_ratr_value;
1745 u8 b_curtxbw_40mhz = mac->bw_40;
1746 u8 b_curshortgi_40mhz = mac->sgi_40;
1747 u8 b_curshortgi_20mhz = mac->sgi_20;
1748 enum wireless_mode wirelessmode = mac->mode;
1749
1750 ratr_value |= EF2BYTE((*(u16 *) (p_mcsrate))) << 12;
1751
1752 switch (wirelessmode) {
1753 case WIRELESS_MODE_B:
1754 if (ratr_value & 0x0000000c)
1755 ratr_value &= 0x0000000d;
1756 else
1757 ratr_value &= 0x0000000f;
1758 break;
1759 case WIRELESS_MODE_G:
1760 ratr_value &= 0x00000FF5;
1761 break;
1762 case WIRELESS_MODE_N_24G:
1763 case WIRELESS_MODE_N_5G:
1764 b_nmode = 1;
1765 if (mimo_ps == 0) {
1766 ratr_value &= 0x0007F005;
1767 } else {
1768 u32 ratr_mask;
1769
1770 if (get_rf_type(rtlphy) == RF_1T2R ||
1771 get_rf_type(rtlphy) == RF_1T1R)
1772 ratr_mask = 0x000ff005;
1773 else
1774 ratr_mask = 0x0f0ff005;
1775
1776 ratr_value &= ratr_mask;
1777 }
1778 break;
1779 default:
1780 if (rtlphy->rf_type == RF_1T2R)
1781 ratr_value &= 0x000ff0ff;
1782 else
1783 ratr_value &= 0x0f0ff0ff;
1784
1785 break;
1786 }
1787
1788 ratr_value &= 0x0FFFFFFF;
1789
1790 if (b_nmode && ((b_curtxbw_40mhz &&
1791 b_curshortgi_40mhz) || (!b_curtxbw_40mhz &&
1792 b_curshortgi_20mhz))) {
1793
1794 ratr_value |= 0x10000000;
1795 tmp_ratr_value = (ratr_value >> 12);
1796
1797 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1798 if ((1 << shortgi_rate) & tmp_ratr_value)
1799 break;
1800 }
1801
1802 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1803 (shortgi_rate << 4) | (shortgi_rate);
1804 }
1805
1806 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1807
1808 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1809 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1810}
1811
1812void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1813{
1814 struct rtl_priv *rtlpriv = rtl_priv(hw);
1815 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1816 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1817 u32 ratr_bitmap = (u32) mac->basic_rates;
1818 u8 *p_mcsrate = mac->mcs;
1819 u8 ratr_index;
1820 u8 b_curtxbw_40mhz = mac->bw_40;
1821 u8 b_curshortgi_40mhz = mac->sgi_40;
1822 u8 b_curshortgi_20mhz = mac->sgi_20;
1823 enum wireless_mode wirelessmode = mac->mode;
1824 bool b_shortgi = false;
1825 u8 rate_mask[5];
1826 u8 macid = 0;
1827 u8 mimops = 1;
1828
1829 ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
1830 switch (wirelessmode) {
1831 case WIRELESS_MODE_B:
1832 ratr_index = RATR_INX_WIRELESS_B;
1833 if (ratr_bitmap & 0x0000000c)
1834 ratr_bitmap &= 0x0000000d;
1835 else
1836 ratr_bitmap &= 0x0000000f;
1837 break;
1838 case WIRELESS_MODE_G:
1839 ratr_index = RATR_INX_WIRELESS_GB;
1840
1841 if (rssi_level == 1)
1842 ratr_bitmap &= 0x00000f00;
1843 else if (rssi_level == 2)
1844 ratr_bitmap &= 0x00000ff0;
1845 else
1846 ratr_bitmap &= 0x00000ff5;
1847 break;
1848 case WIRELESS_MODE_A:
1849 ratr_index = RATR_INX_WIRELESS_A;
1850 ratr_bitmap &= 0x00000ff0;
1851 break;
1852 case WIRELESS_MODE_N_24G:
1853 case WIRELESS_MODE_N_5G:
1854 ratr_index = RATR_INX_WIRELESS_NGB;
1855
1856 if (mimops == 0) {
1857 if (rssi_level == 1)
1858 ratr_bitmap &= 0x00070000;
1859 else if (rssi_level == 2)
1860 ratr_bitmap &= 0x0007f000;
1861 else
1862 ratr_bitmap &= 0x0007f005;
1863 } else {
1864 if (rtlphy->rf_type == RF_1T2R ||
1865 rtlphy->rf_type == RF_1T1R) {
1866 if (b_curtxbw_40mhz) {
1867 if (rssi_level == 1)
1868 ratr_bitmap &= 0x000f0000;
1869 else if (rssi_level == 2)
1870 ratr_bitmap &= 0x000ff000;
1871 else
1872 ratr_bitmap &= 0x000ff015;
1873 } else {
1874 if (rssi_level == 1)
1875 ratr_bitmap &= 0x000f0000;
1876 else if (rssi_level == 2)
1877 ratr_bitmap &= 0x000ff000;
1878 else
1879 ratr_bitmap &= 0x000ff005;
1880 }
1881 } else {
1882 if (b_curtxbw_40mhz) {
1883 if (rssi_level == 1)
1884 ratr_bitmap &= 0x0f0f0000;
1885 else if (rssi_level == 2)
1886 ratr_bitmap &= 0x0f0ff000;
1887 else
1888 ratr_bitmap &= 0x0f0ff015;
1889 } else {
1890 if (rssi_level == 1)
1891 ratr_bitmap &= 0x0f0f0000;
1892 else if (rssi_level == 2)
1893 ratr_bitmap &= 0x0f0ff000;
1894 else
1895 ratr_bitmap &= 0x0f0ff005;
1896 }
1897 }
1898 }
1899
1900 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
1901 (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
1902
1903 if (macid == 0)
1904 b_shortgi = true;
1905 else if (macid == 1)
1906 b_shortgi = false;
1907 }
1908 break;
1909 default:
1910 ratr_index = RATR_INX_WIRELESS_NGB;
1911
1912 if (rtlphy->rf_type == RF_1T2R)
1913 ratr_bitmap &= 0x000ff0ff;
1914 else
1915 ratr_bitmap &= 0x0f0ff0ff;
1916 break;
1917 }
1918 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1919 ("ratr_bitmap :%x\n", ratr_bitmap));
1920 *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1921 (ratr_index << 28));
1922 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
1923 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1924 "ratr_val:%x, %x:%x:%x:%x:%x\n",
1925 ratr_index, ratr_bitmap,
1926 rate_mask[0], rate_mask[1],
1927 rate_mask[2], rate_mask[3],
1928 rate_mask[4]));
1929 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1930}
1931
1932void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1933{
1934 struct rtl_priv *rtlpriv = rtl_priv(hw);
1935 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1936 u16 sifs_timer;
1937
1938 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1939 (u8 *)&mac->slot_time);
1940 if (!mac->ht_enable)
1941 sifs_timer = 0x0a0a;
1942 else
1943 sifs_timer = 0x1010;
1944 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1945}
1946
1947bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
1948{
1949 struct rtl_priv *rtlpriv = rtl_priv(hw);
1950 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1951 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1952 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1953 u8 u1tmp;
1954 bool b_actuallyset = false;
1955 unsigned long flag;
1956
1957 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
1958 return false;
1959
1960 if (ppsc->b_swrf_processing)
1961 return false;
1962
1963 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1964 if (ppsc->rfchange_inprogress) {
1965 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1966 return false;
1967 } else {
1968 ppsc->rfchange_inprogress = true;
1969 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1970 }
1971
1972 cur_rfstate = ppsc->rfpwr_state;
1973
1974 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
1975 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
1976 rtlpriv->intf_ops->disable_aspm(hw);
1977 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1978 }
1979
1980 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1981 REG_MAC_PINMUX_CFG)&~(BIT(3)));
1982
1983 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1984 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1985
1986 if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
1987 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1988 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
1989
1990 e_rfpowerstate_toset = ERFON;
1991 ppsc->b_hwradiooff = false;
1992 b_actuallyset = true;
1993 } else if ((ppsc->b_hwradiooff == false)
1994 && (e_rfpowerstate_toset == ERFOFF)) {
1995 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1996 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
1997
1998 e_rfpowerstate_toset = ERFOFF;
1999 ppsc->b_hwradiooff = true;
2000 b_actuallyset = true;
2001 }
2002
2003 if (b_actuallyset) {
2004 if (e_rfpowerstate_toset == ERFON) {
2005 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2006 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
2007 rtlpriv->intf_ops->disable_aspm(hw);
2008 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2009 }
2010 }
2011
2012 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2013 ppsc->rfchange_inprogress = false;
2014 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2015
2016 if (e_rfpowerstate_toset == ERFOFF) {
2017 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
2018 rtlpriv->intf_ops->enable_aspm(hw);
2019 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2020 }
2021 }
2022
2023 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2024 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2025 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2026
2027 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
2028 rtlpriv->intf_ops->enable_aspm(hw);
2029 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2030 }
2031
2032 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2033 ppsc->rfchange_inprogress = false;
2034 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2035 } else {
2036 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2037 ppsc->rfchange_inprogress = false;
2038 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2039 }
2040
2041 *valid = 1;
2042 return !ppsc->b_hwradiooff;
2043
2044}
2045
2046void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2047 u8 *p_macaddr, bool is_group, u8 enc_algo,
2048 bool is_wepkey, bool clear_all)
2049{
2050 struct rtl_priv *rtlpriv = rtl_priv(hw);
2051 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2052 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2053 u8 *macaddr = p_macaddr;
2054 u32 entry_id = 0;
2055 bool is_pairwise = false;
2056
2057 static u8 cam_const_addr[4][6] = {
2058 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2059 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2060 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2061 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2062 };
2063 static u8 cam_const_broad[] = {
2064 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2065 };
2066
2067 if (clear_all) {
2068 u8 idx = 0;
2069 u8 cam_offset = 0;
2070 u8 clear_number = 5;
2071
2072 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2073
2074 for (idx = 0; idx < clear_number; idx++) {
2075 rtl_cam_mark_invalid(hw, cam_offset + idx);
2076 rtl_cam_empty_entry(hw, cam_offset + idx);
2077
2078 if (idx < 5) {
2079 memset(rtlpriv->sec.key_buf[idx], 0,
2080 MAX_KEY_LEN);
2081 rtlpriv->sec.key_len[idx] = 0;
2082 }
2083 }
2084
2085 } else {
2086 switch (enc_algo) {
2087 case WEP40_ENCRYPTION:
2088 enc_algo = CAM_WEP40;
2089 break;
2090 case WEP104_ENCRYPTION:
2091 enc_algo = CAM_WEP104;
2092 break;
2093 case TKIP_ENCRYPTION:
2094 enc_algo = CAM_TKIP;
2095 break;
2096 case AESCCMP_ENCRYPTION:
2097 enc_algo = CAM_AES;
2098 break;
2099 default:
2100 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2101 "not process\n"));
2102 enc_algo = CAM_TKIP;
2103 break;
2104 }
2105
2106 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2107 macaddr = cam_const_addr[key_index];
2108 entry_id = key_index;
2109 } else {
2110 if (is_group) {
2111 macaddr = cam_const_broad;
2112 entry_id = key_index;
2113 } else {
2114 key_index = PAIRWISE_KEYIDX;
2115 entry_id = CAM_PAIRWISE_KEY_POSITION;
2116 is_pairwise = true;
2117 }
2118 }
2119
2120 if (rtlpriv->sec.key_len[key_index] == 0) {
2121 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2122 ("delete one entry\n"));
2123 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2124 } else {
2125 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2126 ("The insert KEY length is %d\n",
2127 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2128 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2129 ("The insert KEY is %x %x\n",
2130 rtlpriv->sec.key_buf[0][0],
2131 rtlpriv->sec.key_buf[0][1]));
2132
2133 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2134 ("add one entry\n"));
2135 if (is_pairwise) {
2136 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2137 "Pairwiase Key content :",
2138 rtlpriv->sec.pairwise_key,
2139 rtlpriv->sec.
2140 key_len[PAIRWISE_KEYIDX]);
2141
2142 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2143 ("set Pairwiase key\n"));
2144
2145 rtl_cam_add_one_entry(hw, macaddr, key_index,
2146 entry_id, enc_algo,
2147 CAM_CONFIG_NO_USEDK,
2148 rtlpriv->sec.
2149 key_buf[key_index]);
2150 } else {
2151 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2152 ("set group key\n"));
2153
2154 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2155 rtl_cam_add_one_entry(hw,
2156 rtlefuse->dev_addr,
2157 PAIRWISE_KEYIDX,
2158 CAM_PAIRWISE_KEY_POSITION,
2159 enc_algo,
2160 CAM_CONFIG_NO_USEDK,
2161 rtlpriv->sec.key_buf
2162 [entry_id]);
2163 }
2164
2165 rtl_cam_add_one_entry(hw, macaddr, key_index,
2166 entry_id, enc_algo,
2167 CAM_CONFIG_NO_USEDK,
2168 rtlpriv->sec.key_buf[entry_id]);
2169 }
2170
2171 }
2172 }
2173}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 03:26:47 -0500