diff options
author | Stanislaw Gruszka <sgruszka@redhat.com> | 2011-08-24 09:14:03 -0400 |
---|---|---|
committer | Stanislaw Gruszka <sgruszka@redhat.com> | 2011-11-15 05:22:15 -0500 |
commit | 841b2ccac3251fdbf7a0bc26724874cdc35df96c (patch) | |
tree | 009166cc494f8b4c1aa4247b40e0bd82ce63e41f /drivers/net/wireless/iwlegacy | |
parent | b6297cd2aa4ec318b3634e6c1ca4cf063a0042c9 (diff) |
iwlegacy: rename il_{read,write}32 to _il_{rd,wr}
Introduce rule that underscore at the beginning mean unlocked I/O method.
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Diffstat (limited to 'drivers/net/wireless/iwlegacy')
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-3945.c | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-4965-led.c | 6 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-core.c | 10 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-csr.h | 6 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-debugfs.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-eeprom.c | 6 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-helpers.h | 10 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-io.h | 23 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-rx.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-tx.c | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl3945-base.c | 42 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl4965-base.c | 56 |
12 files changed, 84 insertions, 87 deletions
diff --git a/drivers/net/wireless/iwlegacy/iwl-3945.c b/drivers/net/wireless/iwlegacy/iwl-3945.c index cf47fdb28aa1..6e2e71acbef6 100644 --- a/drivers/net/wireless/iwlegacy/iwl-3945.c +++ b/drivers/net/wireless/iwlegacy/iwl-3945.c | |||
@@ -1058,7 +1058,7 @@ static inline int il3945_hw_reg_temp_out_of_range(int temperature) | |||
1058 | 1058 | ||
1059 | int il3945_hw_get_temperature(struct il_priv *il) | 1059 | int il3945_hw_get_temperature(struct il_priv *il) |
1060 | { | 1060 | { |
1061 | return il_read32(il, CSR_UCODE_DRV_GP2); | 1061 | return _il_rd(il, CSR_UCODE_DRV_GP2); |
1062 | } | 1062 | } |
1063 | 1063 | ||
1064 | /** | 1064 | /** |
@@ -2211,7 +2211,7 @@ int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) | |||
2211 | FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); | 2211 | FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); |
2212 | 2212 | ||
2213 | /* fake read to flush all prev. writes */ | 2213 | /* fake read to flush all prev. writes */ |
2214 | il_read32(il, FH39_TSSR_CBB_BASE); | 2214 | _il_rd(il, FH39_TSSR_CBB_BASE); |
2215 | 2215 | ||
2216 | return 0; | 2216 | return 0; |
2217 | } | 2217 | } |
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-led.c b/drivers/net/wireless/iwlegacy/iwl-4965-led.c index 1436a1b7ebf6..48541577202a 100644 --- a/drivers/net/wireless/iwlegacy/iwl-4965-led.c +++ b/drivers/net/wireless/iwlegacy/iwl-4965-led.c | |||
@@ -55,9 +55,9 @@ il4965_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd) | |||
55 | }; | 55 | }; |
56 | u32 reg; | 56 | u32 reg; |
57 | 57 | ||
58 | reg = il_read32(il, CSR_LED_REG); | 58 | reg = _il_rd(il, CSR_LED_REG); |
59 | if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) | 59 | if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) |
60 | il_write32(il, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); | 60 | _il_wr(il, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); |
61 | 61 | ||
62 | return il_send_cmd(il, &cmd); | 62 | return il_send_cmd(il, &cmd); |
63 | } | 63 | } |
@@ -65,7 +65,7 @@ il4965_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd) | |||
65 | /* Set led register off */ | 65 | /* Set led register off */ |
66 | void il4965_led_enable(struct il_priv *il) | 66 | void il4965_led_enable(struct il_priv *il) |
67 | { | 67 | { |
68 | il_write32(il, CSR_LED_REG, CSR_LED_REG_TRUN_ON); | 68 | _il_wr(il, CSR_LED_REG, CSR_LED_REG_TRUN_ON); |
69 | } | 69 | } |
70 | 70 | ||
71 | const struct il_led_ops il4965_led_ops = { | 71 | const struct il_led_ops il4965_led_ops = { |
diff --git a/drivers/net/wireless/iwlegacy/iwl-core.c b/drivers/net/wireless/iwlegacy/iwl-core.c index 42be833bdc75..c5ffd91af5d0 100644 --- a/drivers/net/wireless/iwlegacy/iwl-core.c +++ b/drivers/net/wireless/iwlegacy/iwl-core.c | |||
@@ -2001,7 +2001,7 @@ int il_pci_resume(struct device *device) | |||
2001 | 2001 | ||
2002 | il_enable_interrupts(il); | 2002 | il_enable_interrupts(il); |
2003 | 2003 | ||
2004 | if (!(il_read32(il, CSR_GP_CNTRL) & | 2004 | if (!(_il_rd(il, CSR_GP_CNTRL) & |
2005 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | 2005 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
2006 | hw_rfkill = true; | 2006 | hw_rfkill = true; |
2007 | 2007 | ||
@@ -2580,12 +2580,12 @@ irqreturn_t il_isr(int irq, void *data) | |||
2580 | * back-to-back ISRs and sporadic interrupts from our NIC. | 2580 | * back-to-back ISRs and sporadic interrupts from our NIC. |
2581 | * If we have something to service, the tasklet will re-enable ints. | 2581 | * If we have something to service, the tasklet will re-enable ints. |
2582 | * If we *don't* have something, we'll re-enable before leaving here. */ | 2582 | * If we *don't* have something, we'll re-enable before leaving here. */ |
2583 | inta_mask = il_read32(il, CSR_INT_MASK); /* just for debug */ | 2583 | inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */ |
2584 | il_write32(il, CSR_INT_MASK, 0x00000000); | 2584 | _il_wr(il, CSR_INT_MASK, 0x00000000); |
2585 | 2585 | ||
2586 | /* Discover which interrupts are active/pending */ | 2586 | /* Discover which interrupts are active/pending */ |
2587 | inta = il_read32(il, CSR_INT); | 2587 | inta = _il_rd(il, CSR_INT); |
2588 | inta_fh = il_read32(il, CSR_FH_INT_STATUS); | 2588 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
2589 | 2589 | ||
2590 | /* Ignore interrupt if there's nothing in NIC to service. | 2590 | /* Ignore interrupt if there's nothing in NIC to service. |
2591 | * This may be due to IRQ shared with another device, | 2591 | * This may be due to IRQ shared with another device, |
diff --git a/drivers/net/wireless/iwlegacy/iwl-csr.h b/drivers/net/wireless/iwlegacy/iwl-csr.h index 24b71ae79040..faffb8e180b4 100644 --- a/drivers/net/wireless/iwlegacy/iwl-csr.h +++ b/drivers/net/wireless/iwlegacy/iwl-csr.h | |||
@@ -70,7 +70,7 @@ | |||
70 | * low power states due to driver-invoked device resets | 70 | * low power states due to driver-invoked device resets |
71 | * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. | 71 | * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. |
72 | * | 72 | * |
73 | * Use il_write32() and il_read32() family to access these registers; | 73 | * Use _il_wr() and _il_rd() family to access these registers; |
74 | * these provide simple PCI bus access, without waking up the MAC. | 74 | * these provide simple PCI bus access, without waking up the MAC. |
75 | * Do not use il_write_direct32() family for these registers; | 75 | * Do not use il_write_direct32() family for these registers; |
76 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. | 76 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. |
@@ -91,7 +91,7 @@ | |||
91 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ | 91 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ |
92 | #define CSR_GP_CNTRL (CSR_BASE+0x024) | 92 | #define CSR_GP_CNTRL (CSR_BASE+0x024) |
93 | 93 | ||
94 | /* 2nd byte of CSR_INT_COALESCING, not accessible via il_write32()! */ | 94 | /* 2nd byte of CSR_INT_COALESCING, not accessible via _il_wr()! */ |
95 | #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) | 95 | #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) |
96 | 96 | ||
97 | /* | 97 | /* |
@@ -374,7 +374,7 @@ | |||
374 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing | 374 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing |
375 | * internal resources. | 375 | * internal resources. |
376 | * | 376 | * |
377 | * Do not use il_write32()/il_read32() family to access these registers; | 377 | * Do not use _il_wr()/_il_rd() family to access these registers; |
378 | * these provide only simple PCI bus access, without waking up the MAC. | 378 | * these provide only simple PCI bus access, without waking up the MAC. |
379 | */ | 379 | */ |
380 | #define HBUS_BASE (0x400) | 380 | #define HBUS_BASE (0x400) |
diff --git a/drivers/net/wireless/iwlegacy/iwl-debugfs.c b/drivers/net/wireless/iwlegacy/iwl-debugfs.c index 45b71a8b9af5..cd15e67c94d3 100644 --- a/drivers/net/wireless/iwlegacy/iwl-debugfs.c +++ b/drivers/net/wireless/iwlegacy/iwl-debugfs.c | |||
@@ -1018,7 +1018,7 @@ static ssize_t il_dbgfs_power_save_status_read(struct file *file, | |||
1018 | const size_t bufsz = sizeof(buf); | 1018 | const size_t bufsz = sizeof(buf); |
1019 | u32 pwrsave_status; | 1019 | u32 pwrsave_status; |
1020 | 1020 | ||
1021 | pwrsave_status = il_read32(il, CSR_GP_CNTRL) & | 1021 | pwrsave_status = _il_rd(il, CSR_GP_CNTRL) & |
1022 | CSR_GP_REG_POWER_SAVE_STATUS_MSK; | 1022 | CSR_GP_REG_POWER_SAVE_STATUS_MSK; |
1023 | 1023 | ||
1024 | pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: "); | 1024 | pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: "); |
diff --git a/drivers/net/wireless/iwlegacy/iwl-eeprom.c b/drivers/net/wireless/iwlegacy/iwl-eeprom.c index 5f0fd2afedfe..26cf50699efc 100644 --- a/drivers/net/wireless/iwlegacy/iwl-eeprom.c +++ b/drivers/net/wireless/iwlegacy/iwl-eeprom.c | |||
@@ -144,7 +144,7 @@ static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */ | |||
144 | 144 | ||
145 | static int il_eeprom_verify_signature(struct il_priv *il) | 145 | static int il_eeprom_verify_signature(struct il_priv *il) |
146 | { | 146 | { |
147 | u32 gp = il_read32(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; | 147 | u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; |
148 | int ret = 0; | 148 | int ret = 0; |
149 | 149 | ||
150 | D_EEPROM("EEPROM signature=0x%08x\n", gp); | 150 | D_EEPROM("EEPROM signature=0x%08x\n", gp); |
@@ -187,7 +187,7 @@ EXPORT_SYMBOL(il_eeprom_query16); | |||
187 | int il_eeprom_init(struct il_priv *il) | 187 | int il_eeprom_init(struct il_priv *il) |
188 | { | 188 | { |
189 | __le16 *e; | 189 | __le16 *e; |
190 | u32 gp = il_read32(il, CSR_EEPROM_GP); | 190 | u32 gp = _il_rd(il, CSR_EEPROM_GP); |
191 | int sz; | 191 | int sz; |
192 | int ret; | 192 | int ret; |
193 | u16 addr; | 193 | u16 addr; |
@@ -223,7 +223,7 @@ int il_eeprom_init(struct il_priv *il) | |||
223 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | 223 | for (addr = 0; addr < sz; addr += sizeof(u16)) { |
224 | u32 r; | 224 | u32 r; |
225 | 225 | ||
226 | _il_write32(il, CSR_EEPROM_REG, | 226 | _il_wr(il, CSR_EEPROM_REG, |
227 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); | 227 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); |
228 | 228 | ||
229 | ret = il_poll_bit(il, CSR_EEPROM_REG, | 229 | ret = il_poll_bit(il, CSR_EEPROM_REG, |
diff --git a/drivers/net/wireless/iwlegacy/iwl-helpers.h b/drivers/net/wireless/iwlegacy/iwl-helpers.h index a0a84b295253..a9d87023e69f 100644 --- a/drivers/net/wireless/iwlegacy/iwl-helpers.h +++ b/drivers/net/wireless/iwlegacy/iwl-helpers.h | |||
@@ -149,26 +149,26 @@ static inline void il_disable_interrupts(struct il_priv *il) | |||
149 | clear_bit(STATUS_INT_ENABLED, &il->status); | 149 | clear_bit(STATUS_INT_ENABLED, &il->status); |
150 | 150 | ||
151 | /* disable interrupts from uCode/NIC to host */ | 151 | /* disable interrupts from uCode/NIC to host */ |
152 | il_write32(il, CSR_INT_MASK, 0x00000000); | 152 | _il_wr(il, CSR_INT_MASK, 0x00000000); |
153 | 153 | ||
154 | /* acknowledge/clear/reset any interrupts still pending | 154 | /* acknowledge/clear/reset any interrupts still pending |
155 | * from uCode or flow handler (Rx/Tx DMA) */ | 155 | * from uCode or flow handler (Rx/Tx DMA) */ |
156 | il_write32(il, CSR_INT, 0xffffffff); | 156 | _il_wr(il, CSR_INT, 0xffffffff); |
157 | il_write32(il, CSR_FH_INT_STATUS, 0xffffffff); | 157 | _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff); |
158 | D_ISR("Disabled interrupts\n"); | 158 | D_ISR("Disabled interrupts\n"); |
159 | } | 159 | } |
160 | 160 | ||
161 | static inline void il_enable_rfkill_int(struct il_priv *il) | 161 | static inline void il_enable_rfkill_int(struct il_priv *il) |
162 | { | 162 | { |
163 | D_ISR("Enabling rfkill interrupt\n"); | 163 | D_ISR("Enabling rfkill interrupt\n"); |
164 | il_write32(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); | 164 | _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); |
165 | } | 165 | } |
166 | 166 | ||
167 | static inline void il_enable_interrupts(struct il_priv *il) | 167 | static inline void il_enable_interrupts(struct il_priv *il) |
168 | { | 168 | { |
169 | D_ISR("Enabling interrupts\n"); | 169 | D_ISR("Enabling interrupts\n"); |
170 | set_bit(STATUS_INT_ENABLED, &il->status); | 170 | set_bit(STATUS_INT_ENABLED, &il->status); |
171 | il_write32(il, CSR_INT_MASK, il->inta_mask); | 171 | _il_wr(il, CSR_INT_MASK, il->inta_mask); |
172 | } | 172 | } |
173 | 173 | ||
174 | /** | 174 | /** |
diff --git a/drivers/net/wireless/iwlegacy/iwl-io.h b/drivers/net/wireless/iwlegacy/iwl-io.h index 1afd5c04d538..cdbcfde20123 100644 --- a/drivers/net/wireless/iwlegacy/iwl-io.h +++ b/drivers/net/wireless/iwlegacy/iwl-io.h | |||
@@ -40,18 +40,15 @@ static inline void _il_write8(struct il_priv *il, u32 ofs, u8 val) | |||
40 | } | 40 | } |
41 | #define il_write8(il, ofs, val) _il_write8(il, ofs, val) | 41 | #define il_write8(il, ofs, val) _il_write8(il, ofs, val) |
42 | 42 | ||
43 | static inline void _il_write32(struct il_priv *il, u32 ofs, u32 val) | 43 | static inline void _il_wr(struct il_priv *il, u32 ofs, u32 val) |
44 | { | 44 | { |
45 | iowrite32(val, il->hw_base + ofs); | 45 | iowrite32(val, il->hw_base + ofs); |
46 | } | 46 | } |
47 | #define il_write32(il, ofs, val) _il_write32(il, ofs, val) | ||
48 | 47 | ||
49 | static inline u32 _il_read32(struct il_priv *il, u32 ofs) | 48 | static inline u32 _il_rd(struct il_priv *il, u32 ofs) |
50 | { | 49 | { |
51 | u32 val = ioread32(il->hw_base + ofs); | 50 | return ioread32(il->hw_base + ofs); |
52 | return val; | ||
53 | } | 51 | } |
54 | #define il_read32(p, o) _il_read32(p, o) | ||
55 | 52 | ||
56 | #define IL_POLL_INTERVAL 10 /* microseconds */ | 53 | #define IL_POLL_INTERVAL 10 /* microseconds */ |
57 | static inline int | 54 | static inline int |
@@ -61,7 +58,7 @@ _il_poll_bit(struct il_priv *il, u32 addr, | |||
61 | int t = 0; | 58 | int t = 0; |
62 | 59 | ||
63 | do { | 60 | do { |
64 | if ((_il_read32(il, addr) & mask) == (bits & mask)) | 61 | if ((_il_rd(il, addr) & mask) == (bits & mask)) |
65 | return t; | 62 | return t; |
66 | udelay(IL_POLL_INTERVAL); | 63 | udelay(IL_POLL_INTERVAL); |
67 | t += IL_POLL_INTERVAL; | 64 | t += IL_POLL_INTERVAL; |
@@ -73,7 +70,7 @@ _il_poll_bit(struct il_priv *il, u32 addr, | |||
73 | 70 | ||
74 | static inline void _il_set_bit(struct il_priv *il, u32 reg, u32 mask) | 71 | static inline void _il_set_bit(struct il_priv *il, u32 reg, u32 mask) |
75 | { | 72 | { |
76 | _il_write32(il, reg, _il_read32(il, reg) | mask); | 73 | _il_wr(il, reg, _il_rd(il, reg) | mask); |
77 | } | 74 | } |
78 | 75 | ||
79 | static inline void il_set_bit(struct il_priv *p, u32 r, u32 m) | 76 | static inline void il_set_bit(struct il_priv *p, u32 r, u32 m) |
@@ -88,7 +85,7 @@ static inline void il_set_bit(struct il_priv *p, u32 r, u32 m) | |||
88 | static inline void | 85 | static inline void |
89 | _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) | 86 | _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) |
90 | { | 87 | { |
91 | _il_write32(il, reg, _il_read32(il, reg) & ~mask); | 88 | _il_wr(il, reg, _il_rd(il, reg) & ~mask); |
92 | } | 89 | } |
93 | 90 | ||
94 | static inline void il_clear_bit(struct il_priv *p, u32 r, u32 m) | 91 | static inline void il_clear_bit(struct il_priv *p, u32 r, u32 m) |
@@ -131,10 +128,10 @@ static inline int _il_grab_nic_access(struct il_priv *il) | |||
131 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | 128 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | |
132 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | 129 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); |
133 | if (ret < 0) { | 130 | if (ret < 0) { |
134 | val = _il_read32(il, CSR_GP_CNTRL); | 131 | val = _il_rd(il, CSR_GP_CNTRL); |
135 | IL_ERR( | 132 | IL_ERR( |
136 | "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); | 133 | "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); |
137 | _il_write32(il, CSR_RESET, | 134 | _il_wr(il, CSR_RESET, |
138 | CSR_RESET_REG_FLAG_FORCE_NMI); | 135 | CSR_RESET_REG_FLAG_FORCE_NMI); |
139 | return -EIO; | 136 | return -EIO; |
140 | } | 137 | } |
@@ -152,7 +149,7 @@ static inline void _il_release_nic_access(struct il_priv *il) | |||
152 | 149 | ||
153 | static inline u32 _il_read_direct32(struct il_priv *il, u32 reg) | 150 | static inline u32 _il_read_direct32(struct il_priv *il, u32 reg) |
154 | { | 151 | { |
155 | return _il_read32(il, reg); | 152 | return _il_rd(il, reg); |
156 | } | 153 | } |
157 | 154 | ||
158 | static inline u32 il_read_direct32(struct il_priv *il, u32 reg) | 155 | static inline u32 il_read_direct32(struct il_priv *il, u32 reg) |
@@ -172,7 +169,7 @@ static inline u32 il_read_direct32(struct il_priv *il, u32 reg) | |||
172 | static inline void _il_write_direct32(struct il_priv *il, | 169 | static inline void _il_write_direct32(struct il_priv *il, |
173 | u32 reg, u32 value) | 170 | u32 reg, u32 value) |
174 | { | 171 | { |
175 | _il_write32(il, reg, value); | 172 | _il_wr(il, reg, value); |
176 | } | 173 | } |
177 | static inline void | 174 | static inline void |
178 | il_write_direct32(struct il_priv *il, u32 reg, u32 value) | 175 | il_write_direct32(struct il_priv *il, u32 reg, u32 value) |
diff --git a/drivers/net/wireless/iwlegacy/iwl-rx.c b/drivers/net/wireless/iwlegacy/iwl-rx.c index 183acdc69a25..e481ca8c0cc9 100644 --- a/drivers/net/wireless/iwlegacy/iwl-rx.c +++ b/drivers/net/wireless/iwlegacy/iwl-rx.c | |||
@@ -138,7 +138,7 @@ il_rx_queue_update_write_ptr(struct il_priv *il, | |||
138 | 138 | ||
139 | /* If power-saving is in use, make sure device is awake */ | 139 | /* If power-saving is in use, make sure device is awake */ |
140 | if (test_bit(STATUS_POWER_PMI, &il->status)) { | 140 | if (test_bit(STATUS_POWER_PMI, &il->status)) { |
141 | reg = il_read32(il, CSR_UCODE_DRV_GP1); | 141 | reg = _il_rd(il, CSR_UCODE_DRV_GP1); |
142 | 142 | ||
143 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | 143 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
144 | D_INFO( | 144 | D_INFO( |
diff --git a/drivers/net/wireless/iwlegacy/iwl-tx.c b/drivers/net/wireless/iwlegacy/iwl-tx.c index cfc015ae203b..6b5e652c4fc3 100644 --- a/drivers/net/wireless/iwlegacy/iwl-tx.c +++ b/drivers/net/wireless/iwlegacy/iwl-tx.c | |||
@@ -55,7 +55,7 @@ il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq) | |||
55 | /* wake up nic if it's powered down ... | 55 | /* wake up nic if it's powered down ... |
56 | * uCode will wake up, and interrupt us again, so next | 56 | * uCode will wake up, and interrupt us again, so next |
57 | * time we'll skip this part. */ | 57 | * time we'll skip this part. */ |
58 | reg = il_read32(il, CSR_UCODE_DRV_GP1); | 58 | reg = _il_rd(il, CSR_UCODE_DRV_GP1); |
59 | 59 | ||
60 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | 60 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
61 | D_INFO( | 61 | D_INFO( |
@@ -75,7 +75,7 @@ il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq) | |||
75 | * trying to tx (during RFKILL, we're not trying to tx). | 75 | * trying to tx (during RFKILL, we're not trying to tx). |
76 | */ | 76 | */ |
77 | } else | 77 | } else |
78 | il_write32(il, HBUS_TARG_WRPTR, | 78 | _il_wr(il, HBUS_TARG_WRPTR, |
79 | txq->q.write_ptr | (txq_id << 8)); | 79 | txq->q.write_ptr | (txq_id << 8)); |
80 | txq->need_update = 0; | 80 | txq->need_update = 0; |
81 | } | 81 | } |
diff --git a/drivers/net/wireless/iwlegacy/iwl3945-base.c b/drivers/net/wireless/iwlegacy/iwl3945-base.c index 66aa8505f4fe..def314073ce8 100644 --- a/drivers/net/wireless/iwlegacy/iwl3945-base.c +++ b/drivers/net/wireless/iwlegacy/iwl3945-base.c | |||
@@ -824,7 +824,7 @@ static void il3945_rx_card_state_notif(struct il_priv *il, | |||
824 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | 824 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
825 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | 825 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); |
826 | 826 | ||
827 | il_write32(il, CSR_UCODE_DRV_GP1_SET, | 827 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
828 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 828 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
829 | 829 | ||
830 | if (flags & HW_CARD_DISABLED) | 830 | if (flags & HW_CARD_DISABLED) |
@@ -1419,19 +1419,19 @@ static void il3945_irq_tasklet(struct il_priv *il) | |||
1419 | /* Ack/clear/reset pending uCode interrupts. | 1419 | /* Ack/clear/reset pending uCode interrupts. |
1420 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | 1420 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, |
1421 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | 1421 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ |
1422 | inta = il_read32(il, CSR_INT); | 1422 | inta = _il_rd(il, CSR_INT); |
1423 | il_write32(il, CSR_INT, inta); | 1423 | _il_wr(il, CSR_INT, inta); |
1424 | 1424 | ||
1425 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | 1425 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. |
1426 | * Any new interrupts that happen after this, either while we're | 1426 | * Any new interrupts that happen after this, either while we're |
1427 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | 1427 | * in this tasklet, or later, will show up in next ISR/tasklet. */ |
1428 | inta_fh = il_read32(il, CSR_FH_INT_STATUS); | 1428 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
1429 | il_write32(il, CSR_FH_INT_STATUS, inta_fh); | 1429 | _il_wr(il, CSR_FH_INT_STATUS, inta_fh); |
1430 | 1430 | ||
1431 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG | 1431 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
1432 | if (il_get_debug_level(il) & IL_DL_ISR) { | 1432 | if (il_get_debug_level(il) & IL_DL_ISR) { |
1433 | /* just for debug */ | 1433 | /* just for debug */ |
1434 | inta_mask = il_read32(il, CSR_INT_MASK); | 1434 | inta_mask = _il_rd(il, CSR_INT_MASK); |
1435 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | 1435 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
1436 | inta, inta_mask, inta_fh); | 1436 | inta, inta_mask, inta_fh); |
1437 | } | 1437 | } |
@@ -1519,7 +1519,7 @@ static void il3945_irq_tasklet(struct il_priv *il) | |||
1519 | D_ISR("Tx interrupt\n"); | 1519 | D_ISR("Tx interrupt\n"); |
1520 | il->isr_stats.tx++; | 1520 | il->isr_stats.tx++; |
1521 | 1521 | ||
1522 | il_write32(il, CSR_FH_INT_STATUS, (1 << 6)); | 1522 | _il_wr(il, CSR_FH_INT_STATUS, (1 << 6)); |
1523 | il_write_direct32(il, FH39_TCSR_CREDIT | 1523 | il_write_direct32(il, FH39_TCSR_CREDIT |
1524 | (FH39_SRVC_CHNL), 0x0); | 1524 | (FH39_SRVC_CHNL), 0x0); |
1525 | handled |= CSR_INT_BIT_FH_TX; | 1525 | handled |= CSR_INT_BIT_FH_TX; |
@@ -1543,9 +1543,9 @@ static void il3945_irq_tasklet(struct il_priv *il) | |||
1543 | 1543 | ||
1544 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG | 1544 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
1545 | if (il_get_debug_level(il) & (IL_DL_ISR)) { | 1545 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
1546 | inta = il_read32(il, CSR_INT); | 1546 | inta = _il_rd(il, CSR_INT); |
1547 | inta_mask = il_read32(il, CSR_INT_MASK); | 1547 | inta_mask = _il_rd(il, CSR_INT_MASK); |
1548 | inta_fh = il_read32(il, CSR_FH_INT_STATUS); | 1548 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
1549 | D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " | 1549 | D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
1550 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | 1550 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1551 | } | 1551 | } |
@@ -1817,7 +1817,7 @@ static int il3945_verify_ucode(struct il_priv *il) | |||
1817 | static void il3945_nic_start(struct il_priv *il) | 1817 | static void il3945_nic_start(struct il_priv *il) |
1818 | { | 1818 | { |
1819 | /* Remove all resets to allow NIC to operate */ | 1819 | /* Remove all resets to allow NIC to operate */ |
1820 | il_write32(il, CSR_RESET, 0); | 1820 | _il_wr(il, CSR_RESET, 0); |
1821 | } | 1821 | } |
1822 | 1822 | ||
1823 | #define IWL3945_UCODE_GET(item) \ | 1823 | #define IWL3945_UCODE_GET(item) \ |
@@ -2304,7 +2304,7 @@ static void __il3945_down(struct il_priv *il) | |||
2304 | clear_bit(STATUS_EXIT_PENDING, &il->status); | 2304 | clear_bit(STATUS_EXIT_PENDING, &il->status); |
2305 | 2305 | ||
2306 | /* stop and reset the on-board processor */ | 2306 | /* stop and reset the on-board processor */ |
2307 | il_write32(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | 2307 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
2308 | 2308 | ||
2309 | /* tell the device to stop sending interrupts */ | 2309 | /* tell the device to stop sending interrupts */ |
2310 | spin_lock_irqsave(&il->lock, flags); | 2310 | spin_lock_irqsave(&il->lock, flags); |
@@ -2412,7 +2412,7 @@ static int __il3945_up(struct il_priv *il) | |||
2412 | } | 2412 | } |
2413 | 2413 | ||
2414 | /* If platform's RF_KILL switch is NOT set to KILL */ | 2414 | /* If platform's RF_KILL switch is NOT set to KILL */ |
2415 | if (il_read32(il, CSR_GP_CNTRL) & | 2415 | if (_il_rd(il, CSR_GP_CNTRL) & |
2416 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | 2416 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2417 | clear_bit(STATUS_RF_KILL_HW, &il->status); | 2417 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
2418 | else { | 2418 | else { |
@@ -2421,7 +2421,7 @@ static int __il3945_up(struct il_priv *il) | |||
2421 | return -ENODEV; | 2421 | return -ENODEV; |
2422 | } | 2422 | } |
2423 | 2423 | ||
2424 | il_write32(il, CSR_INT, 0xFFFFFFFF); | 2424 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
2425 | 2425 | ||
2426 | rc = il3945_hw_nic_init(il); | 2426 | rc = il3945_hw_nic_init(il); |
2427 | if (rc) { | 2427 | if (rc) { |
@@ -2430,17 +2430,17 @@ static int __il3945_up(struct il_priv *il) | |||
2430 | } | 2430 | } |
2431 | 2431 | ||
2432 | /* make sure rfkill handshake bits are cleared */ | 2432 | /* make sure rfkill handshake bits are cleared */ |
2433 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2433 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2434 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, | 2434 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
2435 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 2435 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2436 | 2436 | ||
2437 | /* clear (again), then enable host interrupts */ | 2437 | /* clear (again), then enable host interrupts */ |
2438 | il_write32(il, CSR_INT, 0xFFFFFFFF); | 2438 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
2439 | il_enable_interrupts(il); | 2439 | il_enable_interrupts(il); |
2440 | 2440 | ||
2441 | /* really make sure rfkill handshake bits are cleared */ | 2441 | /* really make sure rfkill handshake bits are cleared */ |
2442 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2442 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2443 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2443 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2444 | 2444 | ||
2445 | /* Copy original ucode data image from disk into backup cache. | 2445 | /* Copy original ucode data image from disk into backup cache. |
2446 | * This will be used to initialize the on-board processor's | 2446 | * This will be used to initialize the on-board processor's |
@@ -2529,7 +2529,7 @@ static void il3945_rfkill_poll(struct work_struct *data) | |||
2529 | struct il_priv *il = | 2529 | struct il_priv *il = |
2530 | container_of(data, struct il_priv, _3945.rfkill_poll.work); | 2530 | container_of(data, struct il_priv, _3945.rfkill_poll.work); |
2531 | bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &il->status); | 2531 | bool old_rfkill = test_bit(STATUS_RF_KILL_HW, &il->status); |
2532 | bool new_rfkill = !(il_read32(il, CSR_GP_CNTRL) | 2532 | bool new_rfkill = !(_il_rd(il, CSR_GP_CNTRL) |
2533 | & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); | 2533 | & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); |
2534 | 2534 | ||
2535 | if (new_rfkill != old_rfkill) { | 2535 | if (new_rfkill != old_rfkill) { |
@@ -3748,7 +3748,7 @@ static int il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *en | |||
3748 | * strange state ... like being left stranded by a primary kernel | 3748 | * strange state ... like being left stranded by a primary kernel |
3749 | * and this is now the kdump kernel trying to start up | 3749 | * and this is now the kdump kernel trying to start up |
3750 | */ | 3750 | */ |
3751 | il_write32(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | 3751 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
3752 | 3752 | ||
3753 | /*********************** | 3753 | /*********************** |
3754 | * 4. Read EEPROM | 3754 | * 4. Read EEPROM |
diff --git a/drivers/net/wireless/iwlegacy/iwl4965-base.c b/drivers/net/wireless/iwlegacy/iwl4965-base.c index df7e0a484dfe..a7743732a6b6 100644 --- a/drivers/net/wireless/iwlegacy/iwl4965-base.c +++ b/drivers/net/wireless/iwlegacy/iwl4965-base.c | |||
@@ -517,9 +517,9 @@ static void il4965_perform_ct_kill_task(struct il_priv *il) | |||
517 | if (il->mac80211_registered) | 517 | if (il->mac80211_registered) |
518 | ieee80211_stop_queues(il->hw); | 518 | ieee80211_stop_queues(il->hw); |
519 | 519 | ||
520 | il_write32(il, CSR_UCODE_DRV_GP1_SET, | 520 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
521 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | 521 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
522 | il_read32(il, CSR_UCODE_DRV_GP1); | 522 | _il_rd(il, CSR_UCODE_DRV_GP1); |
523 | 523 | ||
524 | spin_lock_irqsave(&il->reg_lock, flags); | 524 | spin_lock_irqsave(&il->reg_lock, flags); |
525 | if (!il_grab_nic_access(il)) | 525 | if (!il_grab_nic_access(il)) |
@@ -545,14 +545,14 @@ static void il4965_rx_card_state_notif(struct il_priv *il, | |||
545 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | 545 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | |
546 | CT_CARD_DISABLED)) { | 546 | CT_CARD_DISABLED)) { |
547 | 547 | ||
548 | il_write32(il, CSR_UCODE_DRV_GP1_SET, | 548 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
549 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 549 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
550 | 550 | ||
551 | il_write_direct32(il, HBUS_TARG_MBX_C, | 551 | il_write_direct32(il, HBUS_TARG_MBX_C, |
552 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | 552 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
553 | 553 | ||
554 | if (!(flags & RXON_CARD_DISABLED)) { | 554 | if (!(flags & RXON_CARD_DISABLED)) { |
555 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, | 555 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
556 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 556 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
557 | il_write_direct32(il, HBUS_TARG_MBX_C, | 557 | il_write_direct32(il, HBUS_TARG_MBX_C, |
558 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | 558 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
@@ -787,19 +787,19 @@ static void il4965_irq_tasklet(struct il_priv *il) | |||
787 | /* Ack/clear/reset pending uCode interrupts. | 787 | /* Ack/clear/reset pending uCode interrupts. |
788 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | 788 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, |
789 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | 789 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ |
790 | inta = il_read32(il, CSR_INT); | 790 | inta = _il_rd(il, CSR_INT); |
791 | il_write32(il, CSR_INT, inta); | 791 | _il_wr(il, CSR_INT, inta); |
792 | 792 | ||
793 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | 793 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. |
794 | * Any new interrupts that happen after this, either while we're | 794 | * Any new interrupts that happen after this, either while we're |
795 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | 795 | * in this tasklet, or later, will show up in next ISR/tasklet. */ |
796 | inta_fh = il_read32(il, CSR_FH_INT_STATUS); | 796 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
797 | il_write32(il, CSR_FH_INT_STATUS, inta_fh); | 797 | _il_wr(il, CSR_FH_INT_STATUS, inta_fh); |
798 | 798 | ||
799 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG | 799 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
800 | if (il_get_debug_level(il) & IL_DL_ISR) { | 800 | if (il_get_debug_level(il) & IL_DL_ISR) { |
801 | /* just for debug */ | 801 | /* just for debug */ |
802 | inta_mask = il_read32(il, CSR_INT_MASK); | 802 | inta_mask = _il_rd(il, CSR_INT_MASK); |
803 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", | 803 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
804 | inta, inta_mask, inta_fh); | 804 | inta, inta_mask, inta_fh); |
805 | } | 805 | } |
@@ -853,7 +853,7 @@ static void il4965_irq_tasklet(struct il_priv *il) | |||
853 | /* HW RF KILL switch toggled */ | 853 | /* HW RF KILL switch toggled */ |
854 | if (inta & CSR_INT_BIT_RF_KILL) { | 854 | if (inta & CSR_INT_BIT_RF_KILL) { |
855 | int hw_rf_kill = 0; | 855 | int hw_rf_kill = 0; |
856 | if (!(il_read32(il, CSR_GP_CNTRL) & | 856 | if (!(_il_rd(il, CSR_GP_CNTRL) & |
857 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | 857 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
858 | hw_rf_kill = 1; | 858 | hw_rf_kill = 1; |
859 | 859 | ||
@@ -948,9 +948,9 @@ static void il4965_irq_tasklet(struct il_priv *il) | |||
948 | 948 | ||
949 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG | 949 | #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG |
950 | if (il_get_debug_level(il) & (IL_DL_ISR)) { | 950 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
951 | inta = il_read32(il, CSR_INT); | 951 | inta = _il_rd(il, CSR_INT); |
952 | inta_mask = il_read32(il, CSR_INT_MASK); | 952 | inta_mask = _il_rd(il, CSR_INT_MASK); |
953 | inta_fh = il_read32(il, CSR_FH_INT_STATUS); | 953 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
954 | D_ISR( | 954 | D_ISR( |
955 | "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " | 955 | "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
956 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | 956 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
@@ -1092,7 +1092,7 @@ static void il4965_dealloc_ucode_pci(struct il_priv *il) | |||
1092 | static void il4965_nic_start(struct il_priv *il) | 1092 | static void il4965_nic_start(struct il_priv *il) |
1093 | { | 1093 | { |
1094 | /* Remove all resets to allow NIC to operate */ | 1094 | /* Remove all resets to allow NIC to operate */ |
1095 | il_write32(il, CSR_RESET, 0); | 1095 | _il_wr(il, CSR_RESET, 0); |
1096 | } | 1096 | } |
1097 | 1097 | ||
1098 | static void il4965_ucode_callback(const struct firmware *ucode_raw, | 1098 | static void il4965_ucode_callback(const struct firmware *ucode_raw, |
@@ -1584,7 +1584,7 @@ static void il4965_rf_kill_ct_config(struct il_priv *il) | |||
1584 | int ret = 0; | 1584 | int ret = 0; |
1585 | 1585 | ||
1586 | spin_lock_irqsave(&il->lock, flags); | 1586 | spin_lock_irqsave(&il->lock, flags); |
1587 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, | 1587 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
1588 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | 1588 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
1589 | spin_unlock_irqrestore(&il->lock, flags); | 1589 | spin_unlock_irqrestore(&il->lock, flags); |
1590 | 1590 | ||
@@ -1830,7 +1830,7 @@ static void __il4965_down(struct il_priv *il) | |||
1830 | clear_bit(STATUS_EXIT_PENDING, &il->status); | 1830 | clear_bit(STATUS_EXIT_PENDING, &il->status); |
1831 | 1831 | ||
1832 | /* stop and reset the on-board processor */ | 1832 | /* stop and reset the on-board processor */ |
1833 | il_write32(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | 1833 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
1834 | 1834 | ||
1835 | /* tell the device to stop sending interrupts */ | 1835 | /* tell the device to stop sending interrupts */ |
1836 | spin_lock_irqsave(&il->lock, flags); | 1836 | spin_lock_irqsave(&il->lock, flags); |
@@ -1980,7 +1980,7 @@ static int __il4965_up(struct il_priv *il) | |||
1980 | } | 1980 | } |
1981 | 1981 | ||
1982 | /* If platform's RF_KILL switch is NOT set to KILL */ | 1982 | /* If platform's RF_KILL switch is NOT set to KILL */ |
1983 | if (il_read32(il, | 1983 | if (_il_rd(il, |
1984 | CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | 1984 | CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
1985 | clear_bit(STATUS_RF_KILL_HW, &il->status); | 1985 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
1986 | else | 1986 | else |
@@ -1994,7 +1994,7 @@ static int __il4965_up(struct il_priv *il) | |||
1994 | return 0; | 1994 | return 0; |
1995 | } | 1995 | } |
1996 | 1996 | ||
1997 | il_write32(il, CSR_INT, 0xFFFFFFFF); | 1997 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
1998 | 1998 | ||
1999 | /* must be initialised before il_hw_nic_init */ | 1999 | /* must be initialised before il_hw_nic_init */ |
2000 | il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; | 2000 | il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; |
@@ -2006,17 +2006,17 @@ static int __il4965_up(struct il_priv *il) | |||
2006 | } | 2006 | } |
2007 | 2007 | ||
2008 | /* make sure rfkill handshake bits are cleared */ | 2008 | /* make sure rfkill handshake bits are cleared */ |
2009 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2009 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2010 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, | 2010 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
2011 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 2011 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2012 | 2012 | ||
2013 | /* clear (again), then enable host interrupts */ | 2013 | /* clear (again), then enable host interrupts */ |
2014 | il_write32(il, CSR_INT, 0xFFFFFFFF); | 2014 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
2015 | il_enable_interrupts(il); | 2015 | il_enable_interrupts(il); |
2016 | 2016 | ||
2017 | /* really make sure rfkill handshake bits are cleared */ | 2017 | /* really make sure rfkill handshake bits are cleared */ |
2018 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2018 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2019 | il_write32(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | 2019 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2020 | 2020 | ||
2021 | /* Copy original ucode data image from disk into backup cache. | 2021 | /* Copy original ucode data image from disk into backup cache. |
2022 | * This will be used to initialize the on-board processor's | 2022 | * This will be used to initialize the on-board processor's |
@@ -2296,7 +2296,7 @@ void il4965_mac_stop(struct ieee80211_hw *hw) | |||
2296 | 2296 | ||
2297 | /* User space software may expect getting rfkill changes | 2297 | /* User space software may expect getting rfkill changes |
2298 | * even if interface is down */ | 2298 | * even if interface is down */ |
2299 | il_write32(il, CSR_INT, 0xFFFFFFFF); | 2299 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
2300 | il_enable_rfkill_int(il); | 2300 | il_enable_rfkill_int(il); |
2301 | 2301 | ||
2302 | D_MAC80211("leave\n"); | 2302 | D_MAC80211("leave\n"); |
@@ -2821,8 +2821,8 @@ static void il4965_uninit_drv(struct il_priv *il) | |||
2821 | 2821 | ||
2822 | static void il4965_hw_detect(struct il_priv *il) | 2822 | static void il4965_hw_detect(struct il_priv *il) |
2823 | { | 2823 | { |
2824 | il->hw_rev = _il_read32(il, CSR_HW_REV); | 2824 | il->hw_rev = _il_rd(il, CSR_HW_REV); |
2825 | il->hw_wa_rev = _il_read32(il, CSR_HW_REV_WA_REG); | 2825 | il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG); |
2826 | il->rev_id = il->pci_dev->revision; | 2826 | il->rev_id = il->pci_dev->revision; |
2827 | D_INFO("HW Revision ID = 0x%X\n", il->rev_id); | 2827 | D_INFO("HW Revision ID = 0x%X\n", il->rev_id); |
2828 | } | 2828 | } |
@@ -2978,7 +2978,7 @@ il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2978 | * strange state ... like being left stranded by a primary kernel | 2978 | * strange state ... like being left stranded by a primary kernel |
2979 | * and this is now the kdump kernel trying to start up | 2979 | * and this is now the kdump kernel trying to start up |
2980 | */ | 2980 | */ |
2981 | il_write32(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | 2981 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
2982 | 2982 | ||
2983 | il4965_hw_detect(il); | 2983 | il4965_hw_detect(il); |
2984 | IL_INFO("Detected %s, REV=0x%X\n", | 2984 | IL_INFO("Detected %s, REV=0x%X\n", |
@@ -3066,7 +3066,7 @@ il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
3066 | il_enable_rfkill_int(il); | 3066 | il_enable_rfkill_int(il); |
3067 | 3067 | ||
3068 | /* If platform's RF_KILL switch is NOT set to KILL */ | 3068 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3069 | if (il_read32(il, CSR_GP_CNTRL) & | 3069 | if (_il_rd(il, CSR_GP_CNTRL) & |
3070 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | 3070 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
3071 | clear_bit(STATUS_RF_KILL_HW, &il->status); | 3071 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
3072 | else | 3072 | else |