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authorRafał Miłecki <zajec5@gmail.com>2012-07-25 18:07:39 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-08-06 14:56:35 -0400
commit572d37a48557e7d38a5d9b5857627bc29f33a26c (patch)
tree71580baeab86dab90d398458c0ba6cba5c4e9db2 /drivers/net/wireless/b43
parentd3d178f050813ec6b82b77cc2df668272e10daba (diff)
b43: N-PHY: init 0x2057 radio
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r--drivers/net/wireless/b43/Makefile1
-rw-r--r--drivers/net/wireless/b43/phy_n.c142
-rw-r--r--drivers/net/wireless/b43/radio_2057.c141
-rw-r--r--drivers/net/wireless/b43/radio_2057.h430
4 files changed, 712 insertions, 2 deletions
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 4648bbf76abc..098fe9ee7096 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -4,6 +4,7 @@ b43-y += tables.o
4b43-$(CONFIG_B43_PHY_N) += tables_nphy.o 4b43-$(CONFIG_B43_PHY_N) += tables_nphy.o
5b43-$(CONFIG_B43_PHY_N) += radio_2055.o 5b43-$(CONFIG_B43_PHY_N) += radio_2055.o
6b43-$(CONFIG_B43_PHY_N) += radio_2056.o 6b43-$(CONFIG_B43_PHY_N) += radio_2056.o
7b43-$(CONFIG_B43_PHY_N) += radio_2057.o
7b43-y += phy_common.o 8b43-y += phy_common.o
8b43-y += phy_g.o 9b43-y += phy_g.o
9b43-y += phy_a.o 10b43-y += phy_a.o
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 0e75c3567f5d..113d5ca6623b 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -32,6 +32,7 @@
32#include "tables_nphy.h" 32#include "tables_nphy.h"
33#include "radio_2055.h" 33#include "radio_2055.h"
34#include "radio_2056.h" 34#include "radio_2056.h"
35#include "radio_2057.h"
35#include "main.h" 36#include "main.h"
36 37
37struct nphy_txgains { 38struct nphy_txgains {
@@ -459,6 +460,136 @@ static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
459} 460}
460 461
461/************************************************** 462/**************************************************
463 * Radio 0x2057
464 **************************************************/
465
466/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
467static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
468{
469 struct b43_phy *phy = &dev->phy;
470 u16 tmp;
471
472 if (phy->radio_rev == 5) {
473 b43_phy_mask(dev, 0x342, ~0x2);
474 udelay(10);
475 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
476 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
477 }
478
479 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
480 udelay(10);
481 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
482 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
483 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
484 return 0;
485 }
486 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
487 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
488 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
489
490 if (phy->radio_rev == 5) {
491 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
492 b43_radio_mask(dev, 0x1ca, ~0x2);
493 }
494 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
495 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
496 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
497 tmp << 2);
498 }
499
500 return tmp & 0x3e;
501}
502
503/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
504static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
505{
506 struct b43_phy *phy = &dev->phy;
507 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
508 phy->radio_rev == 6);
509 u16 tmp;
510
511 if (special) {
512 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
513 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
514 } else {
515 b43_radio_write(dev, 0x1AE, 0x61);
516 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
517 }
518 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
519 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
520 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
521 5000000))
522 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
523 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
524 if (special) {
525 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
526 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
527 } else {
528 b43_radio_write(dev, 0x1AE, 0x69);
529 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
530 }
531 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
532 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
533 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
534 5000000))
535 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
536 if (special) {
537 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
538 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
539 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
540 } else {
541 b43_radio_write(dev, 0x1AE, 0x73);
542 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
543 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
544 }
545 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
546 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
547 5000000)) {
548 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
549 return 0;
550 }
551 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
552 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
553 return tmp;
554}
555
556static void b43_radio_2057_init_pre(struct b43_wldev *dev)
557{
558 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
559 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
560 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
561 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
562 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
563}
564
565static void b43_radio_2057_init_post(struct b43_wldev *dev)
566{
567 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
568
569 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
570 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
571 mdelay(2);
572 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
573 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
574
575 if (dev->phy.n->init_por) {
576 b43_radio_2057_rcal(dev);
577 b43_radio_2057_rccal(dev);
578 }
579 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
580
581 dev->phy.n->init_por = false;
582}
583
584/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
585static void b43_radio_2057_init(struct b43_wldev *dev)
586{
587 b43_radio_2057_init_pre(dev);
588 r2057_upload_inittabs(dev);
589 b43_radio_2057_init_post(dev);
590}
591
592/**************************************************
462 * Radio 0x2056 593 * Radio 0x2056
463 **************************************************/ 594 **************************************************/
464 595
@@ -5212,6 +5343,8 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
5212 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2; 5343 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5213 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2; 5344 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5214 } 5345 }
5346
5347 nphy->init_por = true;
5215} 5348}
5216 5349
5217static void b43_nphy_op_free(struct b43_wldev *dev) 5350static void b43_nphy_op_free(struct b43_wldev *dev)
@@ -5298,7 +5431,9 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5298 if (blocked) { 5431 if (blocked) {
5299 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 5432 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5300 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 5433 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
5301 if (dev->phy.rev >= 3) { 5434 if (dev->phy.rev >= 7) {
5435 /* TODO */
5436 } else if (dev->phy.rev >= 3) {
5302 b43_radio_mask(dev, 0x09, ~0x2); 5437 b43_radio_mask(dev, 0x09, ~0x2);
5303 5438
5304 b43_radio_write(dev, 0x204D, 0); 5439 b43_radio_write(dev, 0x204D, 0);
@@ -5316,7 +5451,10 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
5316 b43_radio_write(dev, 0x3064, 0); 5451 b43_radio_write(dev, 0x3064, 0);
5317 } 5452 }
5318 } else { 5453 } else {
5319 if (dev->phy.rev >= 3) { 5454 if (dev->phy.rev >= 7) {
5455 b43_radio_2057_init(dev);
5456 b43_switch_channel(dev, dev->phy.channel);
5457 } else if (dev->phy.rev >= 3) {
5320 b43_radio_init2056(dev); 5458 b43_radio_init2056(dev);
5321 b43_switch_channel(dev, dev->phy.channel); 5459 b43_switch_channel(dev, dev->phy.channel);
5322 } else { 5460 } else {
diff --git a/drivers/net/wireless/b43/radio_2057.c b/drivers/net/wireless/b43/radio_2057.c
new file mode 100644
index 000000000000..d61d6830c5c7
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2057.c
@@ -0,0 +1,141 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n 2057 radio device data tables
5
6 Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include "b43.h"
26#include "radio_2057.h"
27#include "phy_common.h"
28
29static u16 r2057_rev4_init[42][2] = {
30 { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 },
31 { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff },
32 { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 },
33 { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c },
34 { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 },
35 { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c },
36 { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
37 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
38 { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
39 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
40 { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
41};
42
43static u16 r2057_rev5_init[44][2] = {
44 { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 },
45 { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 },
46 { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f },
47 { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
48 { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 },
49 { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f },
50 { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
51 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
52 { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 },
53 { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 },
54 { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, { 0x1C2, 0x80 },
55};
56
57static u16 r2057_rev5a_init[45][2] = {
58 { 0x00, 0x15 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 },
59 { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 },
60 { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f },
61 { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
62 { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 },
63 { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f },
64 { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x14E, 0x01 }, { 0x15E, 0x00 },
65 { 0x15F, 0x00 }, { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 },
66 { 0x163, 0x00 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
67 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
68 { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 },
69 { 0x1C2, 0x80 },
70};
71
72static u16 r2057_rev7_init[54][2] = {
73 { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 },
74 { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 },
75 { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x13 },
76 { 0x66, 0xee }, { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 },
77 { 0x7C, 0x14 }, { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f },
78 { 0x92, 0x36 }, { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 },
79 { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x13 }, { 0xEB, 0xee },
80 { 0xF3, 0x58 }, { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x14 },
81 { 0x102, 0xee }, { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 },
82 { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 },
83 { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 },
84 { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 },
85 { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
86 { 0x1B7, 0x05 }, { 0x1C2, 0xa0 },
87};
88
89static u16 r2057_rev8_init[54][2] = {
90 { 0x00, 0x08 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 },
91 { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 },
92 { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x0f },
93 { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, { 0x7C, 0x0f },
94 { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 },
95 { 0xA1, 0x20 }, { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 },
96 { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0xF3, 0x58 },
97 { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x0f }, { 0x102, 0xee },
98 { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x126, 0x20 },
99 { 0x14E, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 },
100 { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 },
101 { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 },
102 { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 },
103 { 0x1B7, 0x05 }, { 0x1C2, 0xa0 },
104};
105
106void r2057_upload_inittabs(struct b43_wldev *dev)
107{
108 struct b43_phy *phy = &dev->phy;
109 u16 *table = NULL;
110 u16 size, i;
111
112 if (phy->rev == 7) {
113 table = r2057_rev4_init[0];
114 size = ARRAY_SIZE(r2057_rev4_init);
115 } else if (phy->rev == 8 || phy->rev == 9) {
116 if (phy->radio_rev == 5) {
117 if (phy->radio_rev == 8) {
118 table = r2057_rev5_init[0];
119 size = ARRAY_SIZE(r2057_rev5_init);
120 } else {
121 table = r2057_rev5a_init[0];
122 size = ARRAY_SIZE(r2057_rev5a_init);
123 }
124 } else if (phy->radio_rev == 7) {
125 table = r2057_rev7_init[0];
126 size = ARRAY_SIZE(r2057_rev7_init);
127 } else if (phy->radio_rev == 9) {
128 table = r2057_rev8_init[0];
129 size = ARRAY_SIZE(r2057_rev8_init);
130 }
131 }
132
133 if (table) {
134 for (i = 0; i < 10; i++) {
135 pr_info("radio_write 0x%X ", *table);
136 table++;
137 pr_info("0x%X\n", *table);
138 table++;
139 }
140 }
141}
diff --git a/drivers/net/wireless/b43/radio_2057.h b/drivers/net/wireless/b43/radio_2057.h
new file mode 100644
index 000000000000..eeebd8fbeb0d
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2057.h
@@ -0,0 +1,430 @@
1#ifndef B43_RADIO_2057_H_
2#define B43_RADIO_2057_H_
3
4#include <linux/types.h>
5
6#include "tables_nphy.h"
7
8#define R2057_DACBUF_VINCM_CORE0 0x000
9#define R2057_IDCODE 0x001
10#define R2057_RCCAL_MASTER 0x002
11#define R2057_RCCAL_CAP_SIZE 0x003
12#define R2057_RCAL_CONFIG 0x004
13#define R2057_GPAIO_CONFIG 0x005
14#define R2057_GPAIO_SEL1 0x006
15#define R2057_GPAIO_SEL0 0x007
16#define R2057_CLPO_CONFIG 0x008
17#define R2057_BANDGAP_CONFIG 0x009
18#define R2057_BANDGAP_RCAL_TRIM 0x00a
19#define R2057_AFEREG_CONFIG 0x00b
20#define R2057_TEMPSENSE_CONFIG 0x00c
21#define R2057_XTAL_CONFIG1 0x00d
22#define R2057_XTAL_ICORE_SIZE 0x00e
23#define R2057_XTAL_BUF_SIZE 0x00f
24#define R2057_XTAL_PULLCAP_SIZE 0x010
25#define R2057_RFPLL_MASTER 0x011
26#define R2057_VCOMONITOR_VTH_L 0x012
27#define R2057_VCOMONITOR_VTH_H 0x013
28#define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014
29#define R2057_VCO_VARCSIZE_IDAC 0x015
30#define R2057_VCOCAL_COUNTVAL0 0x016
31#define R2057_VCOCAL_COUNTVAL1 0x017
32#define R2057_VCOCAL_INTCLK_COUNT 0x018
33#define R2057_VCOCAL_MASTER 0x019
34#define R2057_VCOCAL_NUMCAPCHANGE 0x01a
35#define R2057_VCOCAL_WINSIZE 0x01b
36#define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c
37#define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d
38#define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e
39#define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f
40#define R2057_VCO_FORCECAPEN_FORCECAP1 0x020
41#define R2057_VCO_FORCECAP0 0x021
42#define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022
43#define R2057_RFPLL_PFD_RESET_PW 0x023
44#define R2057_RFPLL_LOOPFILTER_R2 0x024
45#define R2057_RFPLL_LOOPFILTER_R1 0x025
46#define R2057_RFPLL_LOOPFILTER_C3 0x026
47#define R2057_RFPLL_LOOPFILTER_C2 0x027
48#define R2057_RFPLL_LOOPFILTER_C1 0x028
49#define R2057_CP_KPD_IDAC 0x029
50#define R2057_RFPLL_IDACS 0x02a
51#define R2057_RFPLL_MISC_EN 0x02b
52#define R2057_RFPLL_MMD0 0x02c
53#define R2057_RFPLL_MMD1 0x02d
54#define R2057_RFPLL_MISC_CAL_RESETN 0x02e
55#define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f
56#define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030
57#define R2057_VCOCAL_READCAP0 0x031
58#define R2057_VCOCAL_READCAP1 0x032
59#define R2057_VCOCAL_STATUS 0x033
60#define R2057_LOGEN_PUS 0x034
61#define R2057_LOGEN_PTAT_RESETS 0x035
62#define R2057_VCOBUF_IDACS 0x036
63#define R2057_VCOBUF_TUNE 0x037
64#define R2057_CMOSBUF_TX2GQ_IDACS 0x038
65#define R2057_CMOSBUF_TX2GI_IDACS 0x039
66#define R2057_CMOSBUF_TX5GQ_IDACS 0x03a
67#define R2057_CMOSBUF_TX5GI_IDACS 0x03b
68#define R2057_CMOSBUF_RX2GQ_IDACS 0x03c
69#define R2057_CMOSBUF_RX2GI_IDACS 0x03d
70#define R2057_CMOSBUF_RX5GQ_IDACS 0x03e
71#define R2057_CMOSBUF_RX5GI_IDACS 0x03f
72#define R2057_LOGEN_MX2G_IDACS 0x040
73#define R2057_LOGEN_MX2G_TUNE 0x041
74#define R2057_LOGEN_MX5G_IDACS 0x042
75#define R2057_LOGEN_MX5G_TUNE 0x043
76#define R2057_LOGEN_MX5G_RCCR 0x044
77#define R2057_LOGEN_INDBUF2G_IDAC 0x045
78#define R2057_LOGEN_INDBUF2G_IBOOST 0x046
79#define R2057_LOGEN_INDBUF2G_TUNE 0x047
80#define R2057_LOGEN_INDBUF5G_IDAC 0x048
81#define R2057_LOGEN_INDBUF5G_IBOOST 0x049
82#define R2057_LOGEN_INDBUF5G_TUNE 0x04a
83#define R2057_CMOSBUF_TX_RCCR 0x04b
84#define R2057_CMOSBUF_RX_RCCR 0x04c
85#define R2057_LOGEN_SEL_PKDET 0x04d
86#define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e
87#define R2057_RXTXBIAS_CONFIG_CORE0 0x04f
88#define R2057_TXGM_TXRF_PUS_CORE0 0x050
89#define R2057_TXGM_IDAC_BLEED_CORE0 0x051
90#define R2057_TXGM_GAIN_CORE0 0x056
91#define R2057_TXGM2G_PKDET_PUS_CORE0 0x057
92#define R2057_PAD2G_PTATS_CORE0 0x058
93#define R2057_PAD2G_IDACS_CORE0 0x059
94#define R2057_PAD2G_BOOST_PU_CORE0 0x05a
95#define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b
96#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c
97#define R2057_TXMIX2G_LODC_CORE0 0x05d
98#define R2057_PAD2G_TUNE_PUS_CORE0 0x05e
99#define R2057_IPA2G_GAIN_CORE0 0x05f
100#define R2057_TSSI2G_SPARE1_CORE0 0x060
101#define R2057_TSSI2G_SPARE2_CORE0 0x061
102#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062
103#define R2057_IPA2G_IMAIN_CORE0 0x063
104#define R2057_IPA2G_CASCONV_CORE0 0x064
105#define R2057_IPA2G_CASCOFFV_CORE0 0x065
106#define R2057_IPA2G_BIAS_FILTER_CORE0 0x066
107#define R2057_TX5G_PKDET_CORE0 0x069
108#define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a
109#define R2057_PAD5G_PTATS1_CORE0 0x06b
110#define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c
111#define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d
112#define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e
113#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f
114#define R2057_PGA_BOOST_TUNE_CORE0 0x070
115#define R2057_PGA_GAIN_CORE0 0x071
116#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072
117#define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073
118#define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074
119#define R2057_IPA5G_IAUX_CORE0 0x075
120#define R2057_IPA5G_GAIN_CORE0 0x076
121#define R2057_TSSI5G_SPARE1_CORE0 0x077
122#define R2057_TSSI5G_SPARE2_CORE0 0x078
123#define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079
124#define R2057_IPA5G_PTAT_CORE0 0x07a
125#define R2057_IPA5G_IMAIN_CORE0 0x07b
126#define R2057_IPA5G_CASCONV_CORE0 0x07c
127#define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d
128#define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080
129#define R2057_TR2G_CONFIG1_CORE0_NU 0x081
130#define R2057_TR2G_CONFIG2_CORE0_NU 0x082
131#define R2057_LNA5G_RFEN_CORE0 0x083
132#define R2057_TR5G_CONFIG2_CORE0_NU 0x084
133#define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085
134#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086
135#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087
136#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088
137#define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089
138#define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a
139#define R2057_LNA2_IAUX_PTAT_CORE0 0x08b
140#define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c
141#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d
142#define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e
143#define R2057_TIA_CONFIG_CORE0 0x08f
144#define R2057_TIA_IQGAIN_CORE0 0x090
145#define R2057_TIA_IBIAS2_CORE0 0x091
146#define R2057_TIA_IBIAS1_CORE0 0x092
147#define R2057_TIA_SPARE_Q_CORE0 0x093
148#define R2057_TIA_SPARE_I_CORE0 0x094
149#define R2057_RXMIX2G_PUS_CORE0 0x095
150#define R2057_RXMIX2G_VCMREFS_CORE0 0x096
151#define R2057_RXMIX2G_LODC_QI_CORE0 0x097
152#define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098
153#define R2057_LNA2G_GAIN_CORE0 0x099
154#define R2057_LNA2G_TUNE_CORE0 0x09a
155#define R2057_RXMIX5G_PUS_CORE0 0x09b
156#define R2057_RXMIX5G_VCMREFS_CORE0 0x09c
157#define R2057_RXMIX5G_LODC_QI_CORE0 0x09d
158#define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e
159#define R2057_LNA5G_GAIN_CORE0 0x09f
160#define R2057_LNA5G_TUNE_CORE0 0x0a0
161#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1
162#define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2
163#define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3
164#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4
165#define R2057_TXBUF_VINCM_CORE0 0x0a5
166#define R2057_TXBUF_IDACS_CORE0 0x0a6
167#define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7
168#define R2057_RXBB_CC_CORE0 0x0a8
169#define R2057_RXBB_SPARE3_CORE0 0x0a9
170#define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa
171#define R2057_LPF_IDACS_CORE0 0x0ab
172#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac
173#define R2057_TXBUF_GAIN_CORE0 0x0ad
174#define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae
175#define R2057_RXBUF_DEGEN_CORE0 0x0af
176#define R2057_RXBB_SPARE2_CORE0 0x0b0
177#define R2057_RXBB_SPARE1_CORE0 0x0b1
178#define R2057_RSSI_MASTER_CORE0 0x0b2
179#define R2057_W2_MASTER_CORE0 0x0b3
180#define R2057_NB_MASTER_CORE0 0x0b4
181#define R2057_W2_IDACS0_Q_CORE0 0x0b5
182#define R2057_W2_IDACS1_Q_CORE0 0x0b6
183#define R2057_W2_IDACS0_I_CORE0 0x0b7
184#define R2057_W2_IDACS1_I_CORE0 0x0b8
185#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0x0b9
186#define R2057_NB_IDACS_Q_CORE0 0x0ba
187#define R2057_NB_IDACS_I_CORE0 0x0bb
188#define R2057_BACKUP4_CORE0 0x0c1
189#define R2057_BACKUP3_CORE0 0x0c2
190#define R2057_BACKUP2_CORE0 0x0c3
191#define R2057_BACKUP1_CORE0 0x0c4
192#define R2057_SPARE16_CORE0 0x0c5
193#define R2057_SPARE15_CORE0 0x0c6
194#define R2057_SPARE14_CORE0 0x0c7
195#define R2057_SPARE13_CORE0 0x0c8
196#define R2057_SPARE12_CORE0 0x0c9
197#define R2057_SPARE11_CORE0 0x0ca
198#define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb
199#define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc
200#define R2057_IQTEST_SEL_PU 0x0cd
201#define R2057_XTAL_CONFIG2 0x0ce
202#define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf
203#define R2057_TXLPF_RCCAL_CORE0 0x0d0
204#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1
205#define R2057_LPF_GAIN_CORE0 0x0d2
206#define R2057_DACBUF_IDACS_BW_CORE0 0x0d3
207#define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4
208#define R2057_TXGM_TXRF_PUS_CORE1 0x0d5
209#define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6
210#define R2057_TXGM_GAIN_CORE1 0x0db
211#define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc
212#define R2057_PAD2G_PTATS_CORE1 0x0dd
213#define R2057_PAD2G_IDACS_CORE1 0x0de
214#define R2057_PAD2G_BOOST_PU_CORE1 0x0df
215#define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0
216#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1
217#define R2057_TXMIX2G_LODC_CORE1 0x0e2
218#define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3
219#define R2057_IPA2G_GAIN_CORE1 0x0e4
220#define R2057_TSSI2G_SPARE1_CORE1 0x0e5
221#define R2057_TSSI2G_SPARE2_CORE1 0x0e6
222#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7
223#define R2057_IPA2G_IMAIN_CORE1 0x0e8
224#define R2057_IPA2G_CASCONV_CORE1 0x0e9
225#define R2057_IPA2G_CASCOFFV_CORE1 0x0ea
226#define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb
227#define R2057_TX5G_PKDET_CORE1 0x0ee
228#define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef
229#define R2057_PAD5G_PTATS1_CORE1 0x0f0
230#define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1
231#define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2
232#define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3
233#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4
234#define R2057_PGA_BOOST_TUNE_CORE1 0x0f5
235#define R2057_PGA_GAIN_CORE1 0x0f6
236#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7
237#define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8
238#define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9
239#define R2057_IPA5G_IAUX_CORE1 0x0fa
240#define R2057_IPA5G_GAIN_CORE1 0x0fb
241#define R2057_TSSI5G_SPARE1_CORE1 0x0fc
242#define R2057_TSSI5G_SPARE2_CORE1 0x0fd
243#define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe
244#define R2057_IPA5G_PTAT_CORE1 0x0ff
245#define R2057_IPA5G_IMAIN_CORE1 0x100
246#define R2057_IPA5G_CASCONV_CORE1 0x101
247#define R2057_IPA5G_BIAS_FILTER_CORE1 0x102
248#define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105
249#define R2057_TR2G_CONFIG1_CORE1_NU 0x106
250#define R2057_TR2G_CONFIG2_CORE1_NU 0x107
251#define R2057_LNA5G_RFEN_CORE1 0x108
252#define R2057_TR5G_CONFIG2_CORE1_NU 0x109
253#define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a
254#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b
255#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c
256#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d
257#define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e
258#define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f
259#define R2057_LNA2_IAUX_PTAT_CORE1 0x110
260#define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111
261#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112
262#define R2057_RXRFBIAS_BANDSEL_CORE1 0x113
263#define R2057_TIA_CONFIG_CORE1 0x114
264#define R2057_TIA_IQGAIN_CORE1 0x115
265#define R2057_TIA_IBIAS2_CORE1 0x116
266#define R2057_TIA_IBIAS1_CORE1 0x117
267#define R2057_TIA_SPARE_Q_CORE1 0x118
268#define R2057_TIA_SPARE_I_CORE1 0x119
269#define R2057_RXMIX2G_PUS_CORE1 0x11a
270#define R2057_RXMIX2G_VCMREFS_CORE1 0x11b
271#define R2057_RXMIX2G_LODC_QI_CORE1 0x11c
272#define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d
273#define R2057_LNA2G_GAIN_CORE1 0x11e
274#define R2057_LNA2G_TUNE_CORE1 0x11f
275#define R2057_RXMIX5G_PUS_CORE1 0x120
276#define R2057_RXMIX5G_VCMREFS_CORE1 0x121
277#define R2057_RXMIX5G_LODC_QI_CORE1 0x122
278#define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123
279#define R2057_LNA5G_GAIN_CORE1 0x124
280#define R2057_LNA5G_TUNE_CORE1 0x125
281#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126
282#define R2057_RXBB_BIAS_MASTER_CORE1 0x127
283#define R2057_RXBB_VGABUF_IDACS_CORE1 0x128
284#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129
285#define R2057_TXBUF_VINCM_CORE1 0x12a
286#define R2057_TXBUF_IDACS_CORE1 0x12b
287#define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c
288#define R2057_RXBB_CC_CORE1 0x12d
289#define R2057_RXBB_SPARE3_CORE1 0x12e
290#define R2057_RXBB_RCCAL_HPC_CORE1 0x12f
291#define R2057_LPF_IDACS_CORE1 0x130
292#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131
293#define R2057_TXBUF_GAIN_CORE1 0x132
294#define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133
295#define R2057_RXBUF_DEGEN_CORE1 0x134
296#define R2057_RXBB_SPARE2_CORE1 0x135
297#define R2057_RXBB_SPARE1_CORE1 0x136
298#define R2057_RSSI_MASTER_CORE1 0x137
299#define R2057_W2_MASTER_CORE1 0x138
300#define R2057_NB_MASTER_CORE1 0x139
301#define R2057_W2_IDACS0_Q_CORE1 0x13a
302#define R2057_W2_IDACS1_Q_CORE1 0x13b
303#define R2057_W2_IDACS0_I_CORE1 0x13c
304#define R2057_W2_IDACS1_I_CORE1 0x13d
305#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e
306#define R2057_NB_IDACS_Q_CORE1 0x13f
307#define R2057_NB_IDACS_I_CORE1 0x140
308#define R2057_BACKUP4_CORE1 0x146
309#define R2057_BACKUP3_CORE1 0x147
310#define R2057_BACKUP2_CORE1 0x148
311#define R2057_BACKUP1_CORE1 0x149
312#define R2057_SPARE16_CORE1 0x14a
313#define R2057_SPARE15_CORE1 0x14b
314#define R2057_SPARE14_CORE1 0x14c
315#define R2057_SPARE13_CORE1 0x14d
316#define R2057_SPARE12_CORE1 0x14e
317#define R2057_SPARE11_CORE1 0x14f
318#define R2057_TX2G_BIAS_RESETS_CORE1 0x150
319#define R2057_TX5G_BIAS_RESETS_CORE1 0x151
320#define R2057_SPARE8_CORE1 0x152
321#define R2057_SPARE7_CORE1 0x153
322#define R2057_BUFS_MISC_LPFBW_CORE1 0x154
323#define R2057_TXLPF_RCCAL_CORE1 0x155
324#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156
325#define R2057_LPF_GAIN_CORE1 0x157
326#define R2057_DACBUF_IDACS_BW_CORE1 0x158
327#define R2057_DACBUF_VINCM_CORE1 0x159
328#define R2057_RCCAL_START_R1_Q1_P1 0x15a
329#define R2057_RCCAL_X1 0x15b
330#define R2057_RCCAL_TRC0 0x15c
331#define R2057_RCCAL_TRC1 0x15d
332#define R2057_RCCAL_DONE_OSCCAP 0x15e
333#define R2057_RCCAL_N0_0 0x15f
334#define R2057_RCCAL_N0_1 0x160
335#define R2057_RCCAL_N1_0 0x161
336#define R2057_RCCAL_N1_1 0x162
337#define R2057_RCAL_STATUS 0x163
338#define R2057_XTALPUOVR_PINCTRL 0x164
339#define R2057_OVR_REG0 0x165
340#define R2057_OVR_REG1 0x166
341#define R2057_OVR_REG2 0x167
342#define R2057_OVR_REG3 0x168
343#define R2057_OVR_REG4 0x169
344#define R2057_RCCAL_SCAP_VAL 0x16a
345#define R2057_RCCAL_BCAP_VAL 0x16b
346#define R2057_RCCAL_HPC_VAL 0x16c
347#define R2057_RCCAL_OVERRIDES 0x16d
348#define R2057_TX0_IQCAL_GAIN_BW 0x170
349#define R2057_TX0_LOFT_FINE_I 0x171
350#define R2057_TX0_LOFT_FINE_Q 0x172
351#define R2057_TX0_LOFT_COARSE_I 0x173
352#define R2057_TX0_LOFT_COARSE_Q 0x174
353#define R2057_TX0_TX_SSI_MASTER 0x175
354#define R2057_TX0_IQCAL_VCM_HG 0x176
355#define R2057_TX0_IQCAL_IDAC 0x177
356#define R2057_TX0_TSSI_VCM 0x178
357#define R2057_TX0_TX_SSI_MUX 0x179
358#define R2057_TX0_TSSIA 0x17a
359#define R2057_TX0_TSSIG 0x17b
360#define R2057_TX0_TSSI_MISC1 0x17c
361#define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d
362#define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e
363#define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f
364#define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180
365#define R2057_TX1_IQCAL_GAIN_BW 0x190
366#define R2057_TX1_LOFT_FINE_I 0x191
367#define R2057_TX1_LOFT_FINE_Q 0x192
368#define R2057_TX1_LOFT_COARSE_I 0x193
369#define R2057_TX1_LOFT_COARSE_Q 0x194
370#define R2057_TX1_TX_SSI_MASTER 0x195
371#define R2057_TX1_IQCAL_VCM_HG 0x196
372#define R2057_TX1_IQCAL_IDAC 0x197
373#define R2057_TX1_TSSI_VCM 0x198
374#define R2057_TX1_TX_SSI_MUX 0x199
375#define R2057_TX1_TSSIA 0x19a
376#define R2057_TX1_TSSIG 0x19b
377#define R2057_TX1_TSSI_MISC1 0x19c
378#define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d
379#define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e
380#define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f
381#define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0
382#define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1
383#define R2057_AFE_SET_VCM_I_CORE0 0x1a2
384#define R2057_AFE_SET_VCM_Q_CORE0 0x1a3
385#define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4
386#define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5
387#define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6
388#define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7
389#define R2057_AFE_SET_VCM_I_CORE1 0x1a8
390#define R2057_AFE_SET_VCM_Q_CORE1 0x1a9
391#define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa
392#define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab
393#define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac
394
395#define R2057v7_DACBUF_VINCM_CORE0 0x1ad
396#define R2057v7_RCCAL_MASTER 0x1ae
397#define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af
398#define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0
399#define R2057v7_LOGEN_PUS1 0x1b1
400#define R2057v7_OVR_REG5 0x1b2
401#define R2057v7_OVR_REG6 0x1b3
402#define R2057v7_OVR_REG7 0x1b4
403#define R2057v7_OVR_REG8 0x1b5
404#define R2057v7_OVR_REG9 0x1b6
405#define R2057v7_OVR_REG10 0x1b7
406#define R2057v7_OVR_REG11 0x1b8
407#define R2057v7_OVR_REG12 0x1b9
408#define R2057v7_OVR_REG13 0x1ba
409#define R2057v7_OVR_REG14 0x1bb
410#define R2057v7_OVR_REG15 0x1bc
411#define R2057v7_OVR_REG16 0x1bd
412#define R2057v7_OVR_REG1 0x1be
413#define R2057v7_OVR_REG18 0x1bf
414#define R2057v7_OVR_REG19 0x1c0
415#define R2057v7_OVR_REG20 0x1c1
416#define R2057v7_OVR_REG21 0x1c2
417#define R2057v7_OVR_REG2 0x1c3
418#define R2057v7_OVR_REG23 0x1c4
419#define R2057v7_OVR_REG24 0x1c5
420#define R2057v7_OVR_REG25 0x1c6
421#define R2057v7_OVR_REG26 0x1c7
422#define R2057v7_OVR_REG27 0x1c8
423#define R2057v7_OVR_REG28 0x1c9
424#define R2057v7_IQTEST_SEL_PU2 0x1ca
425
426#define R2057_VCM_MASK 0x7
427
428void r2057_upload_inittabs(struct b43_wldev *dev);
429
430#endif /* B43_RADIO_2057_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 22:59:04 -0400