diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2011-09-04 17:23:53 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-09-14 13:56:30 -0400 |
commit | 0eff8fcd290dc7f25d393fb3692e8e673babdeeb (patch) | |
tree | 6fa52b2182a8cc14382aa10c2ca254dc8e552954 /drivers/net/wireless/b43/phy_n.c | |
parent | 73d07a39ee3eadb9ff6734432151a10c50329804 (diff) |
b43: N-PHY: implement few random missing ops
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43/phy_n.c')
-rw-r--r-- | drivers/net/wireless/b43/phy_n.c | 111 |
1 files changed, 94 insertions, 17 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c index 8647933f9321..b17d9b6c33a5 100644 --- a/drivers/net/wireless/b43/phy_n.c +++ b/drivers/net/wireless/b43/phy_n.c | |||
@@ -78,6 +78,7 @@ enum b43_nphy_rssi_type { | |||
78 | B43_NPHY_RSSI_TBD, | 78 | B43_NPHY_RSSI_TBD, |
79 | }; | 79 | }; |
80 | 80 | ||
81 | /* TODO: reorder functions */ | ||
81 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, | 82 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, |
82 | bool enable); | 83 | bool enable); |
83 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, | 84 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, |
@@ -88,6 +89,7 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, | |||
88 | u16 value, u8 core, bool off); | 89 | u16 value, u8 core, bool off); |
89 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, | 90 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, |
90 | u16 value, u8 core); | 91 | u16 value, u8 core); |
92 | static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev); | ||
91 | 93 | ||
92 | static inline bool b43_nphy_ipa(struct b43_wldev *dev) | 94 | static inline bool b43_nphy_ipa(struct b43_wldev *dev) |
93 | { | 95 | { |
@@ -453,8 +455,14 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |||
453 | tmp = (tmp & 0xFF00) | bbmult; | 455 | tmp = (tmp & 0xFF00) | bbmult; |
454 | b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); | 456 | b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); |
455 | 457 | ||
456 | if (0) | 458 | if (b43_nphy_ipa(dev)) { |
457 | ; /* TODO */ | 459 | u32 tmp32; |
460 | u16 reg = (i == 0) ? | ||
461 | B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1; | ||
462 | tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, txpi[i])); | ||
463 | b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); | ||
464 | b43_phy_set(dev, reg, 0x4); | ||
465 | } | ||
458 | } | 466 | } |
459 | 467 | ||
460 | b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); | 468 | b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); |
@@ -463,6 +471,57 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |||
463 | b43_nphy_stay_in_carrier_search(dev, 0); | 471 | b43_nphy_stay_in_carrier_search(dev, 0); |
464 | } | 472 | } |
465 | 473 | ||
474 | static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) | ||
475 | { | ||
476 | struct b43_phy *phy = &dev->phy; | ||
477 | |||
478 | const u32 *table = NULL; | ||
479 | #if 0 | ||
480 | TODO: b43_ntab_papd_pga_gain_delta_ipa_2* | ||
481 | u32 rfpwr_offset; | ||
482 | u8 pga_gain; | ||
483 | int i; | ||
484 | #endif | ||
485 | |||
486 | if (phy->rev >= 3) { | ||
487 | if (b43_nphy_ipa(dev)) { | ||
488 | table = b43_nphy_get_ipa_gain_table(dev); | ||
489 | } else { | ||
490 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | ||
491 | if (phy->rev == 3) | ||
492 | table = b43_ntab_tx_gain_rev3_5ghz; | ||
493 | if (phy->rev == 4) | ||
494 | table = b43_ntab_tx_gain_rev4_5ghz; | ||
495 | else | ||
496 | table = b43_ntab_tx_gain_rev5plus_5ghz; | ||
497 | } else { | ||
498 | table = b43_ntab_tx_gain_rev3plus_2ghz; | ||
499 | } | ||
500 | } | ||
501 | } else { | ||
502 | table = b43_ntab_tx_gain_rev0_1_2; | ||
503 | } | ||
504 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); | ||
505 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); | ||
506 | |||
507 | if (phy->rev >= 3) { | ||
508 | #if 0 | ||
509 | nphy->gmval = (table[0] >> 16) & 0x7000; | ||
510 | |||
511 | for (i = 0; i < 128; i++) { | ||
512 | pga_gain = (table[i] >> 24) & 0xF; | ||
513 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | ||
514 | rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; | ||
515 | else | ||
516 | rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain]; | ||
517 | b43_ntab_write(dev, B43_NTAB32(26, 576 + i), | ||
518 | rfpwr_offset); | ||
519 | b43_ntab_write(dev, B43_NTAB32(27, 576 + i), | ||
520 | rfpwr_offset); | ||
521 | } | ||
522 | #endif | ||
523 | } | ||
524 | } | ||
466 | 525 | ||
467 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ | 526 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ |
468 | static void b43_radio_2055_setup(struct b43_wldev *dev, | 527 | static void b43_radio_2055_setup(struct b43_wldev *dev, |
@@ -1430,8 +1489,19 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) | |||
1430 | 1489 | ||
1431 | static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) | 1490 | static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) |
1432 | { | 1491 | { |
1492 | struct b43_phy_n *nphy = dev->phy.n; | ||
1433 | struct ssb_sprom *sprom = dev->dev->bus_sprom; | 1493 | struct ssb_sprom *sprom = dev->dev->bus_sprom; |
1434 | 1494 | ||
1495 | /* TX to RX */ | ||
1496 | u8 tx2rx_events[9] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F }; | ||
1497 | u8 tx2rx_delays[9] = { 8, 4, 2, 2, 4, 4, 6, 1 }; | ||
1498 | /* RX to TX */ | ||
1499 | u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, | ||
1500 | 0x1F }; | ||
1501 | u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; | ||
1502 | u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; | ||
1503 | u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; | ||
1504 | |||
1435 | u16 tmp16; | 1505 | u16 tmp16; |
1436 | u32 tmp32; | 1506 | u32 tmp32; |
1437 | 1507 | ||
@@ -1449,7 +1519,22 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) | |||
1449 | b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); | 1519 | b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); |
1450 | b43_phy_write(dev, 0x2AE, 0x000C); | 1520 | b43_phy_write(dev, 0x2AE, 0x000C); |
1451 | 1521 | ||
1452 | /* TODO */ | 1522 | /* TX to RX */ |
1523 | b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 9); | ||
1524 | |||
1525 | /* RX to TX */ | ||
1526 | if (b43_nphy_ipa(dev)) | ||
1527 | b43_nphy_set_rf_sequence(dev, 1, rx2tx_events_ipa, | ||
1528 | rx2tx_delays_ipa, 9); | ||
1529 | if (nphy->hw_phyrxchain != 3 && | ||
1530 | nphy->hw_phyrxchain != nphy->hw_phytxchain) { | ||
1531 | if (b43_nphy_ipa(dev)) { | ||
1532 | rx2tx_delays[5] = 59; | ||
1533 | rx2tx_delays[6] = 1; | ||
1534 | rx2tx_events[7] = 0x1F; | ||
1535 | } | ||
1536 | b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays, 9); | ||
1537 | } | ||
1453 | 1538 | ||
1454 | tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? | 1539 | tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? |
1455 | 0x2 : 0x9C40; | 1540 | 0x2 : 0x9C40; |
@@ -1553,8 +1638,8 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) | |||
1553 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | 1638 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); |
1554 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | 1639 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); |
1555 | 1640 | ||
1556 | if (sprom->boardflags2_lo & 0x100 && | 1641 | if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD && |
1557 | dev->dev->board_type == 0x8B) { | 1642 | dev->dev->board_type == 0x8B) { |
1558 | delays1[0] = 0x1; | 1643 | delays1[0] = 0x1; |
1559 | delays1[5] = 0x14; | 1644 | delays1[5] = 0x14; |
1560 | } | 1645 | } |
@@ -2649,8 +2734,8 @@ static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) | |||
2649 | { | 2734 | { |
2650 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | 2735 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { |
2651 | if (dev->phy.rev >= 6) { | 2736 | if (dev->phy.rev >= 6) { |
2652 | /* TODO If the chip is 47162 | 2737 | if (dev->dev->chip_id == 47162) |
2653 | return txpwrctrl_tx_gain_ipa_rev5 */ | 2738 | return txpwrctrl_tx_gain_ipa_rev5; |
2654 | return txpwrctrl_tx_gain_ipa_rev6; | 2739 | return txpwrctrl_tx_gain_ipa_rev6; |
2655 | } else if (dev->phy.rev >= 5) { | 2740 | } else if (dev->phy.rev >= 5) { |
2656 | return txpwrctrl_tx_gain_ipa_rev5; | 2741 | return txpwrctrl_tx_gain_ipa_rev5; |
@@ -3717,7 +3802,7 @@ int b43_phy_initn(struct b43_wldev *dev) | |||
3717 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); | 3802 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); |
3718 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); | 3803 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); |
3719 | 3804 | ||
3720 | if (sprom->boardflags2_lo & 0x100 || | 3805 | if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || |
3721 | (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && | 3806 | (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && |
3722 | dev->dev->board_type == 0x8B)) | 3807 | dev->dev->board_type == 0x8B)) |
3723 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); | 3808 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); |
@@ -3774,15 +3859,7 @@ int b43_phy_initn(struct b43_wldev *dev) | |||
3774 | b43_nphy_tx_power_fix(dev); | 3859 | b43_nphy_tx_power_fix(dev); |
3775 | /* TODO N PHY TX Power Control Idle TSSI */ | 3860 | /* TODO N PHY TX Power Control Idle TSSI */ |
3776 | /* TODO N PHY TX Power Control Setup */ | 3861 | /* TODO N PHY TX Power Control Setup */ |
3777 | 3862 | b43_nphy_tx_gain_table_upload(dev); | |
3778 | if (phy->rev >= 3) { | ||
3779 | /* TODO */ | ||
3780 | } else { | ||
3781 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, | ||
3782 | b43_ntab_tx_gain_rev0_1_2); | ||
3783 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, | ||
3784 | b43_ntab_tx_gain_rev0_1_2); | ||
3785 | } | ||
3786 | 3863 | ||
3787 | if (nphy->phyrxchain != 3) | 3864 | if (nphy->phyrxchain != 3) |
3788 | b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); | 3865 | b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); |