ath9k: Adding support for Atheros AR9285 chipset.

Signed-off-by: Senthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 98 insertions, 0 deletions

diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 51c8a3ce4e60..3c7454fc51bd 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -818,6 +818,101 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
         return true;
 }
 
+static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)
+{
+
+        u32 regVal;
+        int i, offset, offs_6_1, offs_0;
+        u32 ccomp_org, reg_field;
+        u32 regList[][2] = {
+                { 0x786c, 0 },
+                { 0x7854, 0 },
+                { 0x7820, 0 },
+                { 0x7824, 0 },
+                { 0x7868, 0 },
+                { 0x783c, 0 },
+                { 0x7838, 0 },
+        };
+
+        if (AR_SREV_9285_11(ah)) {
+                REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
+                udelay(10);
+        }
+
+        for (i = 0; i < ARRAY_SIZE(regList); i++)
+                regList[i][1] = REG_READ(ah, regList[i][0]);
+
+        regVal = REG_READ(ah, 0x7834);
+        regVal &= (~(0x1));
+        REG_WRITE(ah, 0x7834, regVal);
+        regVal = REG_READ(ah, 0x9808);
+        regVal |= (0x1 << 27);
+        REG_WRITE(ah, 0x9808, regVal);
+
+        REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
+        REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
+        REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
+        REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
+        ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);
+
+        REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
+        udelay(30);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
+
+        for (i = 6; i > 0; i--) {
+                regVal = REG_READ(ah, 0x7834);
+                regVal |= (1 << (19 + i));
+                REG_WRITE(ah, 0x7834, regVal);
+                udelay(1);
+                regVal = REG_READ(ah, 0x7834);
+                regVal &= (~(0x1 << (19 + i)));
+                reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
+                regVal |= (reg_field << (19 + i));
+                REG_WRITE(ah, 0x7834, regVal);
+        }
+
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
+        udelay(1);
+        reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
+        offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
+        offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
+
+        offset = (offs_6_1<<1) | offs_0;
+        offset = offset - 0;
+        offs_6_1 = offset>>1;
+        offs_0 = offset & 1;
+
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
+
+        regVal = REG_READ(ah, 0x7834);
+        regVal |= 0x1;
+        REG_WRITE(ah, 0x7834, regVal);
+        regVal = REG_READ(ah, 0x9808);
+        regVal &= (~(0x1 << 27));
+        REG_WRITE(ah, 0x9808, regVal);
+
+        for (i = 0; i < ARRAY_SIZE(regList); i++)
+                REG_WRITE(ah, regList[i][0], regList[i][1]);
+
+        REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
+
+        if (AR_SREV_9285_11(ah))
+                REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
+
+}
+
 bool ath9k_hw_init_cal(struct ath_hal *ah,
                        struct ath9k_channel *chan)
 {
@@ -835,6 +930,9 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
                 return false;
         }
 
+        if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))
+                ath9k_hw_9285_pa_cal(ah);
+
         REG_WRITE(ah, AR_PHY_AGC_CONTROL,
                   REG_READ(ah, AR_PHY_AGC_CONTROL) |
                   AR_PHY_AGC_CONTROL_NF);