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authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>2012-06-04 06:58:47 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-06-06 15:20:29 -0400
commit153dccd467b818b1dd3a6801b14e94a7a48ef859 (patch)
treeaf763f63b0892c2c026fc885cb0760fbe9dbc798 /drivers/net/wireless/ath/ath9k/hw.c
parentc9ae6ab4c7d7aa29f9607ac69daafbc241fc123e (diff)
ath9k_hw: fix power state for MCI
Program MCI related power registers only if MCI interrupts are enabled. This could help to reduce power consumptions when WLAN alone is enabled in BT coex chips. Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/hw.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c25
1 files changed, 9 insertions, 16 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 98478fd5d284..45e670087e1c 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -2009,12 +2009,9 @@ static void ath9k_set_power_sleep(struct ath_hw *ah)
2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2009 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2010 2010
2011 if (AR_SREV_9462(ah)) { 2011 if (AR_SREV_9462(ah)) {
2012 REG_WRITE(ah, AR_TIMER_MODE, 2012 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2013 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 2013 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2014 REG_WRITE(ah, AR_NDP2_TIMER_MODE, 2014 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2015 REG_READ(ah, AR_NDP2_TIMER_MODE) & 0xFFFFFF00);
2016 REG_WRITE(ah, AR_SLP32_INC,
2017 REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
2018 /* xxx Required for WLAN only case ? */ 2015 /* xxx Required for WLAN only case ? */
2019 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); 2016 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2020 udelay(100); 2017 udelay(100);
@@ -2026,7 +2023,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah)
2026 */ 2023 */
2027 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 2024 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2028 2025
2029 if (AR_SREV_9462(ah)) 2026 if (ath9k_hw_mci_is_enabled(ah))
2030 udelay(100); 2027 udelay(100);
2031 2028
2032 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 2029 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
@@ -2051,7 +2048,6 @@ static void ath9k_set_power_sleep(struct ath_hw *ah)
2051static void ath9k_set_power_network_sleep(struct ath_hw *ah) 2048static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2052{ 2049{
2053 struct ath9k_hw_capabilities *pCap = &ah->caps; 2050 struct ath9k_hw_capabilities *pCap = &ah->caps;
2054 u32 val;
2055 2051
2056 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 2052 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2057 2053
@@ -2070,19 +2066,16 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2070 * SYS_WAKING and SYS_SLEEPING messages which will make 2066 * SYS_WAKING and SYS_SLEEPING messages which will make
2071 * BT CPU to busy to process. 2067 * BT CPU to busy to process.
2072 */ 2068 */
2073 if (AR_SREV_9462(ah)) { 2069 if (ath9k_hw_mci_is_enabled(ah))
2074 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 2070 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2075 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 2071 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2076 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
2077 }
2078 /* 2072 /*
2079 * Clear the RTC force wake bit to allow the 2073 * Clear the RTC force wake bit to allow the
2080 * mac to go to sleep. 2074 * mac to go to sleep.
2081 */ 2075 */
2082 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 2076 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2083 AR_RTC_FORCE_WAKE_EN);
2084 2077
2085 if (AR_SREV_9462(ah)) 2078 if (ath9k_hw_mci_is_enabled(ah))
2086 udelay(30); 2079 udelay(30);
2087 } 2080 }
2088 2081