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authorFelix Fietkau <nbd@openwrt.org>2010-04-15 17:38:33 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-16 15:43:23 -0400
commitf7abf0c1958ab363874cad0d799a1bb43880145a (patch)
treeecceb819d6f50ec1338bf183392a6e7206f33b79 /drivers/net/wireless/ath/ath9k/ar9003_phy.c
parent7152451aa12558ab032f319a119ceb928396b905 (diff)
ath9k_hw: Set the channel on AR9003
Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_phy.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c47
1 files changed, 46 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 084b0f92afde..f1632abdce50 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -44,7 +44,52 @@
44 */ 44 */
45static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 45static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
46{ 46{
47 /* TODO */ 47 u16 bMode, fracMode = 0, aModeRefSel = 0;
48 u32 freq, channelSel = 0, reg32 = 0;
49 struct chan_centers centers;
50 int loadSynthChannel;
51
52 ath9k_hw_get_channel_centers(ah, chan, &centers);
53 freq = centers.synth_center;
54
55 if (freq < 4800) { /* 2 GHz, fractional mode */
56 channelSel = CHANSEL_2G(freq);
57 /* Set to 2G mode */
58 bMode = 1;
59 } else {
60 channelSel = CHANSEL_5G(freq);
61 /* Doubler is ON, so, divide channelSel by 2. */
62 channelSel >>= 1;
63 /* Set to 5G mode */
64 bMode = 0;
65 }
66
67 /* Enable fractional mode for all channels */
68 fracMode = 1;
69 aModeRefSel = 0;
70 loadSynthChannel = 0;
71
72 reg32 = (bMode << 29);
73 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
74
75 /* Enable Long shift Select for Synthesizer */
76 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
77 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
78
79 /* Program Synth. setting */
80 reg32 = (channelSel << 2) | (fracMode << 30) |
81 (aModeRefSel << 28) | (loadSynthChannel << 31);
82 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
83
84 /* Toggle Load Synth channel bit */
85 loadSynthChannel = 1;
86 reg32 = (channelSel << 2) | (fracMode << 30) |
87 (aModeRefSel << 28) | (loadSynthChannel << 31);
88 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
89
90 ah->curchan = chan;
91 ah->curchan_rad_index = -1;
92
48 return 0; 93 return 0;
49} 94}
50 95