aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
diff options
context:
space:
mode:
authorFelix Fietkau <nbd@openwrt.org>2010-05-11 11:23:03 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-05-12 16:39:07 -0400
commitffdc4cbe5b17c83af779f45de8536c6ece297e42 (patch)
tree07de5a7693a1b76fbd1f213e2a472ac346b82182 /drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
parent9bff0bc4012c7f079b297eb45b47780e3713f367 (diff)
ath9k_hw: clean up EEPROM endian handling on AR9003
Remove the double swapping of the descriptor data structure, instead keep it little-endian (native format of the eeprom data), and byteswap on access. This allows sparse to verify endian access to the eeprom struct. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_eeprom.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index d8c0318f416f..23fb353c3bba 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -169,7 +169,7 @@ enum CompressAlgorithm {
169}; 169};
170 170
171struct ar9300_base_eep_hdr { 171struct ar9300_base_eep_hdr {
172 u16 regDmn[2]; 172 __le16 regDmn[2];
173 /* 4 bits tx and 4 bits rx */ 173 /* 4 bits tx and 4 bits rx */
174 u8 txrxMask; 174 u8 txrxMask;
175 struct eepFlags opCapFlags; 175 struct eepFlags opCapFlags;
@@ -199,16 +199,16 @@ struct ar9300_base_eep_hdr {
199 u8 rxBandSelectGpio; 199 u8 rxBandSelectGpio;
200 u8 txrxgain; 200 u8 txrxgain;
201 /* SW controlled internal regulator fields */ 201 /* SW controlled internal regulator fields */
202 u32 swreg; 202 __le32 swreg;
203} __packed; 203} __packed;
204 204
205struct ar9300_modal_eep_header { 205struct ar9300_modal_eep_header {
206 /* 4 idle, t1, t2, b (4 bits per setting) */ 206 /* 4 idle, t1, t2, b (4 bits per setting) */
207 u32 antCtrlCommon; 207 __le32 antCtrlCommon;
208 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 208 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
209 u32 antCtrlCommon2; 209 __le32 antCtrlCommon2;
210 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */ 210 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
211 u16 antCtrlChain[AR9300_MAX_CHAINS]; 211 __le16 antCtrlChain[AR9300_MAX_CHAINS];
212 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 212 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
213 u8 xatten1DB[AR9300_MAX_CHAINS]; 213 u8 xatten1DB[AR9300_MAX_CHAINS];
214 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */ 214 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */