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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-01-10 23:10:08 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-01-10 23:10:08 -0500
commiteed0ba0b4ab2d1668588219a8efa81bf8636a12d (patch)
treef5aa3c732e7830a1b24e6071f8bed0f799881187 /drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
parent98b14d6b290d96b24ae993ceaccc59b2aa4b130c (diff)
parentc9de9333f5a860cab82052bce6ac28bcac9b2c26 (diff)
Merge remote branch 'gcl/next' into next
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_eeprom.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c73
1 files changed, 38 insertions, 35 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index c4182359bee4..a7b82f0085d2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -55,6 +55,8 @@
55#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 55#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
56#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 56#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
57 57
58#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
59
58static const struct ar9300_eeprom ar9300_default = { 60static const struct ar9300_eeprom ar9300_default = {
59 .eepromVersion = 2, 61 .eepromVersion = 2,
60 .templateVersion = 2, 62 .templateVersion = 2,
@@ -290,20 +292,21 @@ static const struct ar9300_eeprom ar9300_default = {
290 } 292 }
291 }, 293 },
292 .ctlPowerData_2G = { 294 .ctlPowerData_2G = {
293 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 295 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
294 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 296 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
295 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } }, 297 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
296 298
297 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } }, 299 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
298 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 300 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
299 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 301 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
300 302
301 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } }, 303 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
302 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 304 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
303 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 305 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
304 306
305 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } }, 307 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
306 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } }, 308 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
309 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
307 }, 310 },
308 .modalHeader5G = { 311 .modalHeader5G = {
309 /* 4 idle,t1,t2,b (4 bits per setting) */ 312 /* 4 idle,t1,t2,b (4 bits per setting) */
@@ -568,56 +571,56 @@ static const struct ar9300_eeprom ar9300_default = {
568 .ctlPowerData_5G = { 571 .ctlPowerData_5G = {
569 { 572 {
570 { 573 {
571 {60, 1}, {60, 1}, {60, 1}, {60, 1}, 574 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
572 {60, 1}, {60, 1}, {60, 1}, {60, 0}, 575 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
573 } 576 }
574 }, 577 },
575 { 578 {
576 { 579 {
577 {60, 1}, {60, 1}, {60, 1}, {60, 1}, 580 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
578 {60, 1}, {60, 1}, {60, 1}, {60, 0}, 581 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
579 } 582 }
580 }, 583 },
581 { 584 {
582 { 585 {
583 {60, 0}, {60, 1}, {60, 0}, {60, 1}, 586 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
584 {60, 1}, {60, 1}, {60, 1}, {60, 1}, 587 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
585 } 588 }
586 }, 589 },
587 { 590 {
588 { 591 {
589 {60, 0}, {60, 1}, {60, 1}, {60, 0}, 592 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
590 {60, 1}, {60, 0}, {60, 0}, {60, 0}, 593 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
591 } 594 }
592 }, 595 },
593 { 596 {
594 { 597 {
595 {60, 1}, {60, 1}, {60, 1}, {60, 0}, 598 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
596 {60, 0}, {60, 0}, {60, 0}, {60, 0}, 599 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
597 } 600 }
598 }, 601 },
599 { 602 {
600 { 603 {
601 {60, 1}, {60, 1}, {60, 1}, {60, 1}, 604 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
602 {60, 1}, {60, 0}, {60, 0}, {60, 0}, 605 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
603 } 606 }
604 }, 607 },
605 { 608 {
606 { 609 {
607 {60, 1}, {60, 1}, {60, 1}, {60, 1}, 610 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
608 {60, 1}, {60, 1}, {60, 1}, {60, 1}, 611 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
609 } 612 }
610 }, 613 },
611 { 614 {
612 { 615 {
613 {60, 1}, {60, 1}, {60, 0}, {60, 1}, 616 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
614 {60, 1}, {60, 1}, {60, 1}, {60, 0}, 617 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
615 } 618 }
616 }, 619 },
617 { 620 {
618 { 621 {
619 {60, 1}, {60, 0}, {60, 1}, {60, 1}, 622 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
620 {60, 1}, {60, 1}, {60, 0}, {60, 1}, 623 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
621 } 624 }
622 }, 625 },
623 } 626 }
@@ -1827,9 +1830,9 @@ static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
1827 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; 1830 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
1828 1831
1829 if (is2GHz) 1832 if (is2GHz)
1830 return ctl_2g[idx].ctlEdges[edge].tPower; 1833 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
1831 else 1834 else
1832 return ctl_5g[idx].ctlEdges[edge].tPower; 1835 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
1833} 1836}
1834 1837
1835static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, 1838static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
@@ -1847,12 +1850,12 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
1847 1850
1848 if (is2GHz) { 1851 if (is2GHz) {
1849 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && 1852 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
1850 ctl_2g[idx].ctlEdges[edge - 1].flag) 1853 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
1851 return ctl_2g[idx].ctlEdges[edge - 1].tPower; 1854 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
1852 } else { 1855 } else {
1853 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && 1856 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
1854 ctl_5g[idx].ctlEdges[edge - 1].flag) 1857 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
1855 return ctl_5g[idx].ctlEdges[edge - 1].tPower; 1858 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
1856 } 1859 }
1857 1860
1858 return AR9300_MAX_RATE_POWER; 1861 return AR9300_MAX_RATE_POWER;