diff options
author | Peer Chen <Peer.Chen@uli.com.tw> | 2005-07-29 15:33:58 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-07-29 15:33:58 -0400 |
commit | 4689ced99b18937e28c0f6c190394ccc3c61d651 (patch) | |
tree | aaec0912f3802359f1fd2023e078cf3d31c57286 /drivers/net/tulip | |
parent | c32511e2718618f0b53479eb36e07439aa363a74 (diff) |
[netdrvr] add 'uli526x' driver (a tulip clone)
We want to extract our LAN card driver from tulip core driver and
make a new file uli526x.c at tulip folder, because we have added
some ethtool interface support and non-eprom support in our driver
and may be other change in the futher.
If our controllers support are still contained in the tulip core
driver, I think it'll increase the complexity of maintenance, you
know, tulip core driver include several files and support so many
other controllers. Furthermore, I tested the newest kernel 2.6.12
and I found the tulip driver can not work on our lan controller, and
I no time to debug it, so I aspired want to make a single uli526x.c
file just for our controllers. Could you help us remove the ULi
m5261/m5263 lan controller support from tulip core driver and add
the new single uli526x.c file for us?
Signed-off-by: Peer Chen <Peer.Chen@uli.com.tw>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/tulip')
-rw-r--r-- | drivers/net/tulip/Kconfig | 12 | ||||
-rw-r--r-- | drivers/net/tulip/Makefile | 1 | ||||
-rw-r--r-- | drivers/net/tulip/uli526x.c | 1770 |
3 files changed, 1783 insertions, 0 deletions
diff --git a/drivers/net/tulip/Kconfig b/drivers/net/tulip/Kconfig index e2cdaf876201..8c9634a98c11 100644 --- a/drivers/net/tulip/Kconfig +++ b/drivers/net/tulip/Kconfig | |||
@@ -135,6 +135,18 @@ config DM9102 | |||
135 | <file:Documentation/networking/net-modules.txt>. The module will | 135 | <file:Documentation/networking/net-modules.txt>. The module will |
136 | be called dmfe. | 136 | be called dmfe. |
137 | 137 | ||
138 | config ULI526X | ||
139 | tristate "ULi M526x controller support" | ||
140 | depends on NET_TULIP && PCI | ||
141 | select CRC32 | ||
142 | ---help--- | ||
143 | This driver is for ULi M5261/M5263 10/100M Ethernet Controller | ||
144 | (<http://www.uli.com.tw/>). | ||
145 | |||
146 | To compile this driver as a module, choose M here and read | ||
147 | <file:Documentation/networking/net-modules.txt>. The module will | ||
148 | be called uli526x. | ||
149 | |||
138 | config PCMCIA_XIRCOM | 150 | config PCMCIA_XIRCOM |
139 | tristate "Xircom CardBus support (new driver)" | 151 | tristate "Xircom CardBus support (new driver)" |
140 | depends on NET_TULIP && CARDBUS | 152 | depends on NET_TULIP && CARDBUS |
diff --git a/drivers/net/tulip/Makefile b/drivers/net/tulip/Makefile index 8bb9b4683979..451090d6fcca 100644 --- a/drivers/net/tulip/Makefile +++ b/drivers/net/tulip/Makefile | |||
@@ -9,6 +9,7 @@ obj-$(CONFIG_WINBOND_840) += winbond-840.o | |||
9 | obj-$(CONFIG_DE2104X) += de2104x.o | 9 | obj-$(CONFIG_DE2104X) += de2104x.o |
10 | obj-$(CONFIG_TULIP) += tulip.o | 10 | obj-$(CONFIG_TULIP) += tulip.o |
11 | obj-$(CONFIG_DE4X5) += de4x5.o | 11 | obj-$(CONFIG_DE4X5) += de4x5.o |
12 | obj-$(CONFIG_ULI526X) += uli526x.o | ||
12 | 13 | ||
13 | # Declare multi-part drivers. | 14 | # Declare multi-part drivers. |
14 | 15 | ||
diff --git a/drivers/net/tulip/uli526x.c b/drivers/net/tulip/uli526x.c new file mode 100644 index 000000000000..27f99e087f79 --- /dev/null +++ b/drivers/net/tulip/uli526x.c | |||
@@ -0,0 +1,1770 @@ | |||
1 | /* | ||
2 | This program is free software; you can redistribute it and/or | ||
3 | modify it under the terms of the GNU General Public License | ||
4 | as published by the Free Software Foundation; either version 2 | ||
5 | of the License, or (at your option) any later version. | ||
6 | |||
7 | This program is distributed in the hope that it will be useful, | ||
8 | but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
10 | GNU General Public License for more details. | ||
11 | |||
12 | |||
13 | */ | ||
14 | |||
15 | #define DRV_NAME "uli526x" | ||
16 | #define DRV_VERSION "0.9.3" | ||
17 | #define DRV_RELDATE "2005-7-29" | ||
18 | |||
19 | #include <linux/module.h> | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/string.h> | ||
23 | #include <linux/timer.h> | ||
24 | #include <linux/ptrace.h> | ||
25 | #include <linux/errno.h> | ||
26 | #include <linux/ioport.h> | ||
27 | #include <linux/slab.h> | ||
28 | #include <linux/interrupt.h> | ||
29 | #include <linux/pci.h> | ||
30 | #include <linux/init.h> | ||
31 | #include <linux/netdevice.h> | ||
32 | #include <linux/etherdevice.h> | ||
33 | #include <linux/ethtool.h> | ||
34 | #include <linux/skbuff.h> | ||
35 | #include <linux/delay.h> | ||
36 | #include <linux/spinlock.h> | ||
37 | |||
38 | #include <asm/processor.h> | ||
39 | #include <asm/bitops.h> | ||
40 | #include <asm/io.h> | ||
41 | #include <asm/dma.h> | ||
42 | #include <asm/uaccess.h> | ||
43 | |||
44 | |||
45 | /* Board/System/Debug information/definition ---------------- */ | ||
46 | #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/ | ||
47 | #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/ | ||
48 | |||
49 | #define ULI526X_IO_SIZE 0x100 | ||
50 | #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */ | ||
51 | #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */ | ||
52 | #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */ | ||
53 | #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */ | ||
54 | #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) | ||
55 | #define TX_BUF_ALLOC 0x600 | ||
56 | #define RX_ALLOC_SIZE 0x620 | ||
57 | #define ULI526X_RESET 1 | ||
58 | #define CR0_DEFAULT 0 | ||
59 | #define CR6_DEFAULT 0x00080000 /* HD */ | ||
60 | #define CR6_DEFAULT_A 0x22240000 | ||
61 | #define CR7_DEFAULT 0x180c1 | ||
62 | #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */ | ||
63 | #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */ | ||
64 | #define MAX_PACKET_SIZE 1514 | ||
65 | #define ULI5261_MAX_MULTICAST 14 | ||
66 | #define RX_COPY_SIZE 100 | ||
67 | #define MAX_CHECK_PACKET 0x8000 | ||
68 | |||
69 | #define ULI526X_10MHF 0 | ||
70 | #define ULI526X_100MHF 1 | ||
71 | #define ULI526X_10MFD 4 | ||
72 | #define ULI526X_100MFD 5 | ||
73 | #define ULI526X_AUTO 8 | ||
74 | |||
75 | #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */ | ||
76 | #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */ | ||
77 | #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */ | ||
78 | #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */ | ||
79 | #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */ | ||
80 | #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */ | ||
81 | |||
82 | #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */ | ||
83 | #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */ | ||
84 | #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */ | ||
85 | |||
86 | #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value)) | ||
87 | |||
88 | #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half"); | ||
89 | |||
90 | |||
91 | /* CR9 definition: SROM/MII */ | ||
92 | #define CR9_SROM_READ 0x4800 | ||
93 | #define CR9_SRCS 0x1 | ||
94 | #define CR9_SRCLK 0x2 | ||
95 | #define CR9_CRDOUT 0x8 | ||
96 | #define SROM_DATA_0 0x0 | ||
97 | #define SROM_DATA_1 0x4 | ||
98 | #define PHY_DATA_1 0x20000 | ||
99 | #define PHY_DATA_0 0x00000 | ||
100 | #define MDCLKH 0x10000 | ||
101 | |||
102 | #define PHY_POWER_DOWN 0x800 | ||
103 | |||
104 | #define SROM_V41_CODE 0x14 | ||
105 | |||
106 | #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5); | ||
107 | |||
108 | /* Sten Check */ | ||
109 | #define DEVICE net_device | ||
110 | |||
111 | /* Structure/enum declaration ------------------------------- */ | ||
112 | struct tx_desc { | ||
113 | u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */ | ||
114 | char *tx_buf_ptr; /* Data for us */ | ||
115 | struct tx_desc *next_tx_desc; | ||
116 | } __attribute__(( aligned(32) )); | ||
117 | |||
118 | struct rx_desc { | ||
119 | u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */ | ||
120 | struct sk_buff *rx_skb_ptr; /* Data for us */ | ||
121 | struct rx_desc *next_rx_desc; | ||
122 | } __attribute__(( aligned(32) )); | ||
123 | |||
124 | struct uli526x_board_info { | ||
125 | u32 chip_id; /* Chip vendor/Device ID */ | ||
126 | struct DEVICE *next_dev; /* next device */ | ||
127 | struct pci_dev *pdev; /* PCI device */ | ||
128 | spinlock_t lock; | ||
129 | |||
130 | long ioaddr; /* I/O base address */ | ||
131 | u32 cr0_data; | ||
132 | u32 cr5_data; | ||
133 | u32 cr6_data; | ||
134 | u32 cr7_data; | ||
135 | u32 cr15_data; | ||
136 | |||
137 | /* pointer for memory physical address */ | ||
138 | dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */ | ||
139 | dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */ | ||
140 | dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */ | ||
141 | dma_addr_t first_tx_desc_dma; | ||
142 | dma_addr_t first_rx_desc_dma; | ||
143 | |||
144 | /* descriptor pointer */ | ||
145 | unsigned char *buf_pool_ptr; /* Tx buffer pool memory */ | ||
146 | unsigned char *buf_pool_start; /* Tx buffer pool align dword */ | ||
147 | unsigned char *desc_pool_ptr; /* descriptor pool memory */ | ||
148 | struct tx_desc *first_tx_desc; | ||
149 | struct tx_desc *tx_insert_ptr; | ||
150 | struct tx_desc *tx_remove_ptr; | ||
151 | struct rx_desc *first_rx_desc; | ||
152 | struct rx_desc *rx_insert_ptr; | ||
153 | struct rx_desc *rx_ready_ptr; /* packet come pointer */ | ||
154 | unsigned long tx_packet_cnt; /* transmitted packet count */ | ||
155 | unsigned long rx_avail_cnt; /* available rx descriptor count */ | ||
156 | unsigned long interval_rx_cnt; /* rx packet count a callback time */ | ||
157 | |||
158 | u16 dbug_cnt; | ||
159 | u16 NIC_capability; /* NIC media capability */ | ||
160 | u16 PHY_reg4; /* Saved Phyxcer register 4 value */ | ||
161 | |||
162 | u8 media_mode; /* user specify media mode */ | ||
163 | u8 op_mode; /* real work media mode */ | ||
164 | u8 phy_addr; | ||
165 | u8 link_failed; /* Ever link failed */ | ||
166 | u8 wait_reset; /* Hardware failed, need to reset */ | ||
167 | struct timer_list timer; | ||
168 | |||
169 | /* System defined statistic counter */ | ||
170 | struct net_device_stats stats; | ||
171 | |||
172 | /* Driver defined statistic counter */ | ||
173 | unsigned long tx_fifo_underrun; | ||
174 | unsigned long tx_loss_carrier; | ||
175 | unsigned long tx_no_carrier; | ||
176 | unsigned long tx_late_collision; | ||
177 | unsigned long tx_excessive_collision; | ||
178 | unsigned long tx_jabber_timeout; | ||
179 | unsigned long reset_count; | ||
180 | unsigned long reset_cr8; | ||
181 | unsigned long reset_fatal; | ||
182 | unsigned long reset_TXtimeout; | ||
183 | |||
184 | /* NIC SROM data */ | ||
185 | unsigned char srom[128]; | ||
186 | u8 init; | ||
187 | }; | ||
188 | |||
189 | enum uli526x_offsets { | ||
190 | DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20, | ||
191 | DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48, | ||
192 | DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70, | ||
193 | DCR15 = 0x78 | ||
194 | }; | ||
195 | |||
196 | enum uli526x_CR6_bits { | ||
197 | CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80, | ||
198 | CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, | ||
199 | CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000 | ||
200 | }; | ||
201 | |||
202 | /* Global variable declaration ----------------------------- */ | ||
203 | static int __devinitdata printed_version; | ||
204 | static char version[] __devinitdata = | ||
205 | KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version " | ||
206 | DRV_VERSION " (" DRV_RELDATE ")\n"; | ||
207 | |||
208 | static int uli526x_debug; | ||
209 | static unsigned char uli526x_media_mode = ULI526X_AUTO; | ||
210 | static u32 uli526x_cr6_user_set; | ||
211 | |||
212 | /* For module input parameter */ | ||
213 | static int debug; | ||
214 | static u32 cr6set; | ||
215 | static u32 m526x_id; | ||
216 | static unsigned char mode = 8; | ||
217 | |||
218 | /* function declaration ------------------------------------- */ | ||
219 | static int uli526x_open(struct DEVICE *); | ||
220 | static int uli526x_start_xmit(struct sk_buff *, struct DEVICE *); | ||
221 | static int uli526x_stop(struct DEVICE *); | ||
222 | static struct net_device_stats * uli526x_get_stats(struct DEVICE *); | ||
223 | static void uli526x_set_filter_mode(struct DEVICE *); | ||
224 | static struct ethtool_ops netdev_ethtool_ops; | ||
225 | static u16 read_srom_word(long ,int); | ||
226 | static irqreturn_t uli526x_interrupt(int , void *, struct pt_regs *); | ||
227 | static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long); | ||
228 | static void allocate_rx_buffer(struct uli526x_board_info *); | ||
229 | static void update_cr6(u32, unsigned long); | ||
230 | static void send_filter_frame(struct DEVICE * ,int); | ||
231 | static u16 phy_read(unsigned long, u8, u8, u32); | ||
232 | static u16 phy_readby_cr10(unsigned long, u8, u8); | ||
233 | static void phy_write(unsigned long, u8, u8, u16, u32); | ||
234 | static void phy_writeby_cr10(unsigned long, u8, u8, u16); | ||
235 | static void phy_write_1bit(unsigned long, u32, u32); | ||
236 | static u16 phy_read_1bit(unsigned long, u32); | ||
237 | static u8 uli526x_sense_speed(struct uli526x_board_info *); | ||
238 | static void uli526x_process_mode(struct uli526x_board_info *); | ||
239 | static void uli526x_timer(unsigned long); | ||
240 | static void uli526x_rx_packet(struct DEVICE *, struct uli526x_board_info *); | ||
241 | static void uli526x_free_tx_pkt(struct DEVICE *, struct uli526x_board_info *); | ||
242 | static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *); | ||
243 | static void uli526x_dynamic_reset(struct DEVICE *); | ||
244 | static void uli526x_free_rxbuffer(struct uli526x_board_info *); | ||
245 | static void uli526x_init(struct DEVICE *); | ||
246 | static void uli526x_set_phyxcer(struct uli526x_board_info *); | ||
247 | |||
248 | /* ULI526X network baord routine ---------------------------- */ | ||
249 | |||
250 | /* | ||
251 | * Search ULI526X board ,allocate space and register it | ||
252 | */ | ||
253 | |||
254 | static int __devinit uli526x_init_one (struct pci_dev *pdev, | ||
255 | const struct pci_device_id *ent) | ||
256 | { | ||
257 | struct uli526x_board_info *db; /* board information structure */ | ||
258 | struct net_device *dev; | ||
259 | int i, err; | ||
260 | u32 configval; | ||
261 | |||
262 | ULI526X_DBUG(0, "uli526x_init_one()", 0); | ||
263 | |||
264 | if (!printed_version++) | ||
265 | printk(version); | ||
266 | |||
267 | /* Init network device */ | ||
268 | dev = alloc_etherdev(sizeof(*db)); | ||
269 | if (dev == NULL) | ||
270 | return -ENOMEM; | ||
271 | SET_MODULE_OWNER(dev); | ||
272 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
273 | |||
274 | if (pci_set_dma_mask(pdev, 0xffffffff)) { | ||
275 | printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n"); | ||
276 | err = -ENODEV; | ||
277 | goto err_out_free; | ||
278 | } | ||
279 | |||
280 | /* Enable Master/IO access, Disable memory access */ | ||
281 | err = pci_enable_device(pdev); | ||
282 | if (err) | ||
283 | goto err_out_free; | ||
284 | |||
285 | if (!pci_resource_start(pdev, 0)) { | ||
286 | printk(KERN_ERR DRV_NAME ": I/O base is zero\n"); | ||
287 | err = -ENODEV; | ||
288 | goto err_out_disable; | ||
289 | } | ||
290 | |||
291 | if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) { | ||
292 | printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n"); | ||
293 | err = -ENODEV; | ||
294 | goto err_out_disable; | ||
295 | } | ||
296 | |||
297 | if (pci_request_regions(pdev, DRV_NAME)) { | ||
298 | printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n"); | ||
299 | err = -ENODEV; | ||
300 | goto err_out_disable; | ||
301 | } | ||
302 | |||
303 | //add by clearzhang 2004/7/8 | ||
304 | pci_read_config_dword(pdev,0x0,&configval); | ||
305 | m526x_id = configval; | ||
306 | if(configval == 0x526310b9) | ||
307 | { | ||
308 | //printk("is m5263\n"); | ||
309 | pci_read_config_dword(pdev,0x0c,&configval); | ||
310 | configval = ((configval & 0xffff00ff) | 0x8000); | ||
311 | pci_write_config_dword(pdev,0x0c,configval); | ||
312 | } | ||
313 | /* Init system & device */ | ||
314 | db = netdev_priv(dev); | ||
315 | |||
316 | /* Allocate Tx/Rx descriptor memory */ | ||
317 | db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr); | ||
318 | db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr); | ||
319 | |||
320 | db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; | ||
321 | db->first_tx_desc_dma = db->desc_pool_dma_ptr; | ||
322 | db->buf_pool_start = db->buf_pool_ptr; | ||
323 | db->buf_pool_dma_start = db->buf_pool_dma_ptr; | ||
324 | |||
325 | db->chip_id = ent->driver_data; | ||
326 | db->ioaddr = pci_resource_start(pdev, 0); | ||
327 | |||
328 | db->pdev = pdev; | ||
329 | db->init = 1; | ||
330 | |||
331 | dev->base_addr = db->ioaddr; | ||
332 | dev->irq = pdev->irq; | ||
333 | pci_set_drvdata(pdev, dev); | ||
334 | |||
335 | /* Register some necessary functions */ | ||
336 | dev->open = &uli526x_open; | ||
337 | dev->hard_start_xmit = &uli526x_start_xmit; | ||
338 | dev->stop = &uli526x_stop; | ||
339 | dev->get_stats = &uli526x_get_stats; | ||
340 | dev->set_multicast_list = &uli526x_set_filter_mode; | ||
341 | dev->ethtool_ops = &netdev_ethtool_ops; | ||
342 | spin_lock_init(&db->lock); | ||
343 | |||
344 | |||
345 | /* read 64 word srom data */ | ||
346 | for (i = 0; i < 64; i++) | ||
347 | ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); | ||
348 | |||
349 | /* Set Node address */ | ||
350 | if(((u16 *) db->srom)[0] == 0xffff) /* SROM absent, so read MAC address from ID Table */ | ||
351 | { | ||
352 | outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode | ||
353 | outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port | ||
354 | outl(0, db->ioaddr + DCR14); //Clear reset port | ||
355 | outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer | ||
356 | outl(0, db->ioaddr + DCR14); //Clear reset port | ||
357 | outl(0, db->ioaddr + DCR13); //Clear CR13 | ||
358 | outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port | ||
359 | //Read MAC address from CR14 | ||
360 | for (i = 0; i < 6; i++) | ||
361 | dev->dev_addr[i] = inl(db->ioaddr + DCR14); | ||
362 | //Read end | ||
363 | outl(0, db->ioaddr + DCR13); //Clear CR13 | ||
364 | outl(0, db->ioaddr + DCR0); //Clear CR0 | ||
365 | udelay(10); | ||
366 | } | ||
367 | else /*Exist SROM*/ | ||
368 | { | ||
369 | for (i = 0; i < 6; i++) | ||
370 | dev->dev_addr[i] = db->srom[20 + i]; | ||
371 | } | ||
372 | err = register_netdev (dev); | ||
373 | if (err) | ||
374 | goto err_out_res; | ||
375 | |||
376 | printk(KERN_INFO "%s: ULi M%04lx at pci%s,",dev->name,ent->driver_data >> 16,pci_name(pdev)); | ||
377 | |||
378 | for (i = 0; i < 6; i++) | ||
379 | printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]); | ||
380 | printk(", irq %d.\n", dev->irq); | ||
381 | |||
382 | pci_set_master(pdev); | ||
383 | |||
384 | return 0; | ||
385 | |||
386 | err_out_res: | ||
387 | pci_release_regions(pdev); | ||
388 | err_out_disable: | ||
389 | pci_disable_device(pdev); | ||
390 | err_out_free: | ||
391 | pci_set_drvdata(pdev, NULL); | ||
392 | free_netdev(dev); | ||
393 | |||
394 | return err; | ||
395 | } | ||
396 | |||
397 | |||
398 | static void __devexit uli526x_remove_one (struct pci_dev *pdev) | ||
399 | { | ||
400 | struct net_device *dev = pci_get_drvdata(pdev); | ||
401 | struct uli526x_board_info *db = netdev_priv(dev); | ||
402 | |||
403 | ULI526X_DBUG(0, "uli526x_remove_one()", 0); | ||
404 | |||
405 | if (dev) { | ||
406 | pci_free_consistent(db->pdev, sizeof(struct tx_desc) * | ||
407 | DESC_ALL_CNT + 0x20, db->desc_pool_ptr, | ||
408 | db->desc_pool_dma_ptr); | ||
409 | pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, | ||
410 | db->buf_pool_ptr, db->buf_pool_dma_ptr); | ||
411 | unregister_netdev(dev); | ||
412 | pci_release_regions(pdev); | ||
413 | free_netdev(dev); /* free board information */ | ||
414 | pci_set_drvdata(pdev, NULL); | ||
415 | } | ||
416 | |||
417 | ULI526X_DBUG(0, "uli526x_remove_one() exit", 0); | ||
418 | } | ||
419 | |||
420 | |||
421 | /* | ||
422 | * Open the interface. | ||
423 | * The interface is opened whenever "ifconfig" actives it. | ||
424 | */ | ||
425 | |||
426 | static int uli526x_open(struct DEVICE *dev) | ||
427 | { | ||
428 | int ret; | ||
429 | struct uli526x_board_info *db = netdev_priv(dev); | ||
430 | |||
431 | ULI526X_DBUG(0, "uli526x_open", 0); | ||
432 | |||
433 | ret = request_irq(dev->irq, &uli526x_interrupt, SA_SHIRQ, dev->name, dev); | ||
434 | if (ret) | ||
435 | return ret; | ||
436 | |||
437 | /* system variable init */ | ||
438 | db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set; | ||
439 | if(m526x_id == 0x526310b9) | ||
440 | { | ||
441 | //printk("is 5263\n"); | ||
442 | db->cr6_data = CR6_DEFAULT_A | uli526x_cr6_user_set; | ||
443 | } | ||
444 | db->tx_packet_cnt = 0; | ||
445 | db->rx_avail_cnt = 0; | ||
446 | db->link_failed = 1; | ||
447 | netif_carrier_off(dev); | ||
448 | db->wait_reset = 0; | ||
449 | |||
450 | db->NIC_capability = 0xf; /* All capability*/ | ||
451 | db->PHY_reg4 = 0x1e0; | ||
452 | |||
453 | /* CR6 operation mode decision */ | ||
454 | db->cr6_data |= ULI526X_TXTH_256; | ||
455 | db->cr0_data = CR0_DEFAULT; | ||
456 | |||
457 | /* Initilize ULI526X board */ | ||
458 | uli526x_init(dev); | ||
459 | |||
460 | /* Active System Interface */ | ||
461 | netif_wake_queue(dev); | ||
462 | |||
463 | /* set and active a timer process */ | ||
464 | init_timer(&db->timer); | ||
465 | db->timer.expires = ULI526X_TIMER_WUT + HZ * 2; | ||
466 | db->timer.data = (unsigned long)dev; | ||
467 | db->timer.function = &uli526x_timer; | ||
468 | add_timer(&db->timer); | ||
469 | |||
470 | return 0; | ||
471 | } | ||
472 | |||
473 | |||
474 | /* Initilize ULI526X board | ||
475 | * Reset ULI526X board | ||
476 | * Initilize TX/Rx descriptor chain structure | ||
477 | * Send the set-up frame | ||
478 | * Enable Tx/Rx machine | ||
479 | */ | ||
480 | |||
481 | static void uli526x_init(struct DEVICE *dev) | ||
482 | { | ||
483 | struct uli526x_board_info *db = netdev_priv(dev); | ||
484 | unsigned long ioaddr = db->ioaddr; | ||
485 | u8 phy_tmp; | ||
486 | u16 phy_value; | ||
487 | u16 phy_reg_reset; | ||
488 | |||
489 | ULI526X_DBUG(0, "uli526x_init()", 0); | ||
490 | |||
491 | /* Reset M526x MAC controller */ | ||
492 | outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */ | ||
493 | udelay(100); | ||
494 | outl(db->cr0_data, ioaddr + DCR0); | ||
495 | udelay(5); | ||
496 | |||
497 | /* Phy addr : In some boards,M5261/M5263 phy address != 1 */ | ||
498 | db->phy_addr = 1; | ||
499 | for(phy_tmp=0;phy_tmp<32;phy_tmp++) | ||
500 | { | ||
501 | phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add | ||
502 | if(phy_value != 0xffff&&phy_value!=0) | ||
503 | { | ||
504 | db->phy_addr = phy_tmp; | ||
505 | break; | ||
506 | } | ||
507 | } | ||
508 | if(phy_tmp == 32) | ||
509 | printk(KERN_WARNING "Can not find the phy address!!!"); | ||
510 | /* Parser SROM and media mode */ | ||
511 | db->media_mode = uli526x_media_mode; | ||
512 | |||
513 | //add by clearzhang 2004/7/8 | ||
514 | /* RESET Phyxcer Chip by GPR port bit 7 */ | ||
515 | //outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */ | ||
516 | //outl(0x0, ioaddr + DCR12); /* Clear RESET signal */ | ||
517 | |||
518 | /* Phyxcer capability setting */ | ||
519 | phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); | ||
520 | phy_reg_reset = (phy_reg_reset | 0x8000); | ||
521 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); | ||
522 | udelay(500); | ||
523 | |||
524 | /* Process Phyxcer Media Mode */ | ||
525 | uli526x_set_phyxcer(db); | ||
526 | |||
527 | /* Media Mode Process */ | ||
528 | if ( !(db->media_mode & ULI526X_AUTO) ) | ||
529 | db->op_mode = db->media_mode; /* Force Mode */ | ||
530 | |||
531 | /* Initiliaze Transmit/Receive decriptor and CR3/4 */ | ||
532 | uli526x_descriptor_init(db, ioaddr); | ||
533 | |||
534 | /* Init CR6 to program M526X operation */ | ||
535 | update_cr6(db->cr6_data, ioaddr); | ||
536 | |||
537 | /* Send setup frame */ | ||
538 | send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */ | ||
539 | |||
540 | /* Init CR7, interrupt active bit */ | ||
541 | db->cr7_data = CR7_DEFAULT; | ||
542 | outl(db->cr7_data, ioaddr + DCR7); | ||
543 | |||
544 | /* Init CR15, Tx jabber and Rx watchdog timer */ | ||
545 | outl(db->cr15_data, ioaddr + DCR15); | ||
546 | |||
547 | /* Enable ULI526X Tx/Rx function */ | ||
548 | db->cr6_data |= CR6_RXSC | CR6_TXSC; | ||
549 | update_cr6(db->cr6_data, ioaddr); | ||
550 | } | ||
551 | |||
552 | |||
553 | /* | ||
554 | * Hardware start transmission. | ||
555 | * Send a packet to media from the upper layer. | ||
556 | */ | ||
557 | |||
558 | static int uli526x_start_xmit(struct sk_buff *skb, struct DEVICE *dev) | ||
559 | { | ||
560 | struct uli526x_board_info *db = netdev_priv(dev); | ||
561 | struct tx_desc *txptr; | ||
562 | unsigned long flags; | ||
563 | |||
564 | ULI526X_DBUG(0, "uli526x_start_xmit", 0); | ||
565 | |||
566 | /* Resource flag check */ | ||
567 | netif_stop_queue(dev); | ||
568 | |||
569 | /* Too large packet check */ | ||
570 | if (skb->len > MAX_PACKET_SIZE) { | ||
571 | printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len); | ||
572 | dev_kfree_skb(skb); | ||
573 | return 0; | ||
574 | } | ||
575 | |||
576 | spin_lock_irqsave(&db->lock, flags); | ||
577 | |||
578 | /* No Tx resource check, it never happen nromally */ | ||
579 | if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) { | ||
580 | spin_unlock_irqrestore(&db->lock, flags); | ||
581 | printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt); | ||
582 | return 1; | ||
583 | } | ||
584 | |||
585 | /* Disable NIC interrupt */ | ||
586 | outl(0, dev->base_addr + DCR7); | ||
587 | |||
588 | /* transmit this packet */ | ||
589 | txptr = db->tx_insert_ptr; | ||
590 | memcpy(txptr->tx_buf_ptr, skb->data, skb->len); | ||
591 | txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len); | ||
592 | |||
593 | /* Point to next transmit free descriptor */ | ||
594 | db->tx_insert_ptr = txptr->next_tx_desc; | ||
595 | |||
596 | /* Transmit Packet Process */ | ||
597 | if ( (db->tx_packet_cnt < TX_DESC_CNT) ) { | ||
598 | txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */ | ||
599 | db->tx_packet_cnt++; /* Ready to send */ | ||
600 | outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ | ||
601 | dev->trans_start = jiffies; /* saved time stamp */ | ||
602 | } | ||
603 | |||
604 | /* Tx resource check */ | ||
605 | if ( db->tx_packet_cnt < TX_FREE_DESC_CNT ) | ||
606 | netif_wake_queue(dev); | ||
607 | |||
608 | /* Restore CR7 to enable interrupt */ | ||
609 | spin_unlock_irqrestore(&db->lock, flags); | ||
610 | outl(db->cr7_data, dev->base_addr + DCR7); | ||
611 | |||
612 | /* free this SKB */ | ||
613 | dev_kfree_skb(skb); | ||
614 | |||
615 | return 0; | ||
616 | } | ||
617 | |||
618 | |||
619 | /* | ||
620 | * Stop the interface. | ||
621 | * The interface is stopped when it is brought. | ||
622 | */ | ||
623 | |||
624 | static int uli526x_stop(struct DEVICE *dev) | ||
625 | { | ||
626 | struct uli526x_board_info *db = netdev_priv(dev); | ||
627 | unsigned long ioaddr = dev->base_addr; | ||
628 | |||
629 | ULI526X_DBUG(0, "uli526x_stop", 0); | ||
630 | |||
631 | /* disable system */ | ||
632 | netif_stop_queue(dev); | ||
633 | |||
634 | /* deleted timer */ | ||
635 | del_timer_sync(&db->timer); | ||
636 | |||
637 | /* Reset & stop ULI526X board */ | ||
638 | outl(ULI526X_RESET, ioaddr + DCR0); | ||
639 | udelay(5); | ||
640 | phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); | ||
641 | |||
642 | /* free interrupt */ | ||
643 | free_irq(dev->irq, dev); | ||
644 | |||
645 | /* free allocated rx buffer */ | ||
646 | uli526x_free_rxbuffer(db); | ||
647 | |||
648 | #if 0 | ||
649 | /* show statistic counter */ | ||
650 | printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n", | ||
651 | db->tx_fifo_underrun, db->tx_excessive_collision, | ||
652 | db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier, | ||
653 | db->tx_jabber_timeout, db->reset_count, db->reset_cr8, | ||
654 | db->reset_fatal, db->reset_TXtimeout); | ||
655 | #endif | ||
656 | |||
657 | return 0; | ||
658 | } | ||
659 | |||
660 | |||
661 | /* | ||
662 | * M5261/M5263 insterrupt handler | ||
663 | * receive the packet to upper layer, free the transmitted packet | ||
664 | */ | ||
665 | |||
666 | static irqreturn_t uli526x_interrupt(int irq, void *dev_id, struct pt_regs *regs) | ||
667 | { | ||
668 | struct DEVICE *dev = dev_id; | ||
669 | struct uli526x_board_info *db = netdev_priv(dev); | ||
670 | unsigned long ioaddr = dev->base_addr; | ||
671 | unsigned long flags; | ||
672 | |||
673 | //ULI526X_DBUG(0, "uli526x_interrupt()", 0); | ||
674 | |||
675 | if (!dev) { | ||
676 | ULI526X_DBUG(1, "uli526x_interrupt() without DEVICE arg", 0); | ||
677 | return IRQ_NONE; | ||
678 | } | ||
679 | |||
680 | //outl(0, ioaddr + DCR7); | ||
681 | spin_lock_irqsave(&db->lock, flags); | ||
682 | outl(0, ioaddr + DCR7); | ||
683 | |||
684 | /* Got ULI526X status */ | ||
685 | db->cr5_data = inl(ioaddr + DCR5); | ||
686 | outl(db->cr5_data, ioaddr + DCR5); | ||
687 | if ( !(db->cr5_data & 0x180c1) ) { | ||
688 | spin_unlock_irqrestore(&db->lock, flags); | ||
689 | outl(db->cr7_data, ioaddr + DCR7); | ||
690 | return IRQ_HANDLED; | ||
691 | } | ||
692 | |||
693 | /* Disable all interrupt in CR7 to solve the interrupt edge problem */ | ||
694 | //outl(0, ioaddr + DCR7); | ||
695 | |||
696 | /* Check system status */ | ||
697 | if (db->cr5_data & 0x2000) { | ||
698 | /* system bus error happen */ | ||
699 | ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data); | ||
700 | db->reset_fatal++; | ||
701 | db->wait_reset = 1; /* Need to RESET */ | ||
702 | spin_unlock_irqrestore(&db->lock, flags); | ||
703 | return IRQ_HANDLED; | ||
704 | } | ||
705 | |||
706 | /* Received the coming packet */ | ||
707 | if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) | ||
708 | uli526x_rx_packet(dev, db); | ||
709 | |||
710 | /* reallocate rx descriptor buffer */ | ||
711 | if (db->rx_avail_cnt<RX_DESC_CNT) | ||
712 | allocate_rx_buffer(db); | ||
713 | |||
714 | /* Free the transmitted descriptor */ | ||
715 | if ( db->cr5_data & 0x01) | ||
716 | uli526x_free_tx_pkt(dev, db); | ||
717 | |||
718 | /* Restore CR7 to enable interrupt mask */ | ||
719 | outl(db->cr7_data, ioaddr + DCR7); | ||
720 | |||
721 | spin_unlock_irqrestore(&db->lock, flags); | ||
722 | return IRQ_HANDLED; | ||
723 | } | ||
724 | |||
725 | |||
726 | /* | ||
727 | * Free TX resource after TX complete | ||
728 | */ | ||
729 | |||
730 | static void uli526x_free_tx_pkt(struct DEVICE *dev, struct uli526x_board_info * db) | ||
731 | { | ||
732 | struct tx_desc *txptr; | ||
733 | // unsigned long ioaddr = dev->base_addr; | ||
734 | u32 tdes0; | ||
735 | |||
736 | txptr = db->tx_remove_ptr; | ||
737 | while(db->tx_packet_cnt) { | ||
738 | tdes0 = le32_to_cpu(txptr->tdes0); | ||
739 | /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ | ||
740 | if (tdes0 & 0x80000000) | ||
741 | break; | ||
742 | |||
743 | /* A packet sent completed */ | ||
744 | db->tx_packet_cnt--; | ||
745 | db->stats.tx_packets++; | ||
746 | |||
747 | /* Transmit statistic counter */ | ||
748 | if ( tdes0 != 0x7fffffff ) { | ||
749 | /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */ | ||
750 | db->stats.collisions += (tdes0 >> 3) & 0xf; | ||
751 | db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; | ||
752 | if (tdes0 & TDES0_ERR_MASK) { | ||
753 | db->stats.tx_errors++; | ||
754 | if (tdes0 & 0x0002) { /* UnderRun */ | ||
755 | db->tx_fifo_underrun++; | ||
756 | if ( !(db->cr6_data & CR6_SFT) ) { | ||
757 | db->cr6_data = db->cr6_data | CR6_SFT; | ||
758 | update_cr6(db->cr6_data, db->ioaddr); | ||
759 | } | ||
760 | } | ||
761 | if (tdes0 & 0x0100) | ||
762 | db->tx_excessive_collision++; | ||
763 | if (tdes0 & 0x0200) | ||
764 | db->tx_late_collision++; | ||
765 | if (tdes0 & 0x0400) | ||
766 | db->tx_no_carrier++; | ||
767 | if (tdes0 & 0x0800) | ||
768 | db->tx_loss_carrier++; | ||
769 | if (tdes0 & 0x4000) | ||
770 | db->tx_jabber_timeout++; | ||
771 | } | ||
772 | } | ||
773 | |||
774 | txptr = txptr->next_tx_desc; | ||
775 | }/* End of while */ | ||
776 | |||
777 | /* Update TX remove pointer to next */ | ||
778 | db->tx_remove_ptr = txptr; | ||
779 | |||
780 | /* Resource available check */ | ||
781 | if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT ) | ||
782 | netif_wake_queue(dev); /* Active upper layer, send again */ | ||
783 | } | ||
784 | |||
785 | |||
786 | /* | ||
787 | * Receive the come packet and pass to upper layer | ||
788 | */ | ||
789 | |||
790 | static void uli526x_rx_packet(struct DEVICE *dev, struct uli526x_board_info * db) | ||
791 | { | ||
792 | struct rx_desc *rxptr; | ||
793 | struct sk_buff *skb; | ||
794 | int rxlen; | ||
795 | u32 rdes0; | ||
796 | |||
797 | rxptr = db->rx_ready_ptr; | ||
798 | |||
799 | while(db->rx_avail_cnt) { | ||
800 | rdes0 = le32_to_cpu(rxptr->rdes0); | ||
801 | if (rdes0 & 0x80000000) /* packet owner check */ | ||
802 | { | ||
803 | break; | ||
804 | } | ||
805 | |||
806 | db->rx_avail_cnt--; | ||
807 | db->interval_rx_cnt++; | ||
808 | |||
809 | pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | ||
810 | if ( (rdes0 & 0x300) != 0x300) { | ||
811 | /* A packet without First/Last flag */ | ||
812 | /* reuse this SKB */ | ||
813 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | ||
814 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | ||
815 | } else { | ||
816 | /* A packet with First/Last flag */ | ||
817 | rxlen = ( (rdes0 >> 16) & 0x3fff) - 4; | ||
818 | |||
819 | /* error summary bit check */ | ||
820 | if (rdes0 & 0x8000) { | ||
821 | /* This is a error packet */ | ||
822 | //printk(DRV_NAME ": rdes0: %lx\n", rdes0); | ||
823 | db->stats.rx_errors++; | ||
824 | if (rdes0 & 1) | ||
825 | db->stats.rx_fifo_errors++; | ||
826 | if (rdes0 & 2) | ||
827 | db->stats.rx_crc_errors++; | ||
828 | if (rdes0 & 0x80) | ||
829 | db->stats.rx_length_errors++; | ||
830 | } | ||
831 | |||
832 | if ( !(rdes0 & 0x8000) || | ||
833 | ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { | ||
834 | skb = rxptr->rx_skb_ptr; | ||
835 | |||
836 | /* Good packet, send to upper layer */ | ||
837 | /* Shorst packet used new SKB */ | ||
838 | if ( (rxlen < RX_COPY_SIZE) && | ||
839 | ( (skb = dev_alloc_skb(rxlen + 2) ) | ||
840 | != NULL) ) { | ||
841 | /* size less than COPY_SIZE, allocate a rxlen SKB */ | ||
842 | skb->dev = dev; | ||
843 | skb_reserve(skb, 2); /* 16byte align */ | ||
844 | memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen); | ||
845 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | ||
846 | } else { | ||
847 | skb->dev = dev; | ||
848 | skb_put(skb, rxlen); | ||
849 | } | ||
850 | skb->protocol = eth_type_trans(skb, dev); | ||
851 | netif_rx(skb); | ||
852 | dev->last_rx = jiffies; | ||
853 | db->stats.rx_packets++; | ||
854 | db->stats.rx_bytes += rxlen; | ||
855 | |||
856 | } else { | ||
857 | /* Reuse SKB buffer when the packet is error */ | ||
858 | ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0); | ||
859 | uli526x_reuse_skb(db, rxptr->rx_skb_ptr); | ||
860 | } | ||
861 | } | ||
862 | |||
863 | rxptr = rxptr->next_rx_desc; | ||
864 | } | ||
865 | |||
866 | db->rx_ready_ptr = rxptr; | ||
867 | } | ||
868 | |||
869 | |||
870 | /* | ||
871 | * Get statistics from driver. | ||
872 | */ | ||
873 | |||
874 | static struct net_device_stats * uli526x_get_stats(struct DEVICE *dev) | ||
875 | { | ||
876 | struct uli526x_board_info *db = netdev_priv(dev); | ||
877 | |||
878 | ULI526X_DBUG(0, "uli526x_get_stats", 0); | ||
879 | return &db->stats; | ||
880 | } | ||
881 | |||
882 | |||
883 | /* | ||
884 | * Set ULI526X multicast address | ||
885 | */ | ||
886 | |||
887 | static void uli526x_set_filter_mode(struct DEVICE * dev) | ||
888 | { | ||
889 | struct uli526x_board_info *db = dev->priv; | ||
890 | unsigned long flags; | ||
891 | |||
892 | ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0); | ||
893 | spin_lock_irqsave(&db->lock, flags); | ||
894 | |||
895 | if (dev->flags & IFF_PROMISC) { | ||
896 | ULI526X_DBUG(0, "Enable PROM Mode", 0); | ||
897 | db->cr6_data |= CR6_PM | CR6_PBF; | ||
898 | update_cr6(db->cr6_data, db->ioaddr); | ||
899 | spin_unlock_irqrestore(&db->lock, flags); | ||
900 | return; | ||
901 | } | ||
902 | |||
903 | if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) { | ||
904 | ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count); | ||
905 | db->cr6_data &= ~(CR6_PM | CR6_PBF); | ||
906 | db->cr6_data |= CR6_PAM; | ||
907 | spin_unlock_irqrestore(&db->lock, flags); | ||
908 | return; | ||
909 | } | ||
910 | |||
911 | ULI526X_DBUG(0, "Set multicast address", dev->mc_count); | ||
912 | send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */ | ||
913 | spin_unlock_irqrestore(&db->lock, flags); | ||
914 | } | ||
915 | |||
916 | static void | ||
917 | ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd) | ||
918 | { | ||
919 | //struct e1000_hw *hw = &adapter->hw; | ||
920 | |||
921 | { | ||
922 | |||
923 | ecmd->supported = (SUPPORTED_10baseT_Half | | ||
924 | SUPPORTED_10baseT_Full | | ||
925 | SUPPORTED_100baseT_Half | | ||
926 | SUPPORTED_100baseT_Full | | ||
927 | SUPPORTED_Autoneg | | ||
928 | SUPPORTED_MII); | ||
929 | |||
930 | ecmd->advertising = (ADVERTISED_10baseT_Half | | ||
931 | ADVERTISED_10baseT_Full | | ||
932 | ADVERTISED_100baseT_Half | | ||
933 | ADVERTISED_100baseT_Full | | ||
934 | ADVERTISED_Autoneg | | ||
935 | ADVERTISED_MII); | ||
936 | |||
937 | |||
938 | ecmd->port = PORT_MII; | ||
939 | ecmd->phy_address = db->phy_addr; | ||
940 | |||
941 | ecmd->transceiver = XCVR_EXTERNAL; | ||
942 | |||
943 | |||
944 | } | ||
945 | |||
946 | |||
947 | ecmd->speed = 10; | ||
948 | ecmd->duplex = DUPLEX_HALF; | ||
949 | |||
950 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) | ||
951 | { | ||
952 | ecmd->speed = 100; | ||
953 | } | ||
954 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | ||
955 | { | ||
956 | ecmd->duplex = DUPLEX_FULL; | ||
957 | } | ||
958 | if(db->link_failed) | ||
959 | { | ||
960 | ecmd->speed = -1; | ||
961 | ecmd->duplex = -1; | ||
962 | } | ||
963 | |||
964 | if (db->media_mode & ULI526X_AUTO) | ||
965 | { | ||
966 | ecmd->autoneg = AUTONEG_ENABLE; | ||
967 | } | ||
968 | |||
969 | |||
970 | } | ||
971 | |||
972 | static void netdev_get_drvinfo(struct net_device *dev, | ||
973 | struct ethtool_drvinfo *info) | ||
974 | { | ||
975 | struct uli526x_board_info *np = netdev_priv(dev); | ||
976 | |||
977 | strcpy(info->driver, DRV_NAME); | ||
978 | strcpy(info->version, DRV_VERSION); | ||
979 | if (np->pdev) | ||
980 | strcpy(info->bus_info, pci_name(np->pdev)); | ||
981 | else | ||
982 | sprintf(info->bus_info, "EISA 0x%lx %d", | ||
983 | dev->base_addr, dev->irq); | ||
984 | } | ||
985 | |||
986 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { | ||
987 | struct uli526x_board_info *np = netdev_priv(dev); | ||
988 | |||
989 | ULi_ethtool_gset(np, cmd); | ||
990 | |||
991 | return 0; | ||
992 | } | ||
993 | |||
994 | static u32 netdev_get_link(struct net_device *dev) { | ||
995 | struct uli526x_board_info *np = netdev_priv(dev); | ||
996 | |||
997 | if(np->link_failed) | ||
998 | return 0; | ||
999 | else | ||
1000 | return 1; | ||
1001 | } | ||
1002 | |||
1003 | static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | ||
1004 | { | ||
1005 | wol->supported = WAKE_PHY | WAKE_MAGIC; | ||
1006 | wol->wolopts = 0; | ||
1007 | } | ||
1008 | |||
1009 | static struct ethtool_ops netdev_ethtool_ops = { | ||
1010 | .get_drvinfo = netdev_get_drvinfo, | ||
1011 | .get_settings = netdev_get_settings, | ||
1012 | .get_link = netdev_get_link, | ||
1013 | .get_wol = uli526x_get_wol, | ||
1014 | }; | ||
1015 | |||
1016 | /* | ||
1017 | * A periodic timer routine | ||
1018 | * Dynamic media sense, allocate Rx buffer... | ||
1019 | */ | ||
1020 | |||
1021 | static void uli526x_timer(unsigned long data) | ||
1022 | { | ||
1023 | u32 tmp_cr8; | ||
1024 | unsigned char tmp_cr12=0; | ||
1025 | struct DEVICE *dev = (struct DEVICE *) data; | ||
1026 | struct uli526x_board_info *db = netdev_priv(dev); | ||
1027 | unsigned long flags; | ||
1028 | u8 TmpSpeed=10; | ||
1029 | |||
1030 | //ULI526X_DBUG(0, "uli526x_timer()", 0); | ||
1031 | spin_lock_irqsave(&db->lock, flags); | ||
1032 | |||
1033 | |||
1034 | /* Dynamic reset ULI526X : system error or transmit time-out */ | ||
1035 | tmp_cr8 = inl(db->ioaddr + DCR8); | ||
1036 | if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { | ||
1037 | db->reset_cr8++; | ||
1038 | db->wait_reset = 1; | ||
1039 | } | ||
1040 | db->interval_rx_cnt = 0; | ||
1041 | |||
1042 | /* TX polling kick monitor */ | ||
1043 | if ( db->tx_packet_cnt && | ||
1044 | time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) { | ||
1045 | outl(0x1, dev->base_addr + DCR1); // Tx polling again | ||
1046 | |||
1047 | // TX Timeout | ||
1048 | if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) { | ||
1049 | db->reset_TXtimeout++; | ||
1050 | db->wait_reset = 1; | ||
1051 | printk( "%s: Tx timeout - resetting\n", | ||
1052 | dev->name); | ||
1053 | } | ||
1054 | } | ||
1055 | |||
1056 | if (db->wait_reset) { | ||
1057 | ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); | ||
1058 | db->reset_count++; | ||
1059 | uli526x_dynamic_reset(dev); | ||
1060 | db->timer.expires = ULI526X_TIMER_WUT; | ||
1061 | add_timer(&db->timer); | ||
1062 | spin_unlock_irqrestore(&db->lock, flags); | ||
1063 | return; | ||
1064 | } | ||
1065 | |||
1066 | /* Link status check, Dynamic media type change */ | ||
1067 | if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0) | ||
1068 | tmp_cr12 = 3; | ||
1069 | |||
1070 | if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { | ||
1071 | /* Link Failed */ | ||
1072 | ULI526X_DBUG(0, "Link Failed", tmp_cr12); | ||
1073 | netif_carrier_off(dev); | ||
1074 | printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name); | ||
1075 | db->link_failed = 1; | ||
1076 | |||
1077 | /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */ | ||
1078 | /* AUTO don't need */ | ||
1079 | if ( !(db->media_mode & 0x8) ) | ||
1080 | phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); | ||
1081 | |||
1082 | /* AUTO mode, if INT phyxcer link failed, select EXT device */ | ||
1083 | if (db->media_mode & ULI526X_AUTO) { | ||
1084 | db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ | ||
1085 | update_cr6(db->cr6_data, db->ioaddr); | ||
1086 | } | ||
1087 | } else | ||
1088 | if ((tmp_cr12 & 0x3) && db->link_failed) { | ||
1089 | ULI526X_DBUG(0, "Link link OK", tmp_cr12); | ||
1090 | db->link_failed = 0; | ||
1091 | |||
1092 | /* Auto Sense Speed */ | ||
1093 | if ( (db->media_mode & ULI526X_AUTO) && | ||
1094 | uli526x_sense_speed(db) ) | ||
1095 | db->link_failed = 1; | ||
1096 | uli526x_process_mode(db); | ||
1097 | |||
1098 | if(db->link_failed==0) | ||
1099 | { | ||
1100 | if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD) | ||
1101 | { | ||
1102 | TmpSpeed = 100; | ||
1103 | } | ||
1104 | if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD) | ||
1105 | { | ||
1106 | printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed); | ||
1107 | } | ||
1108 | else | ||
1109 | { | ||
1110 | printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed); | ||
1111 | } | ||
1112 | netif_carrier_on(dev); | ||
1113 | } | ||
1114 | /* SHOW_MEDIA_TYPE(db->op_mode); */ | ||
1115 | } | ||
1116 | else if(!(tmp_cr12 & 0x3) && db->link_failed) | ||
1117 | { | ||
1118 | if(db->init==1) | ||
1119 | { | ||
1120 | printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name); | ||
1121 | netif_carrier_off(dev); | ||
1122 | } | ||
1123 | } | ||
1124 | db->init=0; | ||
1125 | |||
1126 | /* Timer active again */ | ||
1127 | db->timer.expires = ULI526X_TIMER_WUT; | ||
1128 | add_timer(&db->timer); | ||
1129 | spin_unlock_irqrestore(&db->lock, flags); | ||
1130 | } | ||
1131 | |||
1132 | |||
1133 | /* | ||
1134 | * Dynamic reset the ULI526X board | ||
1135 | * Stop ULI526X board | ||
1136 | * Free Tx/Rx allocated memory | ||
1137 | * Reset ULI526X board | ||
1138 | * Re-initilize ULI526X board | ||
1139 | */ | ||
1140 | |||
1141 | static void uli526x_dynamic_reset(struct DEVICE *dev) | ||
1142 | { | ||
1143 | struct uli526x_board_info *db = netdev_priv(dev); | ||
1144 | |||
1145 | ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0); | ||
1146 | |||
1147 | /* Sopt MAC controller */ | ||
1148 | db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ | ||
1149 | update_cr6(db->cr6_data, dev->base_addr); | ||
1150 | outl(0, dev->base_addr + DCR7); /* Disable Interrupt */ | ||
1151 | outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5); | ||
1152 | |||
1153 | /* Disable upper layer interface */ | ||
1154 | netif_stop_queue(dev); | ||
1155 | |||
1156 | /* Free Rx Allocate buffer */ | ||
1157 | uli526x_free_rxbuffer(db); | ||
1158 | |||
1159 | /* system variable init */ | ||
1160 | db->tx_packet_cnt = 0; | ||
1161 | db->rx_avail_cnt = 0; | ||
1162 | db->link_failed = 1; | ||
1163 | db->init=1; | ||
1164 | db->wait_reset = 0; | ||
1165 | |||
1166 | /* Re-initilize ULI526X board */ | ||
1167 | uli526x_init(dev); | ||
1168 | |||
1169 | /* Restart upper layer interface */ | ||
1170 | netif_wake_queue(dev); | ||
1171 | } | ||
1172 | |||
1173 | |||
1174 | /* | ||
1175 | * free all allocated rx buffer | ||
1176 | */ | ||
1177 | |||
1178 | static void uli526x_free_rxbuffer(struct uli526x_board_info * db) | ||
1179 | { | ||
1180 | ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0); | ||
1181 | |||
1182 | /* free allocated rx buffer */ | ||
1183 | while (db->rx_avail_cnt) { | ||
1184 | dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); | ||
1185 | db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; | ||
1186 | db->rx_avail_cnt--; | ||
1187 | } | ||
1188 | } | ||
1189 | |||
1190 | |||
1191 | /* | ||
1192 | * Reuse the SK buffer | ||
1193 | */ | ||
1194 | |||
1195 | static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb) | ||
1196 | { | ||
1197 | struct rx_desc *rxptr = db->rx_insert_ptr; | ||
1198 | |||
1199 | if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) { | ||
1200 | rxptr->rx_skb_ptr = skb; | ||
1201 | rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); | ||
1202 | wmb(); | ||
1203 | rxptr->rdes0 = cpu_to_le32(0x80000000); | ||
1204 | db->rx_avail_cnt++; | ||
1205 | db->rx_insert_ptr = rxptr->next_rx_desc; | ||
1206 | } else | ||
1207 | ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); | ||
1208 | } | ||
1209 | |||
1210 | |||
1211 | /* | ||
1212 | * Initialize transmit/Receive descriptor | ||
1213 | * Using Chain structure, and allocate Tx/Rx buffer | ||
1214 | */ | ||
1215 | |||
1216 | static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr) | ||
1217 | { | ||
1218 | struct tx_desc *tmp_tx; | ||
1219 | struct rx_desc *tmp_rx; | ||
1220 | unsigned char *tmp_buf; | ||
1221 | dma_addr_t tmp_tx_dma, tmp_rx_dma; | ||
1222 | dma_addr_t tmp_buf_dma; | ||
1223 | int i; | ||
1224 | |||
1225 | ULI526X_DBUG(0, "uli526x_descriptor_init()", 0); | ||
1226 | |||
1227 | /* tx descriptor start pointer */ | ||
1228 | db->tx_insert_ptr = db->first_tx_desc; | ||
1229 | db->tx_remove_ptr = db->first_tx_desc; | ||
1230 | outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ | ||
1231 | |||
1232 | /* rx descriptor start pointer */ | ||
1233 | db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; | ||
1234 | db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; | ||
1235 | db->rx_insert_ptr = db->first_rx_desc; | ||
1236 | db->rx_ready_ptr = db->first_rx_desc; | ||
1237 | outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ | ||
1238 | |||
1239 | /* Init Transmit chain */ | ||
1240 | tmp_buf = db->buf_pool_start; | ||
1241 | tmp_buf_dma = db->buf_pool_dma_start; | ||
1242 | tmp_tx_dma = db->first_tx_desc_dma; | ||
1243 | for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { | ||
1244 | tmp_tx->tx_buf_ptr = tmp_buf; | ||
1245 | tmp_tx->tdes0 = cpu_to_le32(0); | ||
1246 | tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */ | ||
1247 | tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma); | ||
1248 | tmp_tx_dma += sizeof(struct tx_desc); | ||
1249 | tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma); | ||
1250 | tmp_tx->next_tx_desc = tmp_tx + 1; | ||
1251 | tmp_buf = tmp_buf + TX_BUF_ALLOC; | ||
1252 | tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC; | ||
1253 | } | ||
1254 | (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); | ||
1255 | tmp_tx->next_tx_desc = db->first_tx_desc; | ||
1256 | |||
1257 | /* Init Receive descriptor chain */ | ||
1258 | tmp_rx_dma=db->first_rx_desc_dma; | ||
1259 | for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { | ||
1260 | tmp_rx->rdes0 = cpu_to_le32(0); | ||
1261 | tmp_rx->rdes1 = cpu_to_le32(0x01000600); | ||
1262 | tmp_rx_dma += sizeof(struct rx_desc); | ||
1263 | tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma); | ||
1264 | tmp_rx->next_rx_desc = tmp_rx + 1; | ||
1265 | } | ||
1266 | (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); | ||
1267 | tmp_rx->next_rx_desc = db->first_rx_desc; | ||
1268 | |||
1269 | /* pre-allocate Rx buffer */ | ||
1270 | allocate_rx_buffer(db); | ||
1271 | } | ||
1272 | |||
1273 | |||
1274 | /* | ||
1275 | * Update CR6 value | ||
1276 | * Firstly stop ULI526X , then written value and start | ||
1277 | */ | ||
1278 | |||
1279 | static void update_cr6(u32 cr6_data, unsigned long ioaddr) | ||
1280 | { | ||
1281 | |||
1282 | outl(cr6_data, ioaddr + DCR6); | ||
1283 | udelay(5); | ||
1284 | } | ||
1285 | |||
1286 | |||
1287 | /* | ||
1288 | * Send a setup frame for M5261/M5263 | ||
1289 | * This setup frame initilize ULI526X address filter mode | ||
1290 | */ | ||
1291 | |||
1292 | static void send_filter_frame(struct DEVICE *dev, int mc_cnt) | ||
1293 | { | ||
1294 | struct uli526x_board_info *db = netdev_priv(dev); | ||
1295 | struct dev_mc_list *mcptr; | ||
1296 | struct tx_desc *txptr; | ||
1297 | u16 * addrptr; | ||
1298 | u32 * suptr; | ||
1299 | int i; | ||
1300 | |||
1301 | ULI526X_DBUG(0, "send_filter_frame()", 0); | ||
1302 | |||
1303 | txptr = db->tx_insert_ptr; | ||
1304 | suptr = (u32 *) txptr->tx_buf_ptr; | ||
1305 | |||
1306 | /* Node address */ | ||
1307 | addrptr = (u16 *) dev->dev_addr; | ||
1308 | *suptr++ = addrptr[0]; | ||
1309 | *suptr++ = addrptr[1]; | ||
1310 | *suptr++ = addrptr[2]; | ||
1311 | |||
1312 | /* broadcast address */ | ||
1313 | *suptr++ = 0xffff; | ||
1314 | *suptr++ = 0xffff; | ||
1315 | *suptr++ = 0xffff; | ||
1316 | |||
1317 | /* fit the multicast address */ | ||
1318 | for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | ||
1319 | addrptr = (u16 *) mcptr->dmi_addr; | ||
1320 | *suptr++ = addrptr[0]; | ||
1321 | *suptr++ = addrptr[1]; | ||
1322 | *suptr++ = addrptr[2]; | ||
1323 | } | ||
1324 | |||
1325 | for (; i<14; i++) { | ||
1326 | *suptr++ = 0xffff; | ||
1327 | *suptr++ = 0xffff; | ||
1328 | *suptr++ = 0xffff; | ||
1329 | } | ||
1330 | |||
1331 | /* prepare the setup frame */ | ||
1332 | db->tx_insert_ptr = txptr->next_tx_desc; | ||
1333 | txptr->tdes1 = cpu_to_le32(0x890000c0); | ||
1334 | |||
1335 | /* Resource Check and Send the setup packet */ | ||
1336 | if (db->tx_packet_cnt < TX_DESC_CNT) { | ||
1337 | /* Resource Empty */ | ||
1338 | db->tx_packet_cnt++; | ||
1339 | txptr->tdes0 = cpu_to_le32(0x80000000); | ||
1340 | update_cr6(db->cr6_data | 0x2000, dev->base_addr); | ||
1341 | outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */ | ||
1342 | update_cr6(db->cr6_data, dev->base_addr); | ||
1343 | dev->trans_start = jiffies; | ||
1344 | } else | ||
1345 | printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n"); | ||
1346 | } | ||
1347 | |||
1348 | |||
1349 | /* | ||
1350 | * Allocate rx buffer, | ||
1351 | * As possible as allocate maxiumn Rx buffer | ||
1352 | */ | ||
1353 | |||
1354 | static void allocate_rx_buffer(struct uli526x_board_info *db) | ||
1355 | { | ||
1356 | struct rx_desc *rxptr; | ||
1357 | struct sk_buff *skb; | ||
1358 | |||
1359 | rxptr = db->rx_insert_ptr; | ||
1360 | |||
1361 | while(db->rx_avail_cnt < RX_DESC_CNT) { | ||
1362 | if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL ) | ||
1363 | break; | ||
1364 | rxptr->rx_skb_ptr = skb; /* FIXME (?) */ | ||
1365 | rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) ); | ||
1366 | wmb(); | ||
1367 | rxptr->rdes0 = cpu_to_le32(0x80000000); | ||
1368 | rxptr = rxptr->next_rx_desc; | ||
1369 | db->rx_avail_cnt++; | ||
1370 | } | ||
1371 | |||
1372 | db->rx_insert_ptr = rxptr; | ||
1373 | } | ||
1374 | |||
1375 | |||
1376 | /* | ||
1377 | * Read one word data from the serial ROM | ||
1378 | */ | ||
1379 | |||
1380 | static u16 read_srom_word(long ioaddr, int offset) | ||
1381 | { | ||
1382 | int i; | ||
1383 | u16 srom_data = 0; | ||
1384 | long cr9_ioaddr = ioaddr + DCR9; | ||
1385 | |||
1386 | outl(CR9_SROM_READ, cr9_ioaddr); | ||
1387 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | ||
1388 | |||
1389 | /* Send the Read Command 110b */ | ||
1390 | SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); | ||
1391 | SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr); | ||
1392 | SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr); | ||
1393 | |||
1394 | /* Send the offset */ | ||
1395 | for (i = 5; i >= 0; i--) { | ||
1396 | srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0; | ||
1397 | SROM_CLK_WRITE(srom_data, cr9_ioaddr); | ||
1398 | } | ||
1399 | |||
1400 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | ||
1401 | |||
1402 | for (i = 16; i > 0; i--) { | ||
1403 | outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr); | ||
1404 | udelay(5); | ||
1405 | srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0); | ||
1406 | outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr); | ||
1407 | udelay(5); | ||
1408 | } | ||
1409 | |||
1410 | outl(CR9_SROM_READ, cr9_ioaddr); | ||
1411 | return srom_data; | ||
1412 | } | ||
1413 | |||
1414 | |||
1415 | /* | ||
1416 | * Auto sense the media mode | ||
1417 | */ | ||
1418 | |||
1419 | static u8 uli526x_sense_speed(struct uli526x_board_info * db) | ||
1420 | { | ||
1421 | u8 ErrFlag = 0; | ||
1422 | u16 phy_mode; | ||
1423 | |||
1424 | phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); | ||
1425 | phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); | ||
1426 | |||
1427 | if ( (phy_mode & 0x24) == 0x24 ) { | ||
1428 | |||
1429 | phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7); | ||
1430 | if(phy_mode&0x8000) | ||
1431 | phy_mode = 0x8000; | ||
1432 | else if(phy_mode&0x4000) | ||
1433 | phy_mode = 0x4000; | ||
1434 | else if(phy_mode&0x2000) | ||
1435 | phy_mode = 0x2000; | ||
1436 | else | ||
1437 | phy_mode = 0x1000; | ||
1438 | |||
1439 | /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */ | ||
1440 | switch (phy_mode) { | ||
1441 | case 0x1000: db->op_mode = ULI526X_10MHF; break; | ||
1442 | case 0x2000: db->op_mode = ULI526X_10MFD; break; | ||
1443 | case 0x4000: db->op_mode = ULI526X_100MHF; break; | ||
1444 | case 0x8000: db->op_mode = ULI526X_100MFD; break; | ||
1445 | default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break; | ||
1446 | } | ||
1447 | } else { | ||
1448 | db->op_mode = ULI526X_10MHF; | ||
1449 | ULI526X_DBUG(0, "Link Failed :", phy_mode); | ||
1450 | ErrFlag = 1; | ||
1451 | } | ||
1452 | |||
1453 | return ErrFlag; | ||
1454 | } | ||
1455 | |||
1456 | |||
1457 | /* | ||
1458 | * Set 10/100 phyxcer capability | ||
1459 | * AUTO mode : phyxcer register4 is NIC capability | ||
1460 | * Force mode: phyxcer register4 is the force media | ||
1461 | */ | ||
1462 | |||
1463 | static void uli526x_set_phyxcer(struct uli526x_board_info *db) | ||
1464 | { | ||
1465 | u16 phy_reg; | ||
1466 | |||
1467 | /* Phyxcer capability setting */ | ||
1468 | phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; | ||
1469 | |||
1470 | if (db->media_mode & ULI526X_AUTO) { | ||
1471 | /* AUTO Mode */ | ||
1472 | phy_reg |= db->PHY_reg4; | ||
1473 | } else { | ||
1474 | /* Force Mode */ | ||
1475 | switch(db->media_mode) { | ||
1476 | case ULI526X_10MHF: phy_reg |= 0x20; break; | ||
1477 | case ULI526X_10MFD: phy_reg |= 0x40; break; | ||
1478 | case ULI526X_100MHF: phy_reg |= 0x80; break; | ||
1479 | case ULI526X_100MFD: phy_reg |= 0x100; break; | ||
1480 | } | ||
1481 | |||
1482 | } | ||
1483 | |||
1484 | /* Write new capability to Phyxcer Reg4 */ | ||
1485 | if ( !(phy_reg & 0x01e0)) { | ||
1486 | phy_reg|=db->PHY_reg4; | ||
1487 | db->media_mode|=ULI526X_AUTO; | ||
1488 | } | ||
1489 | phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); | ||
1490 | |||
1491 | /* Restart Auto-Negotiation */ | ||
1492 | phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); | ||
1493 | udelay(50); | ||
1494 | } | ||
1495 | |||
1496 | |||
1497 | /* | ||
1498 | * Process op-mode | ||
1499 | AUTO mode : PHY controller in Auto-negotiation Mode | ||
1500 | * Force mode: PHY controller in force mode with HUB | ||
1501 | * N-way force capability with SWITCH | ||
1502 | */ | ||
1503 | |||
1504 | static void uli526x_process_mode(struct uli526x_board_info *db) | ||
1505 | { | ||
1506 | u16 phy_reg; | ||
1507 | |||
1508 | /* Full Duplex Mode Check */ | ||
1509 | if (db->op_mode & 0x4) | ||
1510 | db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ | ||
1511 | else | ||
1512 | db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ | ||
1513 | |||
1514 | update_cr6(db->cr6_data, db->ioaddr); | ||
1515 | |||
1516 | /* 10/100M phyxcer force mode need */ | ||
1517 | if ( !(db->media_mode & 0x8)) { | ||
1518 | /* Forece Mode */ | ||
1519 | phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); | ||
1520 | if ( !(phy_reg & 0x1) ) { | ||
1521 | /* parter without N-Way capability */ | ||
1522 | phy_reg = 0x0; | ||
1523 | switch(db->op_mode) { | ||
1524 | case ULI526X_10MHF: phy_reg = 0x0; break; | ||
1525 | case ULI526X_10MFD: phy_reg = 0x100; break; | ||
1526 | case ULI526X_100MHF: phy_reg = 0x2000; break; | ||
1527 | case ULI526X_100MFD: phy_reg = 0x2100; break; | ||
1528 | } | ||
1529 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); | ||
1530 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); | ||
1531 | } | ||
1532 | } | ||
1533 | } | ||
1534 | |||
1535 | |||
1536 | /* | ||
1537 | * Write a word to Phy register | ||
1538 | */ | ||
1539 | |||
1540 | static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id) | ||
1541 | { | ||
1542 | u16 i; | ||
1543 | unsigned long ioaddr; | ||
1544 | |||
1545 | if(chip_id == PCI_ULI5263_ID) | ||
1546 | { | ||
1547 | phy_writeby_cr10(iobase, phy_addr, offset, phy_data); | ||
1548 | return; | ||
1549 | } | ||
1550 | /* M5261/M5263 Chip */ | ||
1551 | ioaddr = iobase + DCR9; | ||
1552 | |||
1553 | /* Send 33 synchronization clock to Phy controller */ | ||
1554 | for (i = 0; i < 35; i++) | ||
1555 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1556 | |||
1557 | /* Send start command(01) to Phy */ | ||
1558 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | ||
1559 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1560 | |||
1561 | /* Send write command(01) to Phy */ | ||
1562 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | ||
1563 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1564 | |||
1565 | /* Send Phy address */ | ||
1566 | for (i = 0x10; i > 0; i = i >> 1) | ||
1567 | phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | ||
1568 | |||
1569 | /* Send register address */ | ||
1570 | for (i = 0x10; i > 0; i = i >> 1) | ||
1571 | phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | ||
1572 | |||
1573 | /* written trasnition */ | ||
1574 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1575 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | ||
1576 | |||
1577 | /* Write a word data to PHY controller */ | ||
1578 | for ( i = 0x8000; i > 0; i >>= 1) | ||
1579 | phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | ||
1580 | |||
1581 | } | ||
1582 | |||
1583 | |||
1584 | /* | ||
1585 | * Read a word data from phy register | ||
1586 | */ | ||
1587 | |||
1588 | static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id) | ||
1589 | { | ||
1590 | int i; | ||
1591 | u16 phy_data; | ||
1592 | unsigned long ioaddr; | ||
1593 | |||
1594 | if(chip_id == PCI_ULI5263_ID) | ||
1595 | return phy_readby_cr10(iobase, phy_addr, offset); | ||
1596 | /* M5261/M5263 Chip */ | ||
1597 | ioaddr = iobase + DCR9; | ||
1598 | |||
1599 | /* Send 33 synchronization clock to Phy controller */ | ||
1600 | for (i = 0; i < 35; i++) | ||
1601 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1602 | |||
1603 | /* Send start command(01) to Phy */ | ||
1604 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | ||
1605 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1606 | |||
1607 | /* Send read command(10) to Phy */ | ||
1608 | phy_write_1bit(ioaddr, PHY_DATA_1, chip_id); | ||
1609 | phy_write_1bit(ioaddr, PHY_DATA_0, chip_id); | ||
1610 | |||
1611 | /* Send Phy address */ | ||
1612 | for (i = 0x10; i > 0; i = i >> 1) | ||
1613 | phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | ||
1614 | |||
1615 | /* Send register address */ | ||
1616 | for (i = 0x10; i > 0; i = i >> 1) | ||
1617 | phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id); | ||
1618 | |||
1619 | /* Skip transition state */ | ||
1620 | phy_read_1bit(ioaddr, chip_id); | ||
1621 | |||
1622 | /* read 16bit data */ | ||
1623 | for (phy_data = 0, i = 0; i < 16; i++) { | ||
1624 | phy_data <<= 1; | ||
1625 | phy_data |= phy_read_1bit(ioaddr, chip_id); | ||
1626 | } | ||
1627 | |||
1628 | return phy_data; | ||
1629 | } | ||
1630 | |||
1631 | static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset) | ||
1632 | { | ||
1633 | unsigned long ioaddr,cr10_value; | ||
1634 | |||
1635 | ioaddr = iobase + DCR10; | ||
1636 | cr10_value = phy_addr; | ||
1637 | cr10_value = (cr10_value<<5) + offset; | ||
1638 | cr10_value = (cr10_value<<16) + 0x08000000; | ||
1639 | outl(cr10_value,ioaddr); | ||
1640 | udelay(1); | ||
1641 | while(1) | ||
1642 | { | ||
1643 | cr10_value = inl(ioaddr); | ||
1644 | if(cr10_value&0x10000000) | ||
1645 | break; | ||
1646 | } | ||
1647 | return (cr10_value&0x0ffff); | ||
1648 | } | ||
1649 | |||
1650 | static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data) | ||
1651 | { | ||
1652 | unsigned long ioaddr,cr10_value; | ||
1653 | |||
1654 | ioaddr = iobase + DCR10; | ||
1655 | cr10_value = phy_addr; | ||
1656 | cr10_value = (cr10_value<<5) + offset; | ||
1657 | cr10_value = (cr10_value<<16) + 0x04000000 + phy_data; | ||
1658 | outl(cr10_value,ioaddr); | ||
1659 | udelay(1); | ||
1660 | } | ||
1661 | /* | ||
1662 | * Write one bit data to Phy Controller | ||
1663 | */ | ||
1664 | |||
1665 | static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id) | ||
1666 | { | ||
1667 | outl(phy_data , ioaddr); /* MII Clock Low */ | ||
1668 | udelay(1); | ||
1669 | outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */ | ||
1670 | udelay(1); | ||
1671 | outl(phy_data , ioaddr); /* MII Clock Low */ | ||
1672 | udelay(1); | ||
1673 | } | ||
1674 | |||
1675 | |||
1676 | /* | ||
1677 | * Read one bit phy data from PHY controller | ||
1678 | */ | ||
1679 | |||
1680 | static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id) | ||
1681 | { | ||
1682 | u16 phy_data; | ||
1683 | |||
1684 | outl(0x50000 , ioaddr); | ||
1685 | udelay(1); | ||
1686 | phy_data = ( inl(ioaddr) >> 19 ) & 0x1; | ||
1687 | outl(0x40000 , ioaddr); | ||
1688 | udelay(1); | ||
1689 | |||
1690 | return phy_data; | ||
1691 | } | ||
1692 | |||
1693 | |||
1694 | static struct pci_device_id uli526x_pci_tbl[] = { | ||
1695 | { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID }, | ||
1696 | { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID }, | ||
1697 | { 0, } | ||
1698 | }; | ||
1699 | MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl); | ||
1700 | |||
1701 | |||
1702 | static struct pci_driver uli526x_driver = { | ||
1703 | .name = "uli526x", | ||
1704 | .id_table = uli526x_pci_tbl, | ||
1705 | .probe = uli526x_init_one, | ||
1706 | .remove = __devexit_p(uli526x_remove_one), | ||
1707 | }; | ||
1708 | |||
1709 | MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw"); | ||
1710 | MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver"); | ||
1711 | MODULE_LICENSE("GPL"); | ||
1712 | |||
1713 | MODULE_PARM(debug, "i"); | ||
1714 | MODULE_PARM(mode, "i"); | ||
1715 | MODULE_PARM(cr6set, "i"); | ||
1716 | MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)"); | ||
1717 | MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA"); | ||
1718 | |||
1719 | /* Description: | ||
1720 | * when user used insmod to add module, system invoked init_module() | ||
1721 | * to initilize and register. | ||
1722 | */ | ||
1723 | |||
1724 | static int __init uli526x_init_module(void) | ||
1725 | { | ||
1726 | int rc; | ||
1727 | |||
1728 | printk(version); | ||
1729 | printed_version = 1; | ||
1730 | |||
1731 | ULI526X_DBUG(0, "init_module() ", debug); | ||
1732 | |||
1733 | if (debug) | ||
1734 | uli526x_debug = debug; /* set debug flag */ | ||
1735 | if (cr6set) | ||
1736 | uli526x_cr6_user_set = cr6set; | ||
1737 | |||
1738 | switch(mode) { | ||
1739 | case ULI526X_10MHF: | ||
1740 | case ULI526X_100MHF: | ||
1741 | case ULI526X_10MFD: | ||
1742 | case ULI526X_100MFD: | ||
1743 | uli526x_media_mode = mode; | ||
1744 | break; | ||
1745 | default:uli526x_media_mode = ULI526X_AUTO; | ||
1746 | break; | ||
1747 | } | ||
1748 | |||
1749 | rc = pci_module_init(&uli526x_driver); | ||
1750 | if (rc < 0) | ||
1751 | return rc; | ||
1752 | |||
1753 | return 0; | ||
1754 | } | ||
1755 | |||
1756 | |||
1757 | /* | ||
1758 | * Description: | ||
1759 | * when user used rmmod to delete module, system invoked clean_module() | ||
1760 | * to un-register all registered services. | ||
1761 | */ | ||
1762 | |||
1763 | static void __exit uli526x_cleanup_module(void) | ||
1764 | { | ||
1765 | ULI526X_DBUG(0, "uli526x_clean_module() ", debug); | ||
1766 | pci_unregister_driver(&uli526x_driver); | ||
1767 | } | ||
1768 | |||
1769 | module_init(uli526x_init_module); | ||
1770 | module_exit(uli526x_cleanup_module); | ||