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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/sk98lin/skgeinit.c
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/sk98lin/skgeinit.c')
-rw-r--r--drivers/net/sk98lin/skgeinit.c2151
1 files changed, 2151 insertions, 0 deletions
diff --git a/drivers/net/sk98lin/skgeinit.c b/drivers/net/sk98lin/skgeinit.c
new file mode 100644
index 000000000000..df4483429a77
--- /dev/null
+++ b/drivers/net/sk98lin/skgeinit.c
@@ -0,0 +1,2151 @@
1/******************************************************************************
2 *
3 * Name: skgeinit.c
4 * Project: Gigabit Ethernet Adapters, Common Modules
5 * Version: $Revision: 1.97 $
6 * Date: $Date: 2003/10/02 16:45:31 $
7 * Purpose: Contains functions to initialize the adapter
8 *
9 ******************************************************************************/
10
11/******************************************************************************
12 *
13 * (C)Copyright 1998-2002 SysKonnect.
14 * (C)Copyright 2002-2003 Marvell.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * The information in this file is provided "AS IS" without warranty.
22 *
23 ******************************************************************************/
24
25#include "h/skdrv1st.h"
26#include "h/skdrv2nd.h"
27
28/* global variables ***********************************************************/
29
30/* local variables ************************************************************/
31
32#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
33static const char SysKonnectFileId[] =
34 "@(#) $Id: skgeinit.c,v 1.97 2003/10/02 16:45:31 rschmidt Exp $ (C) Marvell.";
35#endif
36
37struct s_QOffTab {
38 int RxQOff; /* Receive Queue Address Offset */
39 int XsQOff; /* Sync Tx Queue Address Offset */
40 int XaQOff; /* Async Tx Queue Address Offset */
41};
42static struct s_QOffTab QOffTab[] = {
43 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
44};
45
46struct s_Config {
47 char ScanString[8];
48 SK_U32 Value;
49};
50
51static struct s_Config OemConfig = {
52 {'O','E','M','_','C','o','n','f'},
53#ifdef SK_OEM_CONFIG
54 OEM_CONFIG_VALUE,
55#else
56 0,
57#endif
58};
59
60/******************************************************************************
61 *
62 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
63 *
64 * Description:
65 * Enable or disable the descriptor polling of the receive descriptor
66 * ring (RxD) for port 'Port'.
67 * The new configuration is *not* saved over any SkGeStopPort() and
68 * SkGeInitPort() calls.
69 *
70 * Returns:
71 * nothing
72 */
73void SkGePollRxD(
74SK_AC *pAC, /* adapter context */
75SK_IOC IoC, /* IO context */
76int Port, /* Port Index (MAC_1 + n) */
77SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
78{
79 SK_GEPORT *pPrt;
80
81 pPrt = &pAC->GIni.GP[Port];
82
83 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ?
84 CSR_ENA_POL : CSR_DIS_POL);
85} /* SkGePollRxD */
86
87
88/******************************************************************************
89 *
90 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
91 *
92 * Description:
93 * Enable or disable the descriptor polling of the transmit descriptor
94 * ring(s) (TxD) for port 'Port'.
95 * The new configuration is *not* saved over any SkGeStopPort() and
96 * SkGeInitPort() calls.
97 *
98 * Returns:
99 * nothing
100 */
101void SkGePollTxD(
102SK_AC *pAC, /* adapter context */
103SK_IOC IoC, /* IO context */
104int Port, /* Port Index (MAC_1 + n) */
105SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
106{
107 SK_GEPORT *pPrt;
108 SK_U32 DWord;
109
110 pPrt = &pAC->GIni.GP[Port];
111
112 DWord = (SK_U32)(PollTxD ? CSR_ENA_POL : CSR_DIS_POL);
113
114 if (pPrt->PXSQSize != 0) {
115 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
116 }
117
118 if (pPrt->PXAQSize != 0) {
119 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
120 }
121} /* SkGePollTxD */
122
123
124/******************************************************************************
125 *
126 * SkGeYellowLED() - Switch the yellow LED on or off.
127 *
128 * Description:
129 * Switch the yellow LED on or off.
130 *
131 * Note:
132 * This function may be called any time after SkGeInit(Level 1).
133 *
134 * Returns:
135 * nothing
136 */
137void SkGeYellowLED(
138SK_AC *pAC, /* adapter context */
139SK_IOC IoC, /* IO context */
140int State) /* yellow LED state, 0 = OFF, 0 != ON */
141{
142 if (State == 0) {
143 /* Switch yellow LED OFF */
144 SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
145 }
146 else {
147 /* Switch yellow LED ON */
148 SK_OUT8(IoC, B0_LED, LED_STAT_ON);
149 }
150} /* SkGeYellowLED */
151
152
153#if (!defined(SK_SLIM) || defined(GENESIS))
154/******************************************************************************
155 *
156 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED.
157 *
158 * Description:
159 * The Rx or Tx LED which is specified by 'Led' will be
160 * enabled, disabled or switched on in test mode.
161 *
162 * Note:
163 * 'Led' must contain the address offset of the LEDs INI register.
164 *
165 * Usage:
166 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
167 *
168 * Returns:
169 * nothing
170 */
171void SkGeXmitLED(
172SK_AC *pAC, /* adapter context */
173SK_IOC IoC, /* IO context */
174int Led, /* offset to the LED Init Value register */
175int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
176{
177 SK_U32 LedIni;
178
179 switch (Mode) {
180 case SK_LED_ENA:
181 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
182 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni);
183 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
184 break;
185 case SK_LED_TST:
186 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON);
187 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100);
188 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START);
189 break;
190 case SK_LED_DIS:
191 default:
192 /*
193 * Do NOT stop the LED Timer here. The LED might be
194 * in on state. But it needs to go off.
195 */
196 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
197 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
198 break;
199 }
200
201 /*
202 * 1000BT: The Transmit LED is driven by the PHY.
203 * But the default LED configuration is used for
204 * Level One and Broadcom PHYs.
205 * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
206 * (In this case it has to be added here. But we will see. XXX)
207 */
208} /* SkGeXmitLED */
209#endif /* !SK_SLIM || GENESIS */
210
211
212/******************************************************************************
213 *
214 * DoCalcAddr() - Calculates the start and the end address of a queue.
215 *
216 * Description:
217 * This function calculates the start and the end address of a queue.
218 * Afterwards the 'StartVal' is incremented to the next start position.
219 * If the port is already initialized the calculated values
220 * will be checked against the configured values and an
221 * error will be returned, if they are not equal.
222 * If the port is not initialized the values will be written to
223 * *StartAdr and *EndAddr.
224 *
225 * Returns:
226 * 0: success
227 * 1: configuration error
228 */
229static int DoCalcAddr(
230SK_AC *pAC, /* adapter context */
231SK_GEPORT SK_FAR *pPrt, /* port index */
232int QuSize, /* size of the queue to configure in kB */
233SK_U32 SK_FAR *StartVal, /* start value for address calculation */
234SK_U32 SK_FAR *QuStartAddr,/* start addr to calculate */
235SK_U32 SK_FAR *QuEndAddr) /* end address to calculate */
236{
237 SK_U32 EndVal;
238 SK_U32 NextStart;
239 int Rtv;
240
241 Rtv = 0;
242 if (QuSize == 0) {
243 EndVal = *StartVal;
244 NextStart = EndVal;
245 }
246 else {
247 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1;
248 NextStart = EndVal + 1;
249 }
250
251 if (pPrt->PState >= SK_PRT_INIT) {
252 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) {
253 Rtv = 1;
254 }
255 }
256 else {
257 *QuStartAddr = *StartVal;
258 *QuEndAddr = EndVal;
259 }
260
261 *StartVal = NextStart;
262 return(Rtv);
263} /* DoCalcAddr */
264
265/******************************************************************************
266 *
267 * SkGeInitAssignRamToQueues() - allocate default queue sizes
268 *
269 * Description:
270 * This function assigns the memory to the different queues and ports.
271 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
272 * Otherwise the first port gets most of the memory and all the
273 * other ports just the required minimum.
274 * This function can only be called when pAC->GIni.GIRamSize and
275 * pAC->GIni.GIMacsFound have been initialized, usually this happens
276 * at init level 1
277 *
278 * Returns:
279 * 0 - ok
280 * 1 - invalid input values
281 * 2 - not enough memory
282 */
283
284int SkGeInitAssignRamToQueues(
285SK_AC *pAC, /* Adapter context */
286int ActivePort, /* Active Port in RLMT mode */
287SK_BOOL DualNet) /* adapter context */
288{
289 int i;
290 int UsedKilobytes; /* memory already assigned */
291 int ActivePortKilobytes; /* memory available for active port */
292 SK_GEPORT *pGePort;
293
294 UsedKilobytes = 0;
295
296 if (ActivePort >= pAC->GIni.GIMacsFound) {
297 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
298 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
299 ActivePort));
300 return(1);
301 }
302 if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
303 ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
304 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
305 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
306 pAC->GIni.GIRamSize));
307 return(2);
308 }
309
310 if (DualNet) {
311 /* every port gets the same amount of memory */
312 ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
313 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
314
315 pGePort = &pAC->GIni.GP[i];
316
317 /* take away the minimum memory for active queues */
318 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
319
320 /* receive queue gets the minimum + 80% of the rest */
321 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
322 ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
323 + SK_MIN_RXQ_SIZE;
324
325 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
326
327 /* synchronous transmit queue */
328 pGePort->PXSQSize = 0;
329
330 /* asynchronous transmit queue */
331 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
332 SK_MIN_TXQ_SIZE);
333 }
334 }
335 else {
336 /* Rlmt Mode or single link adapter */
337
338 /* Set standby queue size defaults for all standby ports */
339 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
340
341 if (i != ActivePort) {
342 pGePort = &pAC->GIni.GP[i];
343
344 pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
345 pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
346 pGePort->PXSQSize = 0;
347
348 /* Count used RAM */
349 UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
350 }
351 }
352 /* what's left? */
353 ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
354
355 /* assign it to the active port */
356 /* first take away the minimum memory */
357 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
358 pGePort = &pAC->GIni.GP[ActivePort];
359
360 /* receive queue get's the minimum + 80% of the rest */
361 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
362 (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
363
364 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
365
366 /* synchronous transmit queue */
367 pGePort->PXSQSize = 0;
368
369 /* asynchronous transmit queue */
370 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
371 SK_MIN_TXQ_SIZE;
372 }
373#ifdef VCPU
374 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
375 pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
376#endif /* VCPU */
377
378 return(0);
379} /* SkGeInitAssignRamToQueues */
380
381/******************************************************************************
382 *
383 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
384 *
385 * Description:
386 * This function verifies the Queue Size Configuration specified
387 * in the variables PRxQSize, PXSQSize, and PXAQSize of all
388 * used ports.
389 * This requirements must be fullfilled to have a valid configuration:
390 * - The size of all queues must not exceed GIRamSize.
391 * - The queue sizes must be specified in units of 8 kB.
392 * - The size of Rx queues of available ports must not be
393 * smaller than 16 kB.
394 * - The size of at least one Tx queue (synch. or asynch.)
395 * of available ports must not be smaller than 16 kB
396 * when Jumbo Frames are used.
397 * - The RAM start and end addresses must not be changed
398 * for ports which are already initialized.
399 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
400 * of all ports and stores them into the HWAC port structure.
401 *
402 * Returns:
403 * 0: Queue Size Configuration valid
404 * 1: Queue Size Configuration invalid
405 */
406static int SkGeCheckQSize(
407SK_AC *pAC, /* adapter context */
408int Port) /* port index */
409{
410 SK_GEPORT *pPrt;
411 int i;
412 int Rtv;
413 int Rtv2;
414 SK_U32 StartAddr;
415#ifndef SK_SLIM
416 int UsedMem; /* total memory used (max. found ports) */
417#endif
418
419 Rtv = 0;
420
421#ifndef SK_SLIM
422
423 UsedMem = 0;
424 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
425 pPrt = &pAC->GIni.GP[i];
426
427 if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
428 (pPrt->PXSQSize & QZ_UNITS) != 0 ||
429 (pPrt->PXAQSize & QZ_UNITS) != 0) {
430
431 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
432 return(1);
433 }
434
435 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
436 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
437 return(1);
438 }
439
440 /*
441 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
442 * if Jumbo Frames are used, this size has to be >= 16 kB.
443 */
444 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
445 (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
446 ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
447 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
448 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
449 return(1);
450 }
451
452 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
453 }
454
455 if (UsedMem > pAC->GIni.GIRamSize) {
456 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
457 return(1);
458 }
459#endif /* !SK_SLIM */
460
461 /* Now start address calculation */
462 StartAddr = pAC->GIni.GIRamOffs;
463 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
464 pPrt = &pAC->GIni.GP[i];
465
466 /* Calculate/Check values for the receive queue */
467 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
468 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
469 Rtv |= Rtv2;
470
471 /* Calculate/Check values for the synchronous Tx queue */
472 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr,
473 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd);
474 Rtv |= Rtv2;
475
476 /* Calculate/Check values for the asynchronous Tx queue */
477 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr,
478 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd);
479 Rtv |= Rtv2;
480
481 if (Rtv) {
482 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG);
483 return(1);
484 }
485 }
486
487 return(0);
488} /* SkGeCheckQSize */
489
490
491#ifdef GENESIS
492/******************************************************************************
493 *
494 * SkGeInitMacArb() - Initialize the MAC Arbiter
495 *
496 * Description:
497 * This function initializes the MAC Arbiter.
498 * It must not be called if there is still an
499 * initialized or active port.
500 *
501 * Returns:
502 * nothing
503 */
504static void SkGeInitMacArb(
505SK_AC *pAC, /* adapter context */
506SK_IOC IoC) /* IO context */
507{
508 /* release local reset */
509 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
510
511 /* configure timeout values */
512 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53);
513 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53);
514 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53);
515 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53);
516
517 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0);
518 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0);
519 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0);
520 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0);
521
522 /* recovery values are needed for XMAC II Rev. B2 only */
523 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */
524
525 /*
526 * There is no start or enable button to push, therefore
527 * the MAC arbiter is configured and enabled now.
528 */
529} /* SkGeInitMacArb */
530
531
532/******************************************************************************
533 *
534 * SkGeInitPktArb() - Initialize the Packet Arbiter
535 *
536 * Description:
537 * This function initializes the Packet Arbiter.
538 * It must not be called if there is still an
539 * initialized or active port.
540 *
541 * Returns:
542 * nothing
543 */
544static void SkGeInitPktArb(
545SK_AC *pAC, /* adapter context */
546SK_IOC IoC) /* IO context */
547{
548 /* release local reset */
549 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
550
551 /* configure timeout values */
552 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
553 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
554 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
555 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
556
557 /*
558 * enable timeout timers if jumbo frames not used
559 * NOTE: the packet arbiter timeout interrupt is needed for
560 * half duplex hangup workaround
561 */
562 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
563 if (pAC->GIni.GIMacsFound == 1) {
564 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
565 }
566 else {
567 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2);
568 }
569 }
570} /* SkGeInitPktArb */
571#endif /* GENESIS */
572
573
574/******************************************************************************
575 *
576 * SkGeInitMacFifo() - Initialize the MAC FIFOs
577 *
578 * Description:
579 * Initialize all MAC FIFOs of the specified port
580 *
581 * Returns:
582 * nothing
583 */
584static void SkGeInitMacFifo(
585SK_AC *pAC, /* adapter context */
586SK_IOC IoC, /* IO context */
587int Port) /* Port Index (MAC_1 + n) */
588{
589 SK_U16 Word;
590#ifdef VCPU
591 SK_U32 DWord;
592#endif /* VCPU */
593 /*
594 * For each FIFO:
595 * - release local reset
596 * - use default value for MAC FIFO size
597 * - setup defaults for the control register
598 * - enable the FIFO
599 */
600
601#ifdef GENESIS
602 if (pAC->GIni.GIGenesis) {
603 /* Configure Rx MAC FIFO */
604 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
605 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
606 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
607
608 /* Configure Tx MAC FIFO */
609 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
610 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
611 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
612
613 /* Enable frame flushing if jumbo frames used */
614 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
615 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
616 }
617 }
618#endif /* GENESIS */
619
620#ifdef YUKON
621 if (pAC->GIni.GIYukon) {
622 /* set Rx GMAC FIFO Flush Mask */
623 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
624
625 Word = (SK_U16)GMF_RX_CTRL_DEF;
626
627 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
628 if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
629
630 Word &= ~GMF_RX_F_FL_ON;
631 }
632
633 /* Configure Rx MAC FIFO */
634 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
635 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
636
637 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
638 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
639
640 /* Configure Tx MAC FIFO */
641 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
642 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
643
644#ifdef VCPU
645 SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
646 SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
647#endif /* VCPU */
648
649 /* set Tx GMAC FIFO Almost Empty Threshold */
650/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
651 }
652#endif /* YUKON */
653
654} /* SkGeInitMacFifo */
655
656#ifdef SK_LNK_SYNC_CNT
657/******************************************************************************
658 *
659 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
660 *
661 * Description:
662 * This function starts the Link Sync Counter of the specified
663 * port and enables the generation of an Link Sync IRQ.
664 * The Link Sync Counter may be used to detect an active link,
665 * if autonegotiation is not used.
666 *
667 * Note:
668 * o To ensure receiving the Link Sync Event the LinkSyncCounter
669 * should be initialized BEFORE clearing the XMAC's reset!
670 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this
671 * function.
672 *
673 * Returns:
674 * nothing
675 */
676void SkGeLoadLnkSyncCnt(
677SK_AC *pAC, /* adapter context */
678SK_IOC IoC, /* IO context */
679int Port, /* Port Index (MAC_1 + n) */
680SK_U32 CntVal) /* Counter value */
681{
682 SK_U32 OrgIMsk;
683 SK_U32 NewIMsk;
684 SK_U32 ISrc;
685 SK_BOOL IrqPend;
686
687 /* stop counter */
688 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
689
690 /*
691 * ASIC problem:
692 * Each time starting the Link Sync Counter an IRQ is generated
693 * by the adapter. See problem report entry from 21.07.98
694 *
695 * Workaround: Disable Link Sync IRQ and clear the unexpeced IRQ
696 * if no IRQ is already pending.
697 */
698 IrqPend = SK_FALSE;
699 SK_IN32(IoC, B0_ISRC, &ISrc);
700 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
701 if (Port == MAC_1) {
702 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
703 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
704 IrqPend = SK_TRUE;
705 }
706 }
707 else {
708 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2;
709 if ((ISrc & IS_LNK_SYNC_M2) != 0) {
710 IrqPend = SK_TRUE;
711 }
712 }
713 if (!IrqPend) {
714 SK_OUT32(IoC, B0_IMSK, NewIMsk);
715 }
716
717 /* load counter */
718 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
719
720 /* start counter */
721 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
722
723 if (!IrqPend) {
724 /* clear the unexpected IRQ, and restore the interrupt mask */
725 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
726 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
727 }
728} /* SkGeLoadLnkSyncCnt*/
729#endif /* SK_LNK_SYNC_CNT */
730
731#if defined(SK_DIAG) || defined(SK_CFG_SYNC)
732/******************************************************************************
733 *
734 * SkGeCfgSync() - Configure synchronous bandwidth for this port.
735 *
736 * Description:
737 * This function may be used to configure synchronous bandwidth
738 * to the specified port. This may be done any time after
739 * initializing the port. The configuration values are NOT saved
740 * in the HWAC port structure and will be overwritten any
741 * time when stopping and starting the port.
742 * Any values for the synchronous configuration will be ignored
743 * if the size of the synchronous queue is zero!
744 *
745 * The default configuration for the synchronous service is
746 * TXA_ENA_FSYNC. This means if the size of
747 * the synchronous queue is unequal zero but no specific
748 * synchronous bandwidth is configured, the synchronous queue
749 * will always have the 'unlimited' transmit priority!
750 *
751 * This mode will be restored if the synchronous bandwidth is
752 * deallocated ('IntTime' = 0 and 'LimCount' = 0).
753 *
754 * Returns:
755 * 0: success
756 * 1: parameter configuration error
757 * 2: try to configure quality of service although no
758 * synchronous queue is configured
759 */
760int SkGeCfgSync(
761SK_AC *pAC, /* adapter context */
762SK_IOC IoC, /* IO context */
763int Port, /* Port Index (MAC_1 + n) */
764SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
765SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
766int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */
767{
768 int Rtv;
769
770 Rtv = 0;
771
772 /* check the parameters */
773 if (LimCount > IntTime ||
774 (LimCount == 0 && IntTime != 0) ||
775 (LimCount != 0 && IntTime == 0)) {
776
777 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
778 return(1);
779 }
780
781 if (pAC->GIni.GP[Port].PXSQSize == 0) {
782 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
783 return(2);
784 }
785
786 /* calculate register values */
787 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
788 LimCount = LimCount / 8;
789
790 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
791 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
792 return(1);
793 }
794
795 /*
796 * - Enable 'Force Sync' to ensure the synchronous queue
797 * has the priority while configuring the new values.
798 * - Also 'disable alloc' to ensure the settings complies
799 * to the SyncMode parameter.
800 * - Disable 'Rate Control' to configure the new values.
801 * - write IntTime and LimCount
802 * - start 'Rate Control' and disable 'Force Sync'
803 * if Interval Timer or Limit Counter not zero.
804 */
805 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
806 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
807
808 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
809 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
810
811 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
812 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
813
814 if (IntTime != 0 || LimCount != 0) {
815 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
816 }
817
818 return(0);
819} /* SkGeCfgSync */
820#endif /* SK_DIAG || SK_CFG_SYNC*/
821
822
823/******************************************************************************
824 *
825 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue
826 *
827 * Desccription:
828 * If the queue is used, enable and initialize it.
829 * Make sure the queue is still reset, if it is not used.
830 *
831 * Returns:
832 * nothing
833 */
834static void DoInitRamQueue(
835SK_AC *pAC, /* adapter context */
836SK_IOC IoC, /* IO context */
837int QuIoOffs, /* Queue IO Address Offset */
838SK_U32 QuStartAddr, /* Queue Start Address */
839SK_U32 QuEndAddr, /* Queue End Address */
840int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
841{
842 SK_U32 RxUpThresVal;
843 SK_U32 RxLoThresVal;
844
845 if (QuStartAddr != QuEndAddr) {
846 /* calculate thresholds, assume we have a big Rx queue */
847 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8;
848 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8;
849
850 /* build HW address format */
851 QuStartAddr = QuStartAddr / 8;
852 QuEndAddr = QuEndAddr / 8;
853
854 /* release local reset */
855 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR);
856
857 /* configure addresses */
858 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr);
859 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr);
860 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr);
861 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr);
862
863 switch (QuType) {
864 case SK_RX_SRAM_Q:
865 /* configure threshold for small Rx Queue */
866 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8;
867
868 /* continue with SK_RX_BRAM_Q */
869 case SK_RX_BRAM_Q:
870 /* write threshold for Rx Queue */
871
872 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
873 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
874
875 /* the high priority threshold not used */
876 break;
877 case SK_TX_RAM_Q:
878 /*
879 * Do NOT use Store & Forward under normal operation due to
880 * performance optimization (GENESIS only).
881 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB)
882 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
883 * we NEED Store & Forward of the RAM buffer.
884 */
885 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
886 pAC->GIni.GIYukon) {
887 /* enable Store & Forward Mode for the Tx Side */
888 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
889 }
890 break;
891 }
892
893 /* set queue operational */
894 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD);
895 }
896 else {
897 /* ensure the queue is still disabled */
898 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET);
899 }
900} /* DoInitRamQueue */
901
902
903/******************************************************************************
904 *
905 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues
906 *
907 * Description:
908 * Initialize all RAM Buffer Queues of the specified port
909 *
910 * Returns:
911 * nothing
912 */
913static void SkGeInitRamBufs(
914SK_AC *pAC, /* adapter context */
915SK_IOC IoC, /* IO context */
916int Port) /* Port Index (MAC_1 + n) */
917{
918 SK_GEPORT *pPrt;
919 int RxQType;
920
921 pPrt = &pAC->GIni.GP[Port];
922
923 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
924 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
925 }
926 else {
927 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
928 }
929
930 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
931 pPrt->PRxQRamEnd, RxQType);
932
933 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
934 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
935
936 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
937 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
938
939} /* SkGeInitRamBufs */
940
941
942/******************************************************************************
943 *
944 * SkGeInitRamIface() - Initialize the RAM Interface
945 *
946 * Description:
947 * This function initializes the Adapters RAM Interface.
948 *
949 * Note:
950 * This function is used in the diagnostics.
951 *
952 * Returns:
953 * nothing
954 */
955void SkGeInitRamIface(
956SK_AC *pAC, /* adapter context */
957SK_IOC IoC) /* IO context */
958{
959 /* release local reset */
960 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
961
962 /* configure timeout values */
963 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
964 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
965 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
966 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
967 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
968 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
969 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
970 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
971 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
972 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
973 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
974 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
975
976} /* SkGeInitRamIface */
977
978
979/******************************************************************************
980 *
981 * SkGeInitBmu() - Initialize the BMU state machines
982 *
983 * Description:
984 * Initialize all BMU state machines of the specified port
985 *
986 * Returns:
987 * nothing
988 */
989static void SkGeInitBmu(
990SK_AC *pAC, /* adapter context */
991SK_IOC IoC, /* IO context */
992int Port) /* Port Index (MAC_1 + n) */
993{
994 SK_GEPORT *pPrt;
995 SK_U32 RxWm;
996 SK_U32 TxWm;
997
998 pPrt = &pAC->GIni.GP[Port];
999
1000 RxWm = SK_BMU_RX_WM;
1001 TxWm = SK_BMU_TX_WM;
1002
1003 if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
1004 /* for better performance */
1005 RxWm /= 2;
1006 TxWm /= 2;
1007 }
1008
1009 /* Rx Queue: Release all local resets and set the watermark */
1010 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
1011 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
1012
1013 /*
1014 * Tx Queue: Release all local resets if the queue is used !
1015 * set watermark
1016 */
1017 if (pPrt->PXSQSize != 0) {
1018 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
1019 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
1020 }
1021
1022 if (pPrt->PXAQSize != 0) {
1023 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
1024 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
1025 }
1026 /*
1027 * Do NOT enable the descriptor poll timers here, because
1028 * the descriptor addresses are not specified yet.
1029 */
1030} /* SkGeInitBmu */
1031
1032
1033/******************************************************************************
1034 *
1035 * TestStopBit() - Test the stop bit of the queue
1036 *
1037 * Description:
1038 * Stopping a queue is not as simple as it seems to be.
1039 * If descriptor polling is enabled, it may happen
1040 * that RX/TX stop is done and SV idle is NOT set.
1041 * In this case we have to issue another stop command.
1042 *
1043 * Returns:
1044 * The queues control status register
1045 */
1046static SK_U32 TestStopBit(
1047SK_AC *pAC, /* Adapter Context */
1048SK_IOC IoC, /* IO Context */
1049int QuIoOffs) /* Queue IO Address Offset */
1050{
1051 SK_U32 QuCsr; /* CSR contents */
1052
1053 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1054
1055 if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
1056 /* Stop Descriptor overridden by start command */
1057 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
1058
1059 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
1060 }
1061
1062 return(QuCsr);
1063} /* TestStopBit */
1064
1065
1066/******************************************************************************
1067 *
1068 * SkGeStopPort() - Stop the Rx/Tx activity of the port 'Port'.
1069 *
1070 * Description:
1071 * After calling this function the descriptor rings and Rx and Tx
1072 * queues of this port may be reconfigured.
1073 *
1074 * It is possible to stop the receive and transmit path separate or
1075 * both together.
1076 *
1077 * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC.
1078 * The receive queue is still active and
1079 * the pending Rx frames may be still transferred
1080 * into the RxD.
1081 * SK_STOP_RX Stop the receive path. The tansmit path
1082 * has to be stopped once before.
1083 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
1084 *
1085 * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
1086 * SK_HARD_RST Resets the MAC and the PHY.
1087 *
1088 * Example:
1089 * 1) A Link Down event was signaled for a port. Therefore the activity
1090 * of this port should be stopped and a hardware reset should be issued
1091 * to enable the workaround of XMAC Errata #2. But the received frames
1092 * should not be discarded.
1093 * ...
1094 * SkGeStopPort(pAC, IoC, Port, SK_STOP_TX, SK_HARD_RST);
1095 * (transfer all pending Rx frames)
1096 * SkGeStopPort(pAC, IoC, Port, SK_STOP_RX, SK_HARD_RST);
1097 * ...
1098 *
1099 * 2) An event was issued which request the driver to switch
1100 * the 'virtual active' link to an other already active port
1101 * as soon as possible. The frames in the receive queue of this
1102 * port may be lost. But the PHY must not be reset during this
1103 * event.
1104 * ...
1105 * SkGeStopPort(pAC, IoC, Port, SK_STOP_ALL, SK_SOFT_RST);
1106 * ...
1107 *
1108 * Extended Description:
1109 * If SK_STOP_TX is set,
1110 * o disable the MAC's receive and transmitter to prevent
1111 * from sending incomplete frames
1112 * o stop the port's transmit queues before terminating the
1113 * BMUs to prevent from performing incomplete PCI cycles
1114 * on the PCI bus
1115 * - The network Rx and Tx activity and PCI Tx transfer is
1116 * disabled now.
1117 * o reset the MAC depending on the RstMode
1118 * o Stop Interval Timer and Limit Counter of Tx Arbiter,
1119 * also disable Force Sync bit and Enable Alloc bit.
1120 * o perform a local reset of the port's Tx path
1121 * - reset the PCI FIFO of the async Tx queue
1122 * - reset the PCI FIFO of the sync Tx queue
1123 * - reset the RAM Buffer async Tx queue
1124 * - reset the RAM Buffer sync Tx queue
1125 * - reset the MAC Tx FIFO
1126 * o switch Link and Tx LED off, stop the LED counters
1127 *
1128 * If SK_STOP_RX is set,
1129 * o stop the port's receive queue
1130 * - The path data transfer activity is fully stopped now.
1131 * o perform a local reset of the port's Rx path
1132 * - reset the PCI FIFO of the Rx queue
1133 * - reset the RAM Buffer receive queue
1134 * - reset the MAC Rx FIFO
1135 * o switch Rx LED off, stop the LED counter
1136 *
1137 * If all ports are stopped,
1138 * o reset the RAM Interface.
1139 *
1140 * Notes:
1141 * o This function may be called during the driver states RESET_PORT and
1142 * SWITCH_PORT.
1143 */
1144void SkGeStopPort(
1145SK_AC *pAC, /* adapter context */
1146SK_IOC IoC, /* I/O context */
1147int Port, /* port to stop (MAC_1 + n) */
1148int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
1149int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
1150{
1151#ifndef SK_DIAG
1152 SK_EVPARA Para;
1153#endif /* !SK_DIAG */
1154 SK_GEPORT *pPrt;
1155 SK_U32 DWord;
1156 SK_U32 XsCsr;
1157 SK_U32 XaCsr;
1158 SK_U64 ToutStart;
1159 int i;
1160 int ToutCnt;
1161
1162 pPrt = &pAC->GIni.GP[Port];
1163
1164 if ((Dir & SK_STOP_TX) != 0) {
1165 /* disable receiver and transmitter */
1166 SkMacRxTxDisable(pAC, IoC, Port);
1167
1168 /* stop both transmit queues */
1169 /*
1170 * If the BMU is in the reset state CSR_STOP will terminate
1171 * immediately.
1172 */
1173 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
1174 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
1175
1176 ToutStart = SkOsGetTime(pAC);
1177 ToutCnt = 0;
1178 do {
1179 /*
1180 * Clear packet arbiter timeout to make sure
1181 * this loop will terminate.
1182 */
1183 SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
1184 PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
1185
1186 /*
1187 * If the transfer stucks at the MAC the STOP command will not
1188 * terminate if we don't flush the XMAC's transmit FIFO !
1189 */
1190 SkMacFlushTxFifo(pAC, IoC, Port);
1191
1192 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
1193 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
1194
1195 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
1196 /*
1197 * Timeout of 1/18 second reached.
1198 * This needs to be checked at 1/18 sec only.
1199 */
1200 ToutCnt++;
1201 if (ToutCnt > 1) {
1202 /* Might be a problem when the driver event handler
1203 * calls StopPort again. XXX.
1204 */
1205
1206 /* Fatal Error, Loop aborted */
1207 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
1208 SKERR_HWI_E018MSG);
1209#ifndef SK_DIAG
1210 Para.Para64 = Port;
1211 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
1212#endif /* !SK_DIAG */
1213 return;
1214 }
1215 /*
1216 * Cache incoherency workaround: Assume a start command
1217 * has been lost while sending the frame.
1218 */
1219 ToutStart = SkOsGetTime(pAC);
1220
1221 if ((XsCsr & CSR_STOP) != 0) {
1222 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
1223 }
1224 if ((XaCsr & CSR_STOP) != 0) {
1225 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
1226 }
1227 }
1228
1229 /*
1230 * Because of the ASIC problem report entry from 21.08.1998 it is
1231 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
1232 */
1233 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
1234 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1235
1236 /* Reset the MAC depending on the RstMode */
1237 if (RstMode == SK_SOFT_RST) {
1238 SkMacSoftRst(pAC, IoC, Port);
1239 }
1240 else {
1241 SkMacHardRst(pAC, IoC, Port);
1242 }
1243
1244 /* Disable Force Sync bit and Enable Alloc bit */
1245 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
1246 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1247
1248 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1249 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
1250 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
1251
1252 /* Perform a local reset of the port's Tx path */
1253
1254 /* Reset the PCI FIFO of the async Tx queue */
1255 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
1256 /* Reset the PCI FIFO of the sync Tx queue */
1257 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
1258 /* Reset the RAM Buffer async Tx queue */
1259 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
1260 /* Reset the RAM Buffer sync Tx queue */
1261 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
1262
1263 /* Reset Tx MAC FIFO */
1264#ifdef GENESIS
1265 if (pAC->GIni.GIGenesis) {
1266 /* Note: MFF_RST_SET does NOT reset the XMAC ! */
1267 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET);
1268
1269 /* switch Link and Tx LED off, stop the LED counters */
1270 /* Link LED is switched off by the RLMT and the Diag itself */
1271 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
1272 }
1273#endif /* GENESIS */
1274
1275#ifdef YUKON
1276 if (pAC->GIni.GIYukon) {
1277 /* Reset TX MAC FIFO */
1278 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1279 }
1280#endif /* YUKON */
1281 }
1282
1283 if ((Dir & SK_STOP_RX) != 0) {
1284 /*
1285 * The RX Stop Command will not terminate if no buffers
1286 * are queued in the RxD ring. But it will always reach
1287 * the Idle state. Therefore we can use this feature to
1288 * stop the transfer of received packets.
1289 */
1290 /* stop the port's receive queue */
1291 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
1292
1293 i = 100;
1294 do {
1295 /*
1296 * Clear packet arbiter timeout to make sure
1297 * this loop will terminate
1298 */
1299 SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
1300 PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
1301
1302 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
1303
1304 /* timeout if i==0 (bug fix for #10748) */
1305 if (--i == 0) {
1306 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
1307 SKERR_HWI_E024MSG);
1308 break;
1309 }
1310 /*
1311 * because of the ASIC problem report entry from 21.08.98
1312 * it is required to wait until CSR_STOP is reset and
1313 * CSR_SV_IDLE is set.
1314 */
1315 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
1316
1317 /* The path data transfer activity is fully stopped now */
1318
1319 /* Perform a local reset of the port's Rx path */
1320
1321 /* Reset the PCI FIFO of the Rx queue */
1322 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
1323 /* Reset the RAM Buffer receive queue */
1324 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
1325
1326 /* Reset Rx MAC FIFO */
1327#ifdef GENESIS
1328 if (pAC->GIni.GIGenesis) {
1329
1330 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
1331
1332 /* switch Rx LED off, stop the LED counter */
1333 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
1334 }
1335#endif /* GENESIS */
1336
1337#ifdef YUKON
1338 if (pAC->GIni.GIYukon) {
1339 /* Reset Rx MAC FIFO */
1340 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
1341 }
1342#endif /* YUKON */
1343 }
1344} /* SkGeStopPort */
1345
1346
1347/******************************************************************************
1348 *
1349 * SkGeInit0() - Level 0 Initialization
1350 *
1351 * Description:
1352 * - Initialize the BMU address offsets
1353 *
1354 * Returns:
1355 * nothing
1356 */
1357static void SkGeInit0(
1358SK_AC *pAC, /* adapter context */
1359SK_IOC IoC) /* IO context */
1360{
1361 int i;
1362 SK_GEPORT *pPrt;
1363
1364 for (i = 0; i < SK_MAX_MACS; i++) {
1365 pPrt = &pAC->GIni.GP[i];
1366
1367 pPrt->PState = SK_PRT_RESET;
1368 pPrt->PRxQOff = QOffTab[i].RxQOff;
1369 pPrt->PXsQOff = QOffTab[i].XsQOff;
1370 pPrt->PXaQOff = QOffTab[i].XaQOff;
1371 pPrt->PCheckPar = SK_FALSE;
1372 pPrt->PIsave = 0;
1373 pPrt->PPrevShorts = 0;
1374 pPrt->PLinkResCt = 0;
1375 pPrt->PAutoNegTOCt = 0;
1376 pPrt->PPrevRx = 0;
1377 pPrt->PPrevFcs = 0;
1378 pPrt->PRxLim = SK_DEF_RX_WA_LIM;
1379 pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL;
1380 pPrt->PLinkSpeedCap = (SK_U8)SK_LSPEED_CAP_1000MBPS;
1381 pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_1000MBPS;
1382 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_UNKNOWN;
1383 pPrt->PLinkModeConf = (SK_U8)SK_LMODE_AUTOSENSE;
1384 pPrt->PFlowCtrlMode = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
1385 pPrt->PLinkCap = (SK_U8)(SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL |
1386 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL);
1387 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
1388 pPrt->PFlowCtrlCap = (SK_U8)SK_FLOW_MODE_SYM_OR_REM;
1389 pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
1390 pPrt->PMSCap = 0;
1391 pPrt->PMSMode = (SK_U8)SK_MS_MODE_AUTO;
1392 pPrt->PMSStatus = (SK_U8)SK_MS_STAT_UNSET;
1393 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
1394 pPrt->PAutoNegFail = SK_FALSE;
1395 pPrt->PHWLinkUp = SK_FALSE;
1396 pPrt->PLinkBroken = SK_TRUE; /* See WA code */
1397 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
1398 pPrt->PMacColThres = TX_COL_DEF;
1399 pPrt->PMacJamLen = TX_JAM_LEN_DEF;
1400 pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
1401 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
1402 pPrt->PMacIpgData = IPG_DATA_DEF;
1403 pPrt->PMacLimit4 = SK_FALSE;
1404 }
1405
1406 pAC->GIni.GIPortUsage = SK_RED_LINK;
1407 pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
1408 pAC->GIni.GIValIrqMask = IS_ALL_MSK;
1409
1410} /* SkGeInit0*/
1411
1412#ifdef SK_PCI_RESET
1413
1414/******************************************************************************
1415 *
1416 * SkGePciReset() - Reset PCI interface
1417 *
1418 * Description:
1419 * o Read PCI configuration.
1420 * o Change power state to 3.
1421 * o Change power state to 0.
1422 * o Restore PCI configuration.
1423 *
1424 * Returns:
1425 * 0: Success.
1426 * 1: Power state could not be changed to 3.
1427 */
1428static int SkGePciReset(
1429SK_AC *pAC, /* adapter context */
1430SK_IOC IoC) /* IO context */
1431{
1432 int i;
1433 SK_U16 PmCtlSts;
1434 SK_U32 Bp1;
1435 SK_U32 Bp2;
1436 SK_U16 PciCmd;
1437 SK_U8 Cls;
1438 SK_U8 Lat;
1439 SK_U8 ConfigSpace[PCI_CFG_SIZE];
1440
1441 /*
1442 * Note: Switching to D3 state is like a software reset.
1443 * Switching from D3 to D0 is a hardware reset.
1444 * We have to save and restore the configuration space.
1445 */
1446 for (i = 0; i < PCI_CFG_SIZE; i++) {
1447 SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
1448 }
1449
1450 /* We know the RAM Interface Arbiter is enabled. */
1451 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
1452 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1453
1454 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
1455 return(1);
1456 }
1457
1458 /* Return to D0 state. */
1459 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
1460
1461 /* Check for D0 state. */
1462 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
1463
1464 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
1465 return(1);
1466 }
1467
1468 /* Check PCI Config Registers. */
1469 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
1470 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
1471 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
1472 SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
1473 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
1474
1475 if (PciCmd != 0 || Cls != (SK_U8)0 || Lat != (SK_U8)0 ||
1476 (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1) {
1477 return(1);
1478 }
1479
1480 /* Restore PCI Config Space. */
1481 for (i = 0; i < PCI_CFG_SIZE; i++) {
1482 SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
1483 }
1484
1485 return(0);
1486} /* SkGePciReset */
1487
1488#endif /* SK_PCI_RESET */
1489
1490/******************************************************************************
1491 *
1492 * SkGeInit1() - Level 1 Initialization
1493 *
1494 * Description:
1495 * o Do a software reset.
1496 * o Clear all reset bits.
1497 * o Verify that the detected hardware is present.
1498 * Return an error if not.
1499 * o Get the hardware configuration
1500 * + Read the number of MACs/Ports.
1501 * + Read the RAM size.
1502 * + Read the PCI Revision Id.
1503 * + Find out the adapters host clock speed
1504 * + Read and check the PHY type
1505 *
1506 * Returns:
1507 * 0: success
1508 * 5: Unexpected PHY type detected
1509 * 6: HW self test failed
1510 */
1511static int SkGeInit1(
1512SK_AC *pAC, /* adapter context */
1513SK_IOC IoC) /* IO context */
1514{
1515 SK_U8 Byte;
1516 SK_U16 Word;
1517 SK_U16 CtrlStat;
1518 SK_U32 DWord;
1519 int RetVal;
1520 int i;
1521
1522 RetVal = 0;
1523
1524 /* save CLK_RUN bits (YUKON-Lite) */
1525 SK_IN16(IoC, B0_CTST, &CtrlStat);
1526
1527#ifdef SK_PCI_RESET
1528 (void)SkGePciReset(pAC, IoC);
1529#endif /* SK_PCI_RESET */
1530
1531 /* do the SW-reset */
1532 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
1533
1534 /* release the SW-reset */
1535 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
1536
1537 /* reset all error bits in the PCI STATUS register */
1538 /*
1539 * Note: PCI Cfg cycles cannot be used, because they are not
1540 * available on some platforms after 'boot time'.
1541 */
1542 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
1543
1544 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1545 SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
1546 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1547
1548 /* release Master Reset */
1549 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
1550
1551#ifdef CLK_RUN
1552 CtrlStat |= CS_CLK_RUN_ENA;
1553#endif /* CLK_RUN */
1554
1555 /* restore CLK_RUN bits */
1556 SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
1557 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
1558
1559 /* read Chip Identification Number */
1560 SK_IN8(IoC, B2_CHIP_ID, &Byte);
1561 pAC->GIni.GIChipId = Byte;
1562
1563 /* read number of MACs */
1564 SK_IN8(IoC, B2_MAC_CFG, &Byte);
1565 pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
1566
1567 /* get Chip Revision Number */
1568 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
1569
1570 /* get diff. PCI parameters */
1571 SK_IN16(IoC, B0_CTST, &CtrlStat);
1572
1573 /* read the adapters RAM size */
1574 SK_IN8(IoC, B2_E_0, &Byte);
1575
1576 pAC->GIni.GIGenesis = SK_FALSE;
1577 pAC->GIni.GIYukon = SK_FALSE;
1578 pAC->GIni.GIYukonLite = SK_FALSE;
1579
1580#ifdef GENESIS
1581 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
1582
1583 pAC->GIni.GIGenesis = SK_TRUE;
1584
1585 if (Byte == (SK_U8)3) {
1586 /* special case: 4 x 64k x 36, offset = 0x80000 */
1587 pAC->GIni.GIRamSize = 1024;
1588 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
1589 }
1590 else {
1591 pAC->GIni.GIRamSize = (int)Byte * 512;
1592 pAC->GIni.GIRamOffs = 0;
1593 }
1594 /* all GE adapters work with 53.125 MHz host clock */
1595 pAC->GIni.GIHstClkFact = SK_FACT_53;
1596
1597 /* set Descr. Poll Timer Init Value to 250 ms */
1598 pAC->GIni.GIPollTimerVal =
1599 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1600 }
1601#endif /* GENESIS */
1602
1603#ifdef YUKON
1604 if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
1605
1606 pAC->GIni.GIYukon = SK_TRUE;
1607
1608 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
1609
1610 pAC->GIni.GIRamOffs = 0;
1611
1612 /* WA for chip Rev. A */
1613 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON &&
1614 pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
1615
1616 /* get PM Capabilities of PCI config space */
1617 SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
1618
1619 /* check if VAUX is available */
1620 if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
1621 /* check also if PME from D3cold is set */
1622 ((Word & PCI_PME_D3C_SUP) != 0)) {
1623 /* set entry in GE init struct */
1624 pAC->GIni.GIVauxAvail = SK_TRUE;
1625 }
1626
1627 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
1628 /* this is Rev. A1 */
1629 pAC->GIni.GIYukonLite = SK_TRUE;
1630 }
1631 else {
1632 /* save Flash-Address Register */
1633 SK_IN32(IoC, B2_FAR, &DWord);
1634
1635 /* test Flash-Address Register */
1636 SK_OUT8(IoC, B2_FAR + 3, 0xff);
1637 SK_IN8(IoC, B2_FAR + 3, &Byte);
1638
1639 if (Byte != 0) {
1640 /* this is Rev. A0 */
1641 pAC->GIni.GIYukonLite = SK_TRUE;
1642
1643 /* restore Flash-Address Register */
1644 SK_OUT32(IoC, B2_FAR, DWord);
1645 }
1646 }
1647
1648 /* switch power to VCC (WA for VAUX problem) */
1649 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
1650 PC_VAUX_OFF | PC_VCC_ON));
1651
1652 /* read the Interrupt source */
1653 SK_IN32(IoC, B0_ISRC, &DWord);
1654
1655 if ((DWord & IS_HW_ERR) != 0) {
1656 /* read the HW Error Interrupt source */
1657 SK_IN32(IoC, B0_HWE_ISRC, &DWord);
1658
1659 if ((DWord & IS_IRQ_SENSOR) != 0) {
1660 /* disable HW Error IRQ */
1661 pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
1662 }
1663 }
1664
1665 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1666 /* set GMAC Link Control reset */
1667 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1668
1669 /* clear GMAC Link Control reset */
1670 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1671 }
1672 /* all YU chips work with 78.125 MHz host clock */
1673 pAC->GIni.GIHstClkFact = SK_FACT_78;
1674
1675 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
1676 }
1677#endif /* YUKON */
1678
1679 /* check if 64-bit PCI Slot is present */
1680 pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
1681
1682 /* check if 66 MHz PCI Clock is active */
1683 pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
1684
1685 /* read PCI HW Revision Id. */
1686 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
1687 pAC->GIni.GIPciHwRev = Byte;
1688
1689 /* read the PMD type */
1690 SK_IN8(IoC, B2_PMD_TYP, &Byte);
1691 pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
1692
1693 /* read the PHY type */
1694 SK_IN8(IoC, B2_E_1, &Byte);
1695
1696 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
1697 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1698
1699#ifdef GENESIS
1700 if (pAC->GIni.GIGenesis) {
1701 switch (Byte) {
1702 case SK_PHY_XMAC:
1703 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
1704 break;
1705 case SK_PHY_BCOM:
1706 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
1707 pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
1708 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
1709 break;
1710#ifdef OTHER_PHY
1711 case SK_PHY_LONE:
1712 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
1713 break;
1714 case SK_PHY_NAT:
1715 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
1716 break;
1717#endif /* OTHER_PHY */
1718 default:
1719 /* ERROR: unexpected PHY type detected */
1720 RetVal = 5;
1721 break;
1722 }
1723 }
1724#endif /* GENESIS */
1725
1726#ifdef YUKON
1727 if (pAC->GIni.GIYukon) {
1728
1729 if (Byte < (SK_U8)SK_PHY_MARV_COPPER) {
1730 /* if this field is not initialized */
1731 Byte = (SK_U8)SK_PHY_MARV_COPPER;
1732
1733 pAC->GIni.GICopperType = SK_TRUE;
1734 }
1735
1736 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
1737
1738 if (pAC->GIni.GICopperType) {
1739
1740 pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO |
1741 SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
1742 SK_LSPEED_CAP_1000MBPS);
1743
1744 pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
1745
1746 pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
1747 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
1748 }
1749 else {
1750 Byte = (SK_U8)SK_PHY_MARV_FIBER;
1751 }
1752 }
1753#endif /* YUKON */
1754
1755 pAC->GIni.GP[i].PhyType = (int)Byte;
1756
1757 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
1758 ("PHY type: %d PHY addr: %04x\n", Byte,
1759 pAC->GIni.GP[i].PhyAddr));
1760 }
1761
1762 /* get MAC Type & set function pointers dependent on */
1763#ifdef GENESIS
1764 if (pAC->GIni.GIGenesis) {
1765
1766 pAC->GIni.GIMacType = SK_MAC_XMAC;
1767
1768 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
1769 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
1770 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
1771 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
1772 }
1773#endif /* GENESIS */
1774
1775#ifdef YUKON
1776 if (pAC->GIni.GIYukon) {
1777
1778 pAC->GIni.GIMacType = SK_MAC_GMAC;
1779
1780 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
1781 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
1782 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
1783 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
1784
1785#ifdef SPECIAL_HANDLING
1786 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
1787 /* check HW self test result */
1788 SK_IN8(IoC, B2_E_3, &Byte);
1789 if (Byte & B2_E3_RES_MASK) {
1790 RetVal = 6;
1791 }
1792 }
1793#endif
1794 }
1795#endif /* YUKON */
1796
1797 return(RetVal);
1798} /* SkGeInit1 */
1799
1800
1801/******************************************************************************
1802 *
1803 * SkGeInit2() - Level 2 Initialization
1804 *
1805 * Description:
1806 * - start the Blink Source Counter
1807 * - start the Descriptor Poll Timer
1808 * - configure the MAC-Arbiter
1809 * - configure the Packet-Arbiter
1810 * - enable the Tx Arbiters
1811 * - enable the RAM Interface Arbiter
1812 *
1813 * Returns:
1814 * nothing
1815 */
1816static void SkGeInit2(
1817SK_AC *pAC, /* adapter context */
1818SK_IOC IoC) /* IO context */
1819{
1820#ifdef GENESIS
1821 SK_U32 DWord;
1822#endif /* GENESIS */
1823 int i;
1824
1825 /* start the Descriptor Poll Timer */
1826 if (pAC->GIni.GIPollTimerVal != 0) {
1827 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) {
1828 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;
1829
1830 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
1831 }
1832 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
1833 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
1834 }
1835
1836#ifdef GENESIS
1837 if (pAC->GIni.GIGenesis) {
1838 /* start the Blink Source Counter */
1839 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
1840
1841 SK_OUT32(IoC, B2_BSC_INI, DWord);
1842 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
1843
1844 /*
1845 * Configure the MAC Arbiter and the Packet Arbiter.
1846 * They will be started once and never be stopped.
1847 */
1848 SkGeInitMacArb(pAC, IoC);
1849
1850 SkGeInitPktArb(pAC, IoC);
1851 }
1852#endif /* GENESIS */
1853
1854#ifdef YUKON
1855 if (pAC->GIni.GIYukon) {
1856 /* start Time Stamp Timer */
1857 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
1858 }
1859#endif /* YUKON */
1860
1861 /* enable the Tx Arbiters */
1862 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
1863 SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB);
1864 }
1865
1866 /* enable the RAM Interface Arbiter */
1867 SkGeInitRamIface(pAC, IoC);
1868
1869} /* SkGeInit2 */
1870
1871/******************************************************************************
1872 *
1873 * SkGeInit() - Initialize the GE Adapter with the specified level.
1874 *
1875 * Description:
1876 * Level 0: Initialize the Module structures.
1877 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has
1878 * to be set before calling this level.
1879 *
1880 * o Do a software reset.
1881 * o Clear all reset bits.
1882 * o Verify that the detected hardware is present.
1883 * Return an error if not.
1884 * o Get the hardware configuration
1885 * + Set GIMacsFound with the number of MACs.
1886 * + Store the RAM size in GIRamSize.
1887 * + Save the PCI Revision ID in GIPciHwRev.
1888 * o return an error
1889 * if Number of MACs > SK_MAX_MACS
1890 *
1891 * After returning from Level 0 the adapter
1892 * may be accessed with IO operations.
1893 *
1894 * Level 2: start the Blink Source Counter
1895 *
1896 * Returns:
1897 * 0: success
1898 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
1899 * 2: Adapter not present or not accessible
1900 * 3: Illegal initialization level
1901 * 4: Initialization Level 1 Call missing
1902 * 5: Unexpected PHY type detected
1903 * 6: HW self test failed
1904 */
1905int SkGeInit(
1906SK_AC *pAC, /* adapter context */
1907SK_IOC IoC, /* IO context */
1908int Level) /* initialization level */
1909{
1910 int RetVal; /* return value */
1911 SK_U32 DWord;
1912
1913 RetVal = 0;
1914 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
1915 ("SkGeInit(Level %d)\n", Level));
1916
1917 switch (Level) {
1918 case SK_INIT_DATA:
1919 /* Initialization Level 0 */
1920 SkGeInit0(pAC, IoC);
1921 pAC->GIni.GILevel = SK_INIT_DATA;
1922 break;
1923
1924 case SK_INIT_IO:
1925 /* Initialization Level 1 */
1926 RetVal = SkGeInit1(pAC, IoC);
1927 if (RetVal != 0) {
1928 break;
1929 }
1930
1931 /* check if the adapter seems to be accessible */
1932 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
1933 SK_IN32(IoC, B2_IRQM_INI, &DWord);
1934 SK_OUT32(IoC, B2_IRQM_INI, 0L);
1935
1936 if (DWord != SK_TEST_VAL) {
1937 RetVal = 2;
1938 break;
1939 }
1940
1941 /* check if the number of GIMacsFound matches SK_MAX_MACS */
1942 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
1943 RetVal = 1;
1944 break;
1945 }
1946
1947 /* Level 1 successfully passed */
1948 pAC->GIni.GILevel = SK_INIT_IO;
1949 break;
1950
1951 case SK_INIT_RUN:
1952 /* Initialization Level 2 */
1953 if (pAC->GIni.GILevel != SK_INIT_IO) {
1954#ifndef SK_DIAG
1955 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG);
1956#endif /* !SK_DIAG */
1957 RetVal = 4;
1958 break;
1959 }
1960 SkGeInit2(pAC, IoC);
1961
1962 /* Level 2 successfully passed */
1963 pAC->GIni.GILevel = SK_INIT_RUN;
1964 break;
1965
1966 default:
1967 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
1968 RetVal = 3;
1969 break;
1970 }
1971
1972 return(RetVal);
1973} /* SkGeInit */
1974
1975
1976/******************************************************************************
1977 *
1978 * SkGeDeInit() - Deinitialize the adapter
1979 *
1980 * Description:
1981 * All ports of the adapter will be stopped if not already done.
1982 * Do a software reset and switch off all LEDs.
1983 *
1984 * Returns:
1985 * nothing
1986 */
1987void SkGeDeInit(
1988SK_AC *pAC, /* adapter context */
1989SK_IOC IoC) /* IO context */
1990{
1991 int i;
1992 SK_U16 Word;
1993
1994#ifdef SK_PHY_LP_MODE
1995 SK_U8 Byte;
1996 SK_U16 PmCtlSts;
1997#endif /* SK_PHY_LP_MODE */
1998
1999#if (!defined(SK_SLIM) && !defined(VCPU))
2000 /* ensure I2C is ready */
2001 SkI2cWaitIrq(pAC, IoC);
2002#endif
2003
2004 /* stop all current transfer activity */
2005 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2006 if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
2007 pAC->GIni.GP[i].PState != SK_PRT_RESET) {
2008
2009 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
2010 }
2011 }
2012
2013#ifdef SK_PHY_LP_MODE
2014 /*
2015 * for power saving purposes within mobile environments
2016 * we set the PHY to coma mode and switch to D3 power state.
2017 */
2018 if (pAC->GIni.GIYukonLite &&
2019 pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
2020
2021 /* for all ports switch PHY to coma mode */
2022 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
2023
2024 SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
2025 }
2026
2027 if (pAC->GIni.GIVauxAvail) {
2028 /* switch power to VAUX */
2029 Byte = PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF;
2030
2031 SK_OUT8(IoC, B0_POWER_CTRL, Byte);
2032 }
2033
2034 /* switch to D3 state */
2035 SK_IN16(IoC, PCI_C(PCI_PM_CTL_STS), &PmCtlSts);
2036
2037 PmCtlSts |= PCI_PM_STATE_D3;
2038
2039 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2040
2041 SK_OUT16(IoC, PCI_C(PCI_PM_CTL_STS), PmCtlSts);
2042 }
2043#endif /* SK_PHY_LP_MODE */
2044
2045 /* Reset all bits in the PCI STATUS register */
2046 /*
2047 * Note: PCI Cfg cycles cannot be used, because they are not
2048 * available on some platforms after 'boot time'.
2049 */
2050 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
2051
2052 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2053 SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
2054 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2055
2056 /* do the reset, all LEDs are switched off now */
2057 SK_OUT8(IoC, B0_CTST, CS_RST_SET);
2058
2059 pAC->GIni.GILevel = SK_INIT_DATA;
2060} /* SkGeDeInit */
2061
2062
2063/******************************************************************************
2064 *
2065 * SkGeInitPort() Initialize the specified port.
2066 *
2067 * Description:
2068 * PRxQSize, PXSQSize, and PXAQSize has to be
2069 * configured for the specified port before calling this function.
2070 * The descriptor rings has to be initialized too.
2071 *
2072 * o (Re)configure queues of the specified port.
2073 * o configure the MAC of the specified port.
2074 * o put ASIC and MAC(s) in operational mode.
2075 * o initialize Rx/Tx and Sync LED
2076 * o initialize RAM Buffers and MAC FIFOs
2077 *
2078 * The port is ready to connect when returning.
2079 *
2080 * Note:
2081 * The MAC's Rx and Tx state machine is still disabled when returning.
2082 *
2083 * Returns:
2084 * 0: success
2085 * 1: Queue size initialization error. The configured values
2086 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one
2087 * or more queues. The specified port was NOT initialized.
2088 * An error log entry was generated.
2089 * 2: The port has to be stopped before it can be initialized again.
2090 */
2091int SkGeInitPort(
2092SK_AC *pAC, /* adapter context */
2093SK_IOC IoC, /* IO context */
2094int Port) /* Port to configure */
2095{
2096 SK_GEPORT *pPrt;
2097
2098 pPrt = &pAC->GIni.GP[Port];
2099
2100 if (SkGeCheckQSize(pAC, Port) != 0) {
2101 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
2102 return(1);
2103 }
2104
2105 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
2106 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
2107 return(2);
2108 }
2109
2110 /* configuration ok, initialize the Port now */
2111
2112#ifdef GENESIS
2113 if (pAC->GIni.GIGenesis) {
2114 /* initialize Rx, Tx and Link LED */
2115 /*
2116 * If 1000BT Phy needs LED initialization than swap
2117 * LED and XMAC initialization order
2118 */
2119 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
2120 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
2121 /* The Link LED is initialized by RLMT or Diagnostics itself */
2122
2123 SkXmInitMac(pAC, IoC, Port);
2124 }
2125#endif /* GENESIS */
2126
2127#ifdef YUKON
2128 if (pAC->GIni.GIYukon) {
2129
2130 SkGmInitMac(pAC, IoC, Port);
2131 }
2132#endif /* YUKON */
2133
2134 /* do NOT initialize the Link Sync Counter */
2135
2136 SkGeInitMacFifo(pAC, IoC, Port);
2137
2138 SkGeInitRamBufs(pAC, IoC, Port);
2139
2140 if (pPrt->PXSQSize != 0) {
2141 /* enable Force Sync bit if synchronous queue available */
2142 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
2143 }
2144
2145 SkGeInitBmu(pAC, IoC, Port);
2146
2147 /* mark port as initialized */
2148 pPrt->PState = SK_PRT_INIT;
2149
2150 return(0);
2151} /* SkGeInitPort */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:42:00 -0500