sfc: Update hardware definitions for Siena

Siena is still based on the Falcon hardware architecture and will
share many of these definitions, so replace falcon_hwdefs.h with
regs.h.

The new definitions have been generated according to a naming
convention which incorporates the type and revision information.
Update the code accordingly.

Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/net/sfc/falcon_boards.c b/drivers/net/sfc/falcon_boards.c
index ab940756ac73..68ca45c5d5da 100644
--- a/drivers/net/sfc/falcon_boards.c
+++ b/drivers/net/sfc/falcon_boards.c
@@ -13,7 +13,7 @@
 #include "phy.h"
 #include "efx.h"
 #include "falcon.h"
-#include "falcon_hwdefs.h"
+#include "regs.h"
 #include "falcon_io.h"
 #include "workarounds.h"
 
@@ -332,14 +332,14 @@ static int sfn4111t_reset(struct efx_nic *efx)
          * FLASH_CFG_1 strap (GPIO 3) appropriately.  Only change the
          * output enables; the output levels should always be 0 (low)
          * and we rely on external pull-ups. */
-        falcon_read(efx, &reg, GPIO_CTL_REG_KER);
-        EFX_SET_OWORD_FIELD(reg, GPIO2_OEN, true);
-        falcon_write(efx, &reg, GPIO_CTL_REG_KER);
+        falcon_read(efx, &reg, FR_AB_GPIO_CTL);
+        EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);
+        falcon_write(efx, &reg, FR_AB_GPIO_CTL);
         msleep(1000);
-        EFX_SET_OWORD_FIELD(reg, GPIO2_OEN, false);
-        EFX_SET_OWORD_FIELD(reg, GPIO3_OEN,
+        EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);
+        EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,
                             !!(efx->phy_mode & PHY_MODE_SPECIAL));
-        falcon_write(efx, &reg, GPIO_CTL_REG_KER);
+        falcon_write(efx, &reg, FR_AB_GPIO_CTL);
         msleep(1);
 
         mutex_unlock(&efx->i2c_adap.bus_lock);